UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`ADVANCED MICRO DEVICES, INC.
`Petitioner
`
`v.
`
`BROADCOM CORPORATION
`Patent Owner
`____________
`
`Case No. Unassigned
`Patent 7,720,294
`____________
`
`
`
`PETITION FOR INTER PARTES REVIEW OF CLAIMS 1-3 AND 9-11 OF U.S.
`PATENT NO. 7,720,294
`
`
`
`
`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`
`
`TABLE OF CONTENTS
`
`Page
`
`INTRODUCTION ............................................................................................... 1
`I.
`II. MANDATORY NOTICES, STANDING, AND FEES ..................................... 1
`A. Mandatory Notices ........................................................................................... 1
`B. Certification of Grounds for Standing ............................................................. 2
`C. Fees .................................................................................................................. 2
`III. OVERVIEW OF THE ’294 PATENT ............................................................ 2
`IV. SUMMARY OF PRIOR ART ......................................................................... 5
`A. Nguyen ............................................................................................................. 5
`B. Wise ................................................................................................................. 7
`C. Molloy .............................................................................................................. 8
`D. Pearson ........................................................................................................... 11
`V. CLAIM CONSTRUCTION .............................................................................. 12
`A. “wherein the video decoder executes” .......................................................... 12
`VI. THERE IS A REASONABLE LIKELIHOOD THAT THE CHALLENGED
`CLAIMS ARE UNPATENTABLE ......................................................................... 13
`A. Ground 1: The combination of Wise and Nguyen renders Claims 1, 3, 9, and
`11 Obvious Under 35 U.S.C. § 103. ..................................................................... 14
`1. A POSITA would have had a motivation to combine Nguyen and Wise.. 14
`2. The combination of Nguyen and Wise discloses every element of Claims
`1, 3, 9, and 11 .................................................................................................... 18
`B. Ground 1A: The combination of Wise, Nguyen, and Molloy renders Claims
`2 and 10 Obvious Under 35 U.S.C. § 103. ........................................................... 41
`1. A POSITA would have had a motivation to combine Wise/Nguyen and
`Molloy. .............................................................................................................. 41
`2. The combination of Wise and Nguyen and Molloy discloses every element
`of Claims 2 and 10. ........................................................................................... 43
`C. Ground 2: The combination of Nguyen and Molloy renders Claims 1-3 and
`9-11 Obvious Under 35 U.S.C. § 103. ................................................................. 44
`1. A POSITA would have had a motivation to combine Molloy and Nguyen.
`
`44
`
`
`
`i
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`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`
`
`2. The combination of Nguyen and Molloy discloses every element of claims
`1-3 and 9-11. ..................................................................................................... 47
`D. Ground 3: Pearson anticipates Claims 1-3 and 9-11 under 35 U.S.C. § 102 57
`1. Claim 1 ....................................................................................................... 57
`2. Claim 2 ....................................................................................................... 69
`3. Claim 3 ....................................................................................................... 70
`4. Claim 9-11 .................................................................................................. 71
`VII. CONCLUSION .............................................................................................. 72
`
`
`
`
`
`ii
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`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`LIST OF EXHIBITS
`
`U.S. Patent No. 7,720,294 (the “’294 Patent”)
`
`Prosecution History of the ’294 Patent
`
`Declaration of Dr. Samuel Russ
`
`U.S. Patent No. 6,909,744 to Molloy
`
`U.S. Patent No. 6,425,054 to Nguyen
`
`U.S. Patent No. 7,236,525 to Pearson
`
`U.S. Patent No. 7,230,986 to Wise
`
`CV of Dr. Samuel Russ
`
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`iii
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`
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`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`I.
`
`INTRODUCTION
`
`Advanced Micro Devices, Inc. (“AMD” or “Petitioner”) requests inter
`
`partes review (“IPR”) under 35 U.S.C. §§ 311–319 and 37 C.F.R. § 42.100 et seq.
`
`of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294 (“’294 Patent”).
`
`Petitioner asserts that there is a reasonable likelihood that the challenged
`
`claims are unpatentable and requests review of, and cancellation of, the challenged
`
`claims under 35 U.S.C. §§ 102 and 103.
`
`II. MANDATORY NOTICES, STANDING, AND FEES
`
`A. Mandatory Notices
`Real Party in Interest: Petitioner AMD and ATI Technologies ULC are the
`
`real parties-in-interest. ATI Technologies ULC is an indirect, wholly owned
`
`subsidiary of AMD (with 1252986 Alberta ULC being the intervening direct
`
`subsidiary of AMD and parent of ATI Technologies ULC).
`
`Related Matters: The ’294 Patent is subject to a pending lawsuit entitled
`
`Broadcom Corp. v. Sony Corp., No. 8:16-cv-01052 (C.D. Cal.). Petitioner is not a
`
`party to this suit and does not control any party to this suit.
`
`Lead Counsel: Lead Counsel is Brian Oaks (Reg. 44,981) and Back-up
`
`Counsel is and Jennifer Nall (Reg. 57,053), each of Baker Botts L.L.P.
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`Service Information: Baker Botts L.L.P., 98 San Jacinto Blvd., Suite 1500,
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`Austin, Texas 78701; Tel. (512) 322-5470; Fax (512) 322-3622. Petitioner
`
`
`
`1
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`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`consents
`
`to
`
`service by electronic mail at: brian.oaks@bakerbotts.com,
`
`jennifer.nall@bakerbotts.com, and AMD_294IPR@bakerbotts.com. A Power of
`
`Attorney is filed concurrently herewith under 37 C.F.R. § 42.10(b).
`
`B. Certification of Grounds for Standing
`Petitioner certifies that the ’294 Patent is available for IPR. Petitioner is not
`
`barred or estopped from requesting IPR of the ’294 Patent.
`
`Fees
`
`C.
`The Office is authorized to charge any fees that become due in connection
`
`with this Petition to Deposit Account No. 02-0384.
`
`III. OVERVIEW OF THE ’294 PATENT
`
`The ’294 Patent1 discloses a “unified video decoder” for decoding video
`
`data. As was known in the prior art, video data can be compressed using any one of
`
`many known video encoding standards. After video data is encoded (or
`
`compressed) according to a particular standard, that video data may be conveyed
`
`(i.e., transmitted or stored on a computer readable media) to a device (e.g., a
`
`computer or TV) where the device then decodes the compressed video data for
`
`display.
`
`
`1
`The ’294 Patent was filed on February 9, 2004, and does not claim priority
`
`to any other filings.
`
`
`
`2
`
`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`The ’294 Patent claims a dedicated video decoder that executes various sets
`
`of instructions to decode video that has been encoded using one of a variety of
`
`known video encoding standards. According to the background of the ’294 Patent,
`
`multi-standard video decoders were known in the art. Ex. 1001, 1:32-33 (“some
`
`video decoders are capable of decoding video data from multiple formats”). The
`
`’294 Patent criticizes these known video decoders as requiring “special hardware
`
`dedicated to decoding each one of the wide variety of encoding standards.” Id.,
`
`1:34-35. According to the ’294 Patent, “[t]his is disadvantageous because the
`
`additional hardware increases the cost of the decoder system.” Id., 1:35-37.
`
`To avoid extra costs incurred by utilizing multiple sets of dedicated
`
`hardware decoders, the specification of the ’294 Patent discloses a “unified
`
`decoder architecture” that uses firmware to decode video data of different
`
`standards. Ex. 1001, 1:46, 2:66-67. The “unified video decoder” receives a signal
`
`indicating the particular standard used to encode video. Id., 3:7-9. Based on the
`
`indication, the “unified video decoder” decodes the video by executing firmware
`
`instructions associated with the particular standard. Id., 3:10-13.
`
`Figure 2 of the ’294 Patent illustrates the claimed instruction-based video
`
`decoder:
`
`
`
`3
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`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`
`
`Ex. 1001, Fig. 2. “Instruction memory 291” stores various sets of “instructions
`
`295” that are associated with different video encoding standards. Id., 3:14-37.
`
`“Host processor 290” provides an indication to the “video decoder 209” identifying
`
`the standard associated with a particular set of video data. Id., 3:38-44. Responsive
`
`to the indication, “video decoder 209” selects and executes a set of instructions
`
`from instruction memory 291 that are associated with the identified standard. Id.,
`
`3:63-67.
`
`The issued versions of Claims 1-3 and 9-11 claim the instruction-based
`
`video decoder described above.
`
`
`
`4
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`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`IV. SUMMARY OF PRIOR ART
`
`A. Nguyen
`Nguyen2 discloses a firmware-based video decoder that operates in
`
`conjunction with a discrete host processor.
`
`Like the specification of the ’294 Patent, Nguyen also recognizes that
`
`“dedicated hardware” has been used to perform “MPEG video decoding or
`
`encoding.” Ex. 1005, 1:50-54. Nguyen further recognizes that “[d]edicated
`
`hardware . . . [is] only usable for specific problems and [is] unable to adapt to other
`
`problems or changes in standards.” Id., 1:54-57. To solve this problem, Nguyen
`
`discloses a “[m]ultimedia card 100” that uses firmware executed by “multimedia
`
`processor 110” to decode video data that has been encoded in any one of a variety
`
`of video standards. Id., 4:54-58; id., 6:53-61. Nguyen recognizes that using a
`
`firmware-based architecture is advantageous because Nguyen’s video decoder can
`
`be “adapted to a new protocol simply by changing either its application programs
`
`or its firmware.” Ex. 1005, 3:62-64.
`
`
`2
`U.S. Patent No. 6,425,054 to Nguyen was published on July 23, 2002 and is
`
`prior art to the ’294 Patent under 35 U.S.C. § 102(b). Ex. 1005
`
`
`
`5
`
`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`As in the ’294 Patent, Nguyen’s video decoder (“multimedia card 100”)
`
`operates in conjunction with primary processor 310, which is a discrete host
`
`processor of “host computer system 300”:
`
`Host Processor
`
`Master Processor
`
`Video decoder
`
`
`
`Ex. 1005, Fig. 3. (annotated). “Host computer system 300” includes its own
`
`“primary processor 310” that executes applications to communicate with the video
`
`decoder (“multimedia card 100”) via device drivers using “control signals needed
`
`by the particular embodiment of multimedia card 100.” Id., 6:62-7:27; 7:12-16.
`
`
`
`6
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`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`Also similar to the ’294 Patent, Nguyen’s video decoder includes “general purpose
`
`processor 210,” which coordinates the functions of Nguyen’s “multimedia card
`
`100.” Ex. 1005, Fig. 3, 3:44-67; Ex. 1003, ¶¶ 44-46.
`
`B. Wise
`Wise3 discloses a firmware-based, multi-standard video decoder. Wise
`
`describes a video decoder that receives from a microprocessor a signal indicating
`
`the particular encoding standard associated with a video stream, and, based on the
`
`indication, select a set of instructions to decode the video stream. Ex. 1007, 1:21-
`
`28; Ex. 1003, ¶ 47.
`
`Wise’s video decoder includes a pipeline of configurable processing stages:
`
`
`
`
`3
`U.S. Patent No. 7,230,986 to Wise was filed on October 10, 2001, was
`
`published on August 21, 2003, and issued on June 12, 2007. Ex. 1007. Wise is
`
`therefore prior art to the ’294 Patent under 35 U.S.C. §§ 102(a) and 102(e).
`
`
`
`7
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`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`Ex. 1007, Fig. 32. For example, Figure 32 illustrates a “spatial decoder” stage, a
`
`“temporal decoder” stage, and a “formatter” stage.” Ex. 1007, Fig. 32; see also Ex.
`
`1003, ¶ 48. As data moves through the stages of the pipeline, “token” (i.e., a data
`
`structure) identifies the particular standard associated with the coded data. Ex.
`
`1007, 12:26-34
`
`The spatial decoder uses firmware instructions to decode video data. Ex.
`
`1003, ¶¶ 49-50. For example, the spatial decoder includes a Huffman decoder that
`
`operates by executing different programs (i.e., sets of instructions) for each video
`
`standard. Ex. 1007, 11:43-12:3. A particular program is selected based on the
`
`standard identified by the “CODING STANDARD” token. Ex. 1007, 11:43-12:3.
`
`The “CODING STANDARD” token may be supplied to the video decoder from a
`
`microprocessor. Ex. 1007, 37:24-28.
`
`Wise therefore teaches the concept of selecting a set of instructions to
`
`decode video data based upon an indication received from a microprocessor. Ex.
`
`1003, ¶ 51.
`
`C. Molloy
`Molloy discloses a video decoder configured to operate in accordance with a
`
`particular video standard based on an indication received from a microprocessor.
`
`Ex. 1003, ¶ 52.
`
`
`
`8
`
`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`The decoder in Molloy4 is a multi-standard video decoder that can be
`
`configured to decode data encoded using “each of the JPEG, MPEG1, MPEG2 or
`
`MPEG4, H.261 or H.263 compression standards.”5 Ex. 1004, 2:24-31. Like the
`
`’294 Patent, Molloy recognized the importance of adapting video decoders to
`
`operate with a wide variety of standards. Ex. 1004, 4:15-17 (“The video
`
`encoder/decoder may also be configured through further software programming to
`
`encode/decode data according to any other compression standard.”).
`
`Molloy’s processor 200 sends an “indication” to the video decoder 150 to
`
`configure the decoder to operate for a particular encoding standard. Ex. 1003, ¶ 54.
`
`
`4
`U.S. Patent No. 6,909,744 to Molloy was filed on December 8, 2000 and
`
`issued on June 21, 2005. Ex. 1004. Molloy is therefore prior art to the ’294 Patent
`
`under 35 U.S.C. § 102(e).
`
`5
`
`The term “JPEG” refers to both a video standard and a still picture standard.
`
`Ex. 1003, ¶ 54.
`
`
`
`9
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`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`
`
`Ex. 1004, Fig. 2; Ex. 1003, ¶ 54. Specifically, “[t]o configure video
`
`encoder/decoder 150 to encode/decode data according to a selected one of the
`
`above compression standards, processor 200 loads video encoder/decoder 150’s
`
`configuration register with the configuration data for the selected compression
`
`standard.” Ex. 1004, 7:37-60. Writing data to the register in the video decoder is
`
`“an indication” as to the particular standard. Ex. 1003, ¶ 54.
`
`
`
`10
`
`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`D.
`Pearson
`Like the ’294 Patent, Pearson6 discloses a “reconfigurable computing based
`
`multi-standard video codec.” Ex. 1006, [56]; see also Ex. 1003, ¶ 55 (explaining
`
`that “codec” means a “enCOder/DECoder pair to encode and decode video in
`
`accordance with a particular standard):
`
`Host processor
`
`Master processor
`
`Instruction memory
`
`Ex. 1006, Fig. 1.
`
`
`
`
`6
`U.S. Patent No. 7,236,525 to Pearson was filed on May 22, 2003, and issued
`
`on June 26, 2007. Ex. 1006. Pearson is therefore prior art to the ’294 Patent under
`
`35 U.S.C. § 102(e).
`
`
`
`11
`
`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`Pearson’s system includes a discrete host CPU that sends an indication to a
`
`video decoder to configure the decoder for a particular video standard. Ex. 1003,
`
`¶¶ 57-58. Specifically, Pearson includes a field programmable gate array (FPGA)
`
`that utilizes different programs to decode different standards of video data. Ex.
`
`1003, ¶¶ 55-56. Pearson’s FPGA is connected to a “memory module 102” that
`
`stores programs that are used to decode data using different standards. Ex. 1003, ¶
`
`57. Pearson’s “CPU 108” sends an indication identifying the particular standard
`
`associated with the a set of video data, and in response the indication, a program
`
`associated with the standard is loaded into the FPGA to decode the video data. Ex.
`
`1003, ¶¶ 57-58.
`
`V. CLAIM CONSTRUCTION
`
`The constructions set forth below are provided for purposes of this IPR.
`
`“wherein the video decoder executes”
`
`A.
`Claims 1 and 9 recite that “the video decoder executes” instructions
`
`associated with a particular encoding standard. Claims 1 and 9 also recite that the
`
`“video decoder” includes a “master processor.” Ex. 1001, Claims 1 and 9. Patent
`
`Owner may argue that the master processor must be the element of the video
`
`decoder that executes the claimed sets of instructions. Under the broadest
`
`reasonable construction of this phrase, any component of the video decoder may
`
`execute instructions.
`
`
`
`12
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`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`The claims of the ’294 Patent were amended during prosecution to
`
`distinguish art cited by the Examiner. In each of the four office actions issued
`
`during prosecution, all pending claims of the application were rejected as
`
`anticipated by U.S. Pat. Pub. 2003/0185306 (“Macinnis”). Ex. 1002, 144, 180, 216,
`
`265. Before amendment, the claims recited “a host processor for providing an
`
`indication to the video decoder indicating the particular encoding standard,” but
`
`did not recite any structural relationship between the host processor and the video
`
`decoder. Ex. 1002, 16-22. To distinguish Macinnis, the applicant amended the
`
`claims to recite two concepts: (1) that the claimed video decoder is “discrete” from
`
`the host processor, and (2) that the claimed video decoder includes a “master
`
`processor.” Ex. 1002, 200-204, 242-247, 320-325.
`
`Notably, the amended claims do not require that the “master processor”
`
`perform any particular function. Rather, the video decoder—not the master
`
`processor—“executes” the instructions. Because Claims 1 and 9 do not identify the
`
`element of the video decoder that performs the execution, the broadest reasonable
`
`interpretation of the phrase “wherein the video decoder executes” includes any
`
`component of a video decoder executing instructions.
`
`VI. THERE
`IS A REASONABLE LIKELIHOOD THAT THE
`CHALLENGED CLAIMS ARE UNPATENTABLE
`
`This petition presents the following grounds of unpatentability for Claims 1-
`
`3 and 9-11 of the ’294 Patent:
`
`
`
`13
`
`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`Ground
`
`Claims
`
`Prior Art
`
`1, 3, 9, and 11
`
`Obvious over Nguyen and Wise
`
`2 and 10
`
`Obvious over Nguyen, Wise, and Molloy
`
`1-3 and 9-11
`
`Obvious over Nguyen and Molloy
`
`1-3 and 9-11
`
`Anticipated by Pearson
`
`1
`
`1A
`
`2
`
`3
`
`
`
`A. Ground 1: The combination of Wise and Nguyen renders Claims
`1, 3, 9, and 11 Obvious Under 35 U.S.C. § 103.
`1.
`
`A POSITA would have had a motivation to combine
`Nguyen and Wise.
`
`As shown below, Nguyen explicitly discloses every element of Claims 1 and
`
`9 of the ’294 Patent. Ex. 1003, ¶¶ 60-63. However, Nguyen lacks a specific
`
`description of an “indication” from the “host processor,” as recited in Claims 1 and
`
`9. See, e.g., Ex. 1001, Claims 1, 9. As explained below, Nguyen at least suggests
`
`the required “indication” to a POSITA. In addition, Wise discloses a similar video
`
`decoder and describes the claimed “indication” in detail. A POSITA would have
`
`found it obvious to include Wise’s indication in Nguyen’s video decoder.
`
`Nguyen discloses a host processor that sends “control signals” to a video
`
`decoder. Ex. 1003, ¶ 63. A POSITA would have understood that these “control
`
`signals” include an indication of the particular video standard associated with the
`
`video data being processed. Id. Specifically, Nguyen discloses a “host processor”
`
`
`
`14
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`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`(primary processor 310) that executes applications, which communicate with the
`
`video decoder via device drivers. See, e.g., Ex. 1005, 6:62-7:27. Nguyen’s device
`
`drivers transmit “control signals needed by the particular embodiment of
`
`multimedia card 100.” Id., 7:12-16. Accordingly, Nguyen has a host processor that
`
`sends control signals to a video decoder. Ex. 1003, ¶¶ 60-61. However, Nguyen
`
`does not expressly specify that the control signals sent from the host processor to
`
`Nguyen’s video decoder include an indication of the particular decoding standard
`
`to be used.
`
`A POSITA would have known that Nguyen’s video decoder would receive
`
`an indication to identify the particular encoding standard associated with video
`
`data to be processed. Ex. 1003, ¶¶ 64-66. Indeed, there are only a limited number
`
`of ways that a video decoder (such as Nguyen’s) can ascertain the correct video
`
`standard to use. Id. First, a device external to the video decoder can send some
`
`message to the video decoder identifying the video standard. Id. Second, a video
`
`decoder may receive header information associated with video data, and determine
`
`the standard from that header data. Id. In either case, the video decoder receives an
`
`indication (e.g., a message or the header information). Id. Absent such an
`
`indication, a video decoder would be unable to determine from raw frame data
`
`what encoding standard to use. Id., ¶¶ 65-66. Therefore, a POSITA would have
`
`
`
`15
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`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`recognized that a video decoder (including Nguyen’s) would receive an indication
`
`of the video standard. Id.
`
`A POSITA using Nguyen’s video decoder and realizing the need for an
`
`indication would have looked to similar systems to determine how a video decoder
`
`should ascertain the video standard associated with particular video data. Ex. 1003,
`
`¶¶ 67-68. Accordingly, a POSITA would have looked to Wise because Wise
`
`discloses a similar video decoder system as Nguyen, and because Wise discloses
`
`how to use an indication to identify the video standard applicable to a particular set
`
`of video data. Id.
`
`Like the ’294 Patent, Wise discloses that a microprocessor (i.e., a discrete
`
`host processor) may configure the decoder system to decode data using a particular
`
`standard. Supra, Section IV.B. In some embodiments, Wise uses a microprocessor
`
`to transmit control tokens to the video decoder that are used to configure the video
`
`decoder to a particular standard. Ex. 1007, 68:62-65 (“the system of the present
`
`invention configures the downstream functional stages under the control of the
`
`control tokens. An option is provided for obtaining needed and/or alternative
`
`control from the MPU.”); see also id., 133:65-134:55 (“configuration Tokens can
`
`be supplied . . . via . . . [t]he microprocessor interface (MPI).”). One example of
`
`such a control token is Wise’s “CODING_STANDARD token for conditioning the
`
`system
`
`for processing
`
`in a selected one of a plurality of picture
`
`
`
`16
`
`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`compression/decompression
`
`standards.”
`
`Ex.
`
`1007,
`
`12:17-20.
`
`The
`
`“CODING_STANDARD” token designates one of several different video
`
`standards that are used to configure Wise’s decoder to the particular standard
`
`specified in the token. Id., 12:21-25.
`
`It would have been obvious to a POSITA to combine Nguyen and Wise such
`
`that Nguyen’s host processor would send an indication to Nguyen’s video decoder
`
`to specify which encoding standard should be used. Nguyen differs from the
`
`claimed invention only in that Nguyen does not expressly recite that the host
`
`processor sends an indication to the video decoder. Ex. 1003, ¶¶ 68-69. However,
`
`Wise discloses this feature in explicit detail for a similar decoder. Id. A POSITA
`
`would have been motivated to incorporate Wise’s indication into Nguyen’s video
`
`decoding system. Id. Because Nguyen already discloses that “primary processor
`
`310” sends “control signals” to Nguyen’s video decoder, it would have been
`
`obvious to a POSITA to use Nguyen’s “primary processor 310” to send such an
`
`indication. Id. Specifically, a POSITA would have found it obvious to use
`
`Nguyen’s “control signals” to send an indication to the video decoder. Id.
`
`The proposed combination of Nguyen and Wise would have been nothing
`
`more than a “predictable use of prior art elements according to their established
`
`functions,” and would therefore have been obvious. KSR Int’l Co. v. Teleflex Inc.,
`
`550 U.S. 398, 417 (2007). For example, Wise discloses a particular data structure
`
`
`
`17
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`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`(i.e., a token) for transmitting an indication. Ex. 1003, ¶¶ 70-71. Nguyen’s CPU
`
`may be implemented as “an x86 type microprocessor” in a personal computing
`
`system. Id. A POSITA would have been easily able to program Nguyen’s CPU to
`
`send the same type of token disclosed in Wise, or to send the same information in
`
`another data format. Id. As explained above, a POSITA would have recognized
`
`that information to indicate the applicable video standard is required in a multi-
`
`standard decoder. The proposed combination would have yielded predictable
`
`results—an instruction-based video decoder capable of decoding multiple video
`
`standards where a host processor sends an indication to a video decoder to
`
`determine which standard to use. Id. The proposed combination would therefore
`
`have been obvious. Id.
`
`2.
`
`The combination of Nguyen and Wise discloses every
`element of Claims 1, 3, 9, and 11
`(i)
`
`Claim 1
`
`Element 1[p]: “A system for decoding video data encoded with a particular
`standard, said system comprising:”
`
`Nguyen and Wise each disclose the preamble of Claim 1.
`
`Nguyen’s “system 300” includes “multimedia card 100,” which is a video
`
`decoder that is capable of decoding video encoded in a variety of standards:
`
`
`
`18
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`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`Video decoder
`
`
`
`Ex. 1005, Fig. 3. (annotated).
`
`In the description of related art, Nguyen teaches that “digital signal
`
`processors (DSPs) are used in multimedia applications such as coding and
`
`decoding of video, audio, and communications data. One type of DSP has
`
`dedicated hardware to address a specific problem such as MPEG video decoding or
`
`encoding.” Ex. 1005, 1:49-54. Nguyen discloses an improved programmable DSP
`
`that could be used for video encoding and decoding with various different video
`
`
`
`19
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`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`standards. Specifically, Nguyen discloses that “multimedia card 100” may receive
`
`video data consisting of a sequence of pixel values, and that “[m]ultimedia card
`
`100 compresses or encodes the pixel values according to a video encoding standard
`
`such as MPEG, JPEG, or H.324 implemented in the firmware executed by
`
`multimedia processor 110.” Ex. 1005, 4:54-57. Nguyen also teaches that
`
`“[m]ultimedia processor 110 uses a local memory 120, also located on
`
`multimedia card 100, for storage of data and program instructions. Local memory
`
`120 may also act as a frame buffer for video coding and decoding
`
`applications.” Ex. 1005, 4:23-26 (emphasis added). Accordingly, Nguyen’s
`
`“multimedia card 100” can both encode and decode video data using a variety of
`
`standards. Ex. 1003, ¶¶ 74-75.
`
`Like Nguyen and the ’294 Patent, Wise discloses an “apparatus for
`
`decompression which operates to decompress and/or decode a plurality of
`
`differently encoded input signals,” including decoding video standards such as
`
`“JPEG, MPEG and H.261.” Ex. 1007, 1:21-28; Ex. 1003, ¶ 76.
`
`Therefore, both Wise and Nguyen disclose element 1[p].
`
`1[p] A system for decoding
`video data encoded with a
`particular standard, said
`system comprising:
`
`Nguyen:
`
`Nguyen’s “multimedia card 100” is a video decoder:
`
`
`Ex. 1005, 1:49-54: “A variety of digital
`signal processors (DSPs) are used in
`multimedia applications such as coding and
`decoding of video, audio, and
`
`
`
`20
`
`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`communications data. One type of digital
`signal processor (DSP) has dedicated hardware
`to address a specific problem such as MPEG
`video decoding or encoding.” (emphasis
`added).
`
`
`
`Ex. 1005, 4:50-62: “Multimedia card 100
`compresses or encodes the pixel values
`according to a video encoding standard
`such as MPEG, JPEG, or H.324
`implemented in the firmware executed by
`multimedia processor 110. The encoded
`video data can then be transmitted to the host
`computer via local bus 105, to a device such as
`an Ethernet card coupled to local bus 105, or
`to be further encoded for transmission on a
`telephone line coupled to communication
`DAC 148.” (emphasis added).
`
`Wise:
`
`Ex. 1007, 1:21-28: “The present invention is directed
`to improvements in methods and apparatus for
`decompression which operates to decompress and/or
`decode a plurality of differently encoded input
`signals. The illustrative embodiment chosen for
`description hereinafter relates to the decoding of a
`plurality of encoded picture standards. More
`specifically, this embodiment relates to the decoding
`of any one or the well known standards known as
`JPEG, MPEG and H.251.”
`
`Ex. 1007, 12:35-51: “1. Multi-standard
`Configurations
`
`Since the various compression standards, i.e., JPEG,
`MPEG and H.261, are well known, as for example as
`described in the aforementioned U.S. Pat. No.
`5,212,742, the detailed specifications of those
`standards are not repeated here.
`
`
`
`21
`
`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`
`As previously mentioned, the present invention is
`capable of decompressing a variety of differently
`encoded, picture data bitstreams.”
`
`
`
`Element 1[a]: “a video decoder for decoding the video data encoded with the
`particular standard, wherein the video decoder comprises a master processor;”
`
`Nguyen and Wise each disclose Element 1[a].
`
`As discussed above for element 1[p], Nguyen’s “multimedia card 100” is a
`
`video encoder and decoder. Nguyen’s “multimedia card 100” includes the claimed
`
`“master processor.” Ex. 1003, ¶ 78. Specifically, “multimedia card 100” includes
`
`“multimedia processor 110,” which further includes “general purpose processor
`
`210:”
`
`
`
`22
`
`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`Master Processor
`
`Video decoder
`
`
`
`Ex. 1005, Fig. 3 (annotated). Furthermore, Nguyen’s “general purpose processor
`
`210” is a master processor. For example, Nguyen’s “general purpose processor”
`
`coordinates the functions of Nguyen’s DSP, and “acts as the master processor to
`
`the vector processor.” Ex. 1005, 3:44-67.
`
`Wise also discloses a video decoder and a processor that satisfies the
`
`“master processor” limitations recited in Claim 1. Ex. 1003, ¶ 79. The video
`
`
`
`23
`
`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`decoder in Wise includes processing stages such as a spatial decoder, and a
`
`temporal decoder:
`
`Ex. 1007, Fig. 32 (FIG. 32 shows a “multi-standard video decoder”); id., 50:57-60.
`
`Wise’s spatial decoder includes a “Huffman decoder” that executes a program
`
`associated with a particular coding standard:
`
`
`
`Ex. 1007, Fig. 27 (“FIG. 27 is a block diagram illustrating the Huffman decoder
`
`and parser state machine of the Spatial Decoder.”). The Huffman decoder executes
`
`a different program for each video encoding standard. Ex. 1007, 52:19-33.
`
`
`
`
`
`24
`
`

`

`Petition for IPR of Claims 1-3 and 9-11 of U.S. Patent No. 7,720,294
`
`Therefore, Wise’s Huffman decoder performs at least the functions of the master
`
`processor recited in element 1[a]. Ex. 1003, ¶ 80.
`
`Therefore, Nguyen and Wise disclose element 1[a