throbber
Trials@uspto.gov
`571.272.7822
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` Paper 33
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` Entered: October 29, 2018
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
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`CISCO SYSTEMS, INC.,
`Petitioner,
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`v.
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`EGENERA, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-01340
`Patent 6,971,044 B2
`____________
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`Before MELISSA A. HAAPALA, Acting Vice Chief Administrative Patent
`Judge, KRISTEN L. DROESCH and CHARLES J. BOUDREAU,
`Administrative Patent Judges.
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`HAAPALA, Acting Vice Chief Administrative Patent Judge.
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`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
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`Cisco Systems, Inc. (“Petitioner”) filed a Petition pursuant to
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`35 U.S.C. §§ 311–319 to institute an inter partes review of claims 1–6 of
`U.S. Patent No. 6,971,044 B2 (“’044 patent”). Paper 1 (“Pet.”). Egenera,
`Inc. (“Patent Owner”) filed a Preliminary Response. Paper 6 (“Prelim.
`Resp.”). Applying the standard set forth in 35 U.S.C. § 314(a), we granted
`Petitioner’s request and instituted an inter partes review of all challenged
`claims. Paper 7 (“Dec.”).
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`During the trial, Patent Owner timely filed a Response (Paper 18,
`“PO Resp.”), to which Petitioner timely filed a Reply (Paper 25, “Reply”).
`An oral hearing was held on July 25, 2018, and a copy of the transcript was
`entered into the record. Paper 32 (“Tr.”).
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`Additionally, Patent Owner filed a Motion to Exclude Evidence
`(Paper 29, “Mot. To Exclude”), to which Petitioner filed an Opposition
`(Paper 31,”Mot. Opp.”).
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`We have jurisdiction under 35 U.S.C. § 6. This Decision is a Final
`Written Decision under 35 U.S.C. § 318(a) and 37 C.F.R. § 42.73 as to the
`patentability of the claims on which we instituted trial. Based on the record
`before us, we determine that Petitioner has shown, by a preponderance of the
`evidence, that claims 1–6 of the ’044 patent are unpatentable.
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`I. BACKGROUND
`A. The ’044 Patent (Ex. 1001)
`The ’044 patent describes processing systems having virtualized
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`communication networks and storage for quick deployment and
`reconfiguration. Ex. 1001, 1:17–19. The platform provides a large pool of
`processors from which a subset may be selected and configured through
`software commands to form a virtualized network of computers that may be
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`deployed to serve a given set of applications or customer. Id. at 2:59–64.
`The virtualization may include virtualization of local area networks (LANs)
`or the virtualization of I/O storage. Id. at 2:67–3:2.
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`Figure 1 of the ’044 patent is reproduced below:
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`Figure 1 depicts hardware platform 100, which includes processing nodes
`105a-105n connected to switch fabrics 115a, 115b via high-speed
`interconnects 110a, 110b. Id. at 3:10–12. Switch fabrics 115a, 115b are
`also connected to at least one control node 120a, 120b in communication
`with external Internet Protocol (IP) network 125 and storage area network
`(SAN) 130. Id. at 3:13–16. In some embodiments, processing nodes 105a–
`105n, control nodes 120a, 120b, and switch fabrics 115a, 115b are contained
`in a single chassis and interconnected via a fixed, pre-wired mesh of
`point-to-point (PtP) links. Id. at 3:20–24. Figure 1 depicts additional
`components not described.
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`Under software control, the platform supports multiple, simultaneous,
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`and independent processing area networks (PANs), which are each
`configured to have a corresponding subset of processors that may
`communicate via a virtual local area network emulated over the PtP mesh.
`Id. at 3:65–4:3. An administrator defines the network topology of a PAN
`and specifies media access control (MAC) address assignments of the
`various nodes. Id. at 6:4–7. The MAC address is virtual, identifying a
`virtual interface, and is not tied to any specific physical node. Id. at 6:7–9.
`The virtual local area network provides communication among a set of
`computer processors, but excludes processors not in the defined set. Id. at
`2:8–11. A virtual storage space is also defined and established with a
`defined correspondence to the address space of a storage network. Id. at
`2:11–13.
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`The ’044 patent further describes that the control node, via software
`(without any physical re-cabling), may change the PAN configuration to
`allow a new processor to inherit the storage and networking personality of
`another. See id. at 23:3–7, 28:14–19. This may be done to swap a new
`processor into a PAN to replace a failing one. Id. at 29:19–21. In response
`to a failure by a computer processor, a computer processor is allocated to
`replace the failed processor, and the MAC address of the failed processor is
`assigned to the processor that replaces the failed processor. Id. at 2:13–17.
`The virtual storage space and defined correspondence to the address space of
`the storage network is also assigned to the processor that replaces the failed
`processor. Id. at 2:17–19. The virtual local area network is then
`reestablished to include the processor that replaced the failed processor and
`to exclude the failed processor. Id. at 2:19–22.
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`B. Illustrative Claim
`Claims 1 and 4 are independent claims. Claim 1 is illustrative of the
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`subject matter of the claims at issue:
`1. A platform for computer processing, connectable to an
`external communication network and a storage network and
`comprising:
`a plurality of computer processors connected to an
`internal communication network;
`configuration logic to define and establish (a) a virtual
`local area communication network over the internal network,
`wherein each computer processor in the virtual local area
`communication network has a corresponding virtual MAC
`address and the virtual local area network provides
`communication among a set of computer processors but
`excludes the processors from the plurality not in the defined set,
`and (b) a virtual storage space with a defined correspondence to
`the address space of the storage network; and
`failover logic, responsive to a failure of a computer
`processor, to allocate a computer processor from the plurality to
`replace the failed processor, the failover logic including logic to
`assign the virtual MAC address of the failed processor to the
`processor that replaces the failed processor, logic to assign the
`virtual storage space and defined correspondence of the failed
`processor to the processor that replaces the failed processor, and
`logic to reestablish the virtual local area network to include the
`processor that replaces the failed processor and to exclude the
`failed processor.
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`C. Instituted Grounds of Unpatentability
`Petitioner relies on the following references:
`1. U.S. Patent No. 6,779,016, issued Aug. 17, 2004 (“Aziz”)
`(Ex. 1006).
`2. U.S. Patent No. 6,856,591, issued Feb. 15, 2005 (“Ma”)
`(Ex. 1007).
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`3. Thorsten von Eicken & Werner Vogels, Evolution of the
`Virtual Interface Architecture, 10 IEEE COMPUTER 61
`(Nov. 1998) (“Von Eicken”) (Ex. 1008).
`We instituted trial under 35 U.S.C. § 103(a) based on the following
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`combinations of references. Dec. 18.
`References
`Aziz and Ma
`Aziz, Ma, and Von Eicken
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`Claims
`1, 3, 4, 6
`2, 5
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`In support of its contentions, Petitioner submitted a declaration by its
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`witness, Prashant Shenoy, Ph.D. Ex. 1004. In response, Patent Owner
`submitted a declaration by its witness, H. Jonathan Chao, Ph.D. Ex. 2015.
`Both witnesses were cross-examined during the trial, and transcripts of their
`depositions are in the record. Ex. 2017 (Shenoy deposition); Ex. 1035 (Chao
`deposition).
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`D. Related Proceedings
`Petitioner and Patent Owner identify the following related district
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`court litigation: Egenera, Inc. v. Cisco Systems, Inc. (1-16-cv-11613,
`D. Mass). Pet. 6; Paper 4, 2. Petitioner also filed a petition for inter partes
`review of claims 1–8 of U.S. Patent No. 7,231,430 B2 (IPR2017-01341,
`Paper 2) (institution denied; Paper 10), which Patent Owner identifies as a
`related proceeding. Paper 4, 2.
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`II. ANALYSIS
`A. Legal Principles
`A claim is unpatentable under § 103(a) if the differences between the
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`claimed subject matter and the prior art are “such that the subject matter as a
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`whole would have been obvious at the time the invention was made to a
`person having ordinary skill in the art to which said subject matter pertains.”
`KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). The question of
`obviousness is resolved on the basis of underlying factual determinations,
`including: (1) the scope and content of the prior art; (2) any differences
`between the claimed subject matter and the prior art; (3) the level of skill in
`the art; and (4) objective evidence of non-obviousness, i.e., secondary
`considerations such as commercial success, long felt but unsolved needs,
`and failure of others.1 Graham v. John Deere Co., 383 U.S. 1, 17–18
`(1966). The obviousness inquiry further requires an analysis of “whether
`there was an apparent reason to combine the known elements in the fashion
`claimed by the patent at issue.” KSR, 550 U.S. at 418 (citing In re Kahn,
`441 F.3d 977, 988 (Fed. Cir. 2006) (requiring “articulated reasoning with
`some rational underpinning to support the legal conclusion of
`obviousness”)).
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`B. Level of Ordinary Skill in the Art
`Petitioner asserts a person of ordinary skill in the art is someone
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`knowledgeable and familiar with network computing and that such a person
`would have (i) a Bachelor’s degree in Electrical and/or Computer
`Engineering, Computer Science, or equivalent training, and
`(ii) approximately two years of experience working in hardware and/or
`software design and development relating to network computing. Pet. 13–
`14. Petitioner asserts lack of work experience can be remedied by additional
`education, and vice versa. Id. at 14. Patent Owner does not provide a level
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`1 The record does not include arguments or evidence regarding objective
`indicia of non-obviousness.
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`of skill in the art or otherwise contest the level of skill advocated by
`Petitioner. See PO Resp.
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`We accept the level of skill advocated by Petitioner as it is
`uncontested and consistent with the prior art of record.
`C. Claim Construction
`In an inter partes review, claims of an unexpired patent are
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`interpreted using the broadest reasonable construction in light of the
`specification of the patent in which they appear. See 37 C.F.R.
`§ 42.100(b) (2016); Cuozzo Speed Techs., LLC v. Lee, 136 S. Ct. 2131,
`2144–46 (2016). Under that standard, “words of the claim must be given
`their plain meaning, unless such meaning is inconsistent with the
`specification and prosecution history.” Trivascular, Inc. v. Samuels, 812
`F.3d 1056, 1062 (Fed. Cir. 2016).
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`1. “virtual local area communication network”
`This term appears in independent claims 1 and 4. In our Institution
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`Decision, we construed “virtual local area communication network” as “a
`local area network of computer processors that is at least in part simulated
`by software.” Dec. 6–8. Petitioner does not object to our construction.
`Reply 6. Patent Owner states that although it sought a different construction
`pre-institution, it applies the Board’s construction in its Response. PO Resp.
`32.
`However, Patent Owner seeks clarification as to what it means to
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`“simulate” part of a “local area network” with “software.” Id. at 33. Patent
`Owner asserts that in the context of the ’044 patent, a person of ordinary
`skill in the art would understand there are two possible relevant types of
`virtualization or simulation: (1) using software to configure a network
`topology with interconnections of specified computers and network
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`equipment; and (2) using software to implement network equipment itself.
`Id. Patent Owner argues it is the second type that is required by the ’044
`patent. Id. Patent Owner argues the specification makes clear that the
`defined and established network recited in claims 1 and 4 includes software-
`implemented network equipment. Id. at 33 (citing Ex. 1001, 3:65–4:13,
`4:16–28); see also Ex. 2015 ¶¶ 76–78 (Dr. Chao’s testimony that the claims
`and specification of the ’044 patent require the virtualized or simulated
`network to include at least some software to implement network equipment).
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`Petitioner asserts that Patent Owner repackages its pre-institution
`argument and that the Board correctly rejected Patent Owner’s earlier
`proposed requirement for “the network to be entirely simulated by
`software.” Reply 6–7 (citing Dec. 7). Petitioner further asserts that Dr.
`Chao’s suggestion that the ’044 patent disclaimed virtualization involving
`“configuring VLAN switches” (Ex. 2015 ¶ 75) contradicts the specification,
`which describes connections in redundant pairs going through one of two
`switch fabrics 115a,b. Id. at 7 (citing Ex. 1001, 11:57–60). Petitioner
`asserts that, as confirmed by the named co-inventors, switch fabrics 115a,b
`are physical switches. Id. (citing Ex. 1034, 38:14–39:19; Ex. 1033, 34:2–
`12). Petitioner argues that testimony by the named co-inventor supports the
`Board’s construction, which allows for the use of physical networking
`equipment by requiring only partial simulation by software. Id. at 7–8.
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`We are not persuaded by Patent Owner’s argument that the ’044
`patent requires a virtual local area communication network to use software
`to implement network equipment. The portions of the specification cited by
`Patent Owner disclose that each processing area network (PAN) “is
`configured to have a corresponding subset of processors 106 that may
`communicate via a virtual local area network emulated over the PtP mesh”
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`and that “[u]nder certain preferred embodiments, software logic . . . emulates
`switched Ethernet semantics.” Ex. 1001, 3:67–4:8. The cited portions
`further disclose “[c]ertain preferred embodiments allow an administrator to
`build virtual, emulated LANs using virtual components, interfaces, and
`connections” and that “the virtual networks so created emulate a switched
`Ethernet network, though the physical, underlying network is a PtP mesh.”
`Id. at 4:16–24. Neither Patent Owner, nor Dr. Chao, explain why the cited
`portions of the specification require the local area communication network
`to use software to implement network equipment. See PO Resp. 32–34;
`Ex. 2015 ¶¶ 76–78. Nor do we read such a requirement in the specification.
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`Although certain preferred embodiments may emulate switched
`Ethernet semantics, the ’044 patent does not require software to implement
`network equipment. Rather, the ’044 patent describes the virtual network
`emulates a switched network through an underlying PtP mesh, which is a
`physical network that uses switch fabrics 115a,b. See Ex. 1001, 3:20–23,
`4:22–24; see also Dec. 7 (“[T]he ’044 patent describes the virtual local area
`network is emulated over a PtP mesh (physical network) and thus, there is a
`physical component to the network.”). We agree with Petitioner that the
`testimony of the ’044 patent’s co-inventors, Peter Manca and Scott Geng,
`confirms the fact that switch fabrics 115a,b are physical switches. See Ex.
`1034, 39:4–19 (Mr. Manca’s testimony that the switch fabrics described in
`column 3, around line 50, are physical components); Ex. 1033, 34:2–12 (Mr.
`Geng’s testimony that “there was connectivity between the Giganet card on
`the application node and the actual switch itself -- two switches, one
`connection to each switch”). Because the ’044 patent describes the virtual
`local area communication network uses an underlying physical switch
`network, we do not agree with Patent Owner that the virtualization software
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`must implement network equipment itself or that the ’044 patent excludes
`using software to configure a network topology with interconnections of
`specified computers and network equipment (type 1).
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`On the complete record, we maintain our construction of “virtual
`local area communication network” to be “a local area network of computer
`processors that is at least in part simulated by software.” Our construction
`does not require the use of software to implement network equipment.
`2. “computer processor”
`This term appears in independent claims 1 and 4. Patent Owner
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`asserts the issue as to this term is whether computer processors may be
`located on the control node or whether they must be separate from the
`control node. PO Resp. 34. Patent Owner asserts that the latter is the only
`reasonable reading of the term. Id.
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`Petitioner asserts we should reject Patent Owner’s construction
`because the claims do not recite a “control node” and it would be improper
`to read such a limitation into the claims. Reply 8. Petitioner further asserts
`Patent Owner does not identify any issue relating to the construction of
`“computer processor,” so the term is not in dispute and does not require
`construction. Id.
`As noted by Petitioner, the claims do not recite a “control node”
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`limitation; accordingly, we disagree with Patent Owner that there is any
`issue as to whether the recited “computer processors” reside on an element
`not set forth in the claim. Rather, we agree with Petitioner that Patent
`Owner does not identify any issue relating to the proffered construction of
`“computer processor.” See PO Resp. 34. To the extent Patent Owner
`intends its arguments to apply to distinguishing the recited “computer
`processors” from the recited “configuration logic,” Patent Owner does not
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`include any arguments in its Response that the asserted prior art fails to
`disclose a computer processor separate from configuration logic. See id.
`Accordingly, we do not find it necessary to construe this term. See Vivid
`Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999)
`(explaining that “only those terms need be construed that are in controversy,
`and only to the extent necessary to resolve the controversy”).
`3. Other terms
`Petitioner proposes a construction for “personality,” which appears in
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`claims 3 and 6. Pet. 12. Patent Owner does not address Petitioner’s
`construction. See PO Resp.
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`Patent Owner proposes a construction for “responsive to a failure of a
`computer processor” / “in response to a failure by a computer processor,”
`which appear in claims 1 and 4, respectively. See id. at 30–32. Petitioner
`has not stated any objection to Patent Owner’s construction.
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`Because these terms are not in controversy, we determine that we
`need not explicitly construe these terms to resolve the issues before us. See
`Vivid Techs., 200 F.3d at 803.
`D. Obviousness over Aziz and Ma
`Petitioner challenges claims 1, 3, 4, and 6 as obvious under 35 U.S.C.
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`§ 103(a) over Aziz and Ma. Pet. 22–61.
`1. Scope and Content of Aziz
`Aziz describes an extensible computing system based on a wide scale
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`computing fabric (“computing grid”). Ex. 1006, 4:13–14, 4:24–25. The
`computing grid is physically constructed once, and then logically divided up
`for various organizations on demand. Id. at 4:25–27. Each organization’s
`logical portion of the computing grid is referred to as a Virtual Server Farm
`(VSF), which can change dynamically in terms of numbers of central
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`processing units (CPUs), storage capacity, and disk and network bandwidth.
`Id. at 4:29–35.
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`Figure 2 of Aziz is reproduced below:
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`Figure 2 is a block diagram of one configuration of extensible computing
`system 200. Id. at 5:47–48. Extensible computing system 200 includes
`local computing grid 208, which is composed of a large number of
`computing elements (CPU1, CPU2, . . . CPUn). Id. at 5:52–54. The
`computing elements do not store long-lived state information, but instead
`state information is stored separately on disks (DISK1, DISK2, . . . DISKn)
`that are coupled to computing elements CPU1–CPUn via a Storage Area
`Network (SAN) comprising one or more SAN switches 202. Id. at 5:56–
`5:63. All of the computing elements are interconnected to each other
`through one or more VLAN switches 204, which can be divided up into
`Virtual Local Area Networks (VLANs). Id. at 5:66–6:1. VLAN switches
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`204 are coupled to Internet 106. Id. at 6:1–6:2. Control Plane 206 is
`coupled by SAN Control path, CPU Control path, and VLAN Control path
`to SAN switches 202, CPU1–CPUn, and VLAN switches 204, respectively.
`Id. at 6:13–16.
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`Aziz describes that configuration and control of the computing
`elements and their associated networking and storage elements is performed
`by the control plane. Id. at 4:54–59. For example, the control plane may
`configure a VLAN switch to place ports that are each coupled to a
`computing element on an indicated VLAN. See id. at Fig. 5A, 10:1–3. The
`control plane may similarly configure a SAN switch to place ports that are
`each coupled to a disk on a specified SAN zone. See id. at Fig. 5A, 10:3–5.
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`Aziz further describes that the computing grid may include an Idle
`Pool that comprises a large number of computing elements that are kept in
`reserve. Id. at 7:6–8. Computing elements from the Idle Pool may be
`assigned to a particular VSF to increase CPU or memory capacity, or to deal
`with failure of a particular computing element in a VSF. Id. at 7:8–12. In
`moving a computing element from the Idle Pool into a VSF (or vice-versa),
`the control plane configures LAN switches and SAN switches associated
`with a computing element to be part of the VLAN and SAN zones associated
`with a particular VSF (or the Idle Pool). See id. at 7:31–55.
`2. Scope and Content of Ma
`Ma describes providing high reliability to management of a cluster of
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`network devices, such as switches, bridges, and routers. Ex. 1007, 1:9–11,
`1:20–21. The cluster includes a command network device, with a
`commander internet protocol (IP) address and a commander media access
`control (MAC) address. Id. at 3:61–63. A virtual IP address and a virtual
`MAC address are assigned to an “active commander” (command network
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`device with the highest priority) and the active commander uses the virtual
`IP address and the virtual MAC address as its source IP and MAC addresses,
`respectively, instead of its own IP address and MAC address. See id. at
`6:61–7:7. If the active commander fails, a standby commander takes over
`the active commander role, and ownership of the virtual IP address and the
`virtual MAC address is transferred to the new active commander device.
`See id. at 7:24–32, 12:18–25.
`3. Prior Art Status of Ma
`Patent Owner contends that Ma is not prior art to the ’044 patent
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`because the claimed invention was conceived of before the earliest claimed
`priority date for Ma and thereafter diligently reduced to practice. PO Resp.
`36.
`In an inter partes review, the burden of persuasion is on the
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`petitioner to prove “unpatentability by a preponderance of the evidence,”
`35 U.S.C. § 316(e), and that burden never shifts to the patentee. Dynamic
`Drinkware, LLC v. Nat’l Graphics, Inc., 800 F.3d 1375, 1378 (Fed. Cir.
`2015). A petitioner also has the initial burden of production, or the burden
`of going forward with evidence. Id. at 1379. Petitioner met its initial burden
`of production by offering Ma into evidence and arguing that Ma is prior art
`under 35 U.S.C. § 102(e) to the ’044 patent. See Pet. 13. The burden of
`production then shifted to Patent Owner to produce evidence supporting a
`date of invention before Ma. See Dynamic Drinkware, 800 F.3d at 1379–80;
`Mahurkar v. C.R. Bard, Inc., 79 F.3d 1572, 1576–77 (Fed. Cir. 1996).
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`In order to show prior invention, Patent Owner must either prove:
`(1) a conception and reduction to practice before the filing date of Ma; or
`(2) a conception before the filing date of Ma combined with diligence and
`reduction to practice after that date. See REG Synthetic Fuels, LLC v. Neste
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`Oil Oyj, 841 F.3d 954, 958 (Fed. Cir. 2016) (citing Taurus IP, LLC v.
`DaimlerChrysler Corp., 726 F.3d 1306, 1323 (Fed. Cir. 2013)). Both parties
`agree that Ma is entitled to its December 15, 2000, filing date. Pet. 13; PO
`Resp. 36; see also Ex. 1007, (22) (indicating the filed date as December 15,
`2000). Thus, under either approach, Patent Owner must establish that
`conception occurred prior to December 15, 2000.
`a. Conception
`Conception is “the formation, in the mind of the inventor of a definite
`
`and permanent idea of the complete and operative invention, as it is
`thereafter to be applied in practice.” Coleman v. Dines, 754 F.2d 353, 359
`(Fed. Cir. 1985) (emphasis in original) (quoting Gunter v. Stream, 573 F.2d
`77, 80 (C.C.P.A. 1978)). A party claiming conception must show
`possession of every feature or limitation of the claimed invention. Davis v.
`Reddy, 620 F.2d 885, 889 (C.C.P.A. 1980). “Conception must be proved by
`corroborating evidence which shows that the inventor disclosed to others his
`‘completed thought expressed in such clear terms as to enable those skilled
`in the art’ to make the invention.” Coleman, 754 F.2d at 359 (quoting Field
`v. Knowles, 183 F.2d 593, 601 (C.C.P.A. 1950)). An inventor’s testimony,
`standing alone, is insufficient to prove conception—some form of
`corroboration must be shown. Price v. Symsek, 988 F.2d 1187, 1194 (Fed.
`Cir. 1993); see also Mahurkar, 79 F.3d at 1577 (Fed. Cir. 1996)
`(corroboration requirement “arose out of a concern that inventors testifying
`in patent infringement cases would be tempted to remember facts favorable
`to their case by the lure of protecting their patent or defeating another’s
`patent”).
`
`Patent Owner asserts that the subject matter of the claims of the ’044
`patent was conceived of by November 7, 2000. PO Resp. 5. Patent Owner
`
`
`
`
`
`
`16
`
`

`

`
`
`
`
`
`IPR2017-01340
`Patent 6,971,044 B2
`
`
`
`
`states that this is evidenced by internal Egenera documents from mid-to-late
`2000 related to Egenera’s Interframe (later called Bladeframe). Id. at 5–6
`(citing Exs. 2009, 2010, 2012, 2013, 2022, 2024). In support of its
`assertions, Patent Owner provides a chart summarizing where the subject
`matter of the limitations of each claim of the ’044 patent is found in the
`internal Egenera documents and cites to testimony of Dr. Chao (Ex. 2015)
`and Mr. Geng (Ex. 2008). PO Resp. 7–24.
`
`Petitioner argues that Patent Owner does not establish conception of
`“failover logic including logic to assign the virtual MAC address of the
`failed processor to the processor that replaces the failed processor,” as
`recited in claim 1, prior to Ma’s filing date. Reply 11–13. Petitioner asserts
`that, at best, the cited sections describe “simulated MAC addresses” and that
`“spare Application Processors can be configured as standby nodes, and can
`be rapidly booted with the same software configuration as an existing node,”
`but that neither description corroborates the specific language in the
`“failover logic” limitation. Reply 12 (citing PO Resp. 11–12, 16).
`Petitioner further asserts that there is no evidence a “simulated MAC
`address” would be included in the “software configuration” booted on a
`standby node, but rather the evidence indicates that a MAC address would
`not be reassigned from one node to another, since each node’s virtual MAC
`address includes its own “node number.” Id. at 12–13 (citing PO Resp. 12
`(quoting Ex. 2012, 6)); Ex. 2013, 11–12); see also Tr. 5 (“[Ex. 2012] says
`the simulated-MAC address ‘will include the node number.’ So, the node
`number, the number of a node, is particular to a MAC address for that
`node.”).
`
`As evidence of conception of “failover logic including logic to assign
`the virtual MAC address of the failed processor to the processor that
`
`
`
`
`
`
`17
`
`

`

`IPR2017-01340
`Patent 6,971,044 B2
`
`
`
`
`
`
`
`
`
`replaces the failed processor” by November 7, 2000, Patent Owner asserts
`that
`
`
`
`
`
`
`Egenera’s Interframe platform included “failover logic,” . . .
`which when a processing blade/node failed, caused another
`blade/node to replace it, which included taking on the failed
`blade/node configuration/resources. As discussed in [1c], supra,
`this configuration includes virtual MAC addresses. Failover
`logic evidence is included in [1f], supra. Exemplary evidence is
`cited below.
`PO Resp. 19 (citing Exs. 2008 ¶¶ 14–33, 2009–2014, and 2022–2024). In
`the cited evidence, Mr. Geng testifies the “N+1 Blade fail over capability for
`entire Frame” mentioned in the Egenera Product Roadmap “allowed for any
`number of running servers to utilize a single spare compute node to replace
`any of the active compute nodes in case of failure.” Ex. 2008 ¶¶ 15, 16
`(citing Ex. 2011, 9). Mr. Geng further testifies “[t]he newly booted server
`running on the new compute node maintained the same network and storage
`personality (including the network MAC address) as the previously failed
`node.” Id. ¶ 16; see also id. ¶ 18 (“[T]he N+1 BladeFrame failover caused
`the server definition—including virtual interfaces with their MAC addresses,
`storage, and other aspects of the personality—to automatically be moved to
`a new processing node, which would then replace the failed node.”).
`
`Patent Owner also cites to testimony of Dr. Chao as evidence of
`conception of the limitation at issue. PO Resp. 19 (citing Ex. 2015 ¶¶ 116–
`119). Dr. Chao testifies that
`The Egenera documents support this limitation because they
`teach and discuss failover logic in the Interframe platform,
`including software on the Interframe Controller, which is able to
`respond to the failure of computer processors . . . by providing
`the replacement computer processor with the virtual, or
`simulated MAC address that had been used by the failed
`processor.
`
`18
`
`

`

`IPR2017-01340
`Patent 6,971,044 B2
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`. . .
`[U]pon failure Interframe software automatically allocates
`configurations from the failed computer processor to another
`computer processor.
`. . .
`[A] person of ordinary skill in the art would understand that the
`re-allocated configuration would include the virtual, or simulated
`MAC addresses.
`Ex. 2015 ¶¶ 116–118.
`
`Finally, as further evidence supporting conception antedating the Ma
`reference, Patent Owner points to “evidence cited in [1c] and [1f], supra.”
`PO Resp. 19. The identified sections discuss the conception of “wherein
`each computer processor in the virtual local area communication network
`has a corresponding virtual MAC address” (limitation 1c) and “failover
`logic, responsive to a failure of a computer processor, to allocate a computer
`processor from the plurality to replace the failed processor” (limitation 1f).
`Id. at 11–13 (discussing conception of limitation 1c), 15–19 (discussing
`conception of limitation 1f).
`
`Upon review of the evidence, we determine that Patent Owner has
`provided insufficient corroborating evidence to prove that the inventors of
`the ’044 patent conceived of failover logic “to assign the virtual MAC
`address of the failed processor to the processor that replaces the failed
`processor” by December 15, 2000. Although Mr. Geng testifies the Egenera
`Product

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