Trials@uspto.gov
`571.272.7822
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` Paper 10
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`Entered: November 13, 2017
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
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`CISCO SYSTEMS, INC.,
`Petitioner,
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`v.
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`EGENERA, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-01341
`Patent 7,231,430 B2
`____________
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`
`
`Before CHARLES J. BOUDREAU, WILLIAM M. FINK, and
`MELISSA A. HAAPALA, Administrative Patent Judges.
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`HAAPALA, Administrative Patent Judge.
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`
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`DECISION
`Denying Institution of Inter Partes Review
`37 C.F.R. § 42.108
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`IPR2017-01341
`Patent 7,231,430 B2
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`Cisco Systems, Inc. (“Petitioner”) filed a Petition pursuant to
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`35 U.S.C. §§ 311–319 to institute an inter partes review of claims 1–8 of
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`U.S. Patent No. 7,231,430 B2 (“the ’430 patent”). Paper 2 (“Pet.”).
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`Egenera, Inc. (“Patent Owner”) filed a Preliminary Response. Paper 7
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`(“Prelim. Resp.”). Pursuant to our authorization, Petitioner filed a Reply to
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`Patent Owner’s Preliminary Response. Paper 9. Applying the standard set
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`forth in 35 U.S.C. § 314(a), which requires demonstration of a reasonable
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`likelihood that Petitioner would prevail with respect to at least one
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`challenged claim, we deny Petitioner’s request and do not institute an inter
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`partes review.
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`I. BACKGROUND
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`A. The ’430 Patent (Ex. 1001)
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`The ’430 patent describes processing systems having virtualized
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`communication networks and storage for quick deployment and
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`reconfiguration. Ex. 1001, 1:17–19. The platform provides a large pool of
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`processors from which a subset may be selected and configured through
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`software commands to form a virtualized network of computers (“processing
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`area network” or “processor clusters”) that may be deployed to serve a given
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`set of applications or customer. Id. at 2:47–52. The virtualization may
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`include virtualization of local area networks (LANs) or the virtualization of
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`I/O storage. Id. at 2:55–57.
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`Figure 1 of the ’430 patent is reproduced below:
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`Patent 7,231,430 B2
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`Figure 1 illustrates a system diagram of a preferred hardware platform of the
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`invention. Id. at 2:21–22, 2:65. Hardware platform 100 includes processing
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`nodes 105a-105n connected to switch fabrics 115a, 115b via high-speed
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`interconnects 110a, 110b. Id. at 2:65–67. Switch fabrics 115a, 115b are
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`also connected to at least one control node 120a, 120b in communication
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`with external Internet Protocol (IP) network 125 and storage area network
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`(SAN) 130. Id. at 3:1–4.
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`Each control node 120a, 120b communicates with SAN 130 via
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`channel adapter card 128. Id. at 3:26–27. Control nodes 120a, 120b
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`communicate with Internet 125 (or other external network) via external
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`network interface 129. Id. at 3:28–30. Management application 135 may
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`access one of more of control nodes 120a, 120b via IP network 125 to assist
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`in configuring platform 100 and deploying virtualized Processing Area
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`Networks (PANs). Id. at 3:4–8. In some embodiments, processing nodes
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`105a–105n, control nodes 120a, 120b, and switch fabrics 115a, 115b are
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`contained in a single chassis and interconnected via a fixed, pre-wired mesh
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`of point-to-point (PtP) links. Id. at 3:9–12. Figure 1 depicts additional
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`components not described.
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`Under software control, the platform supports multiple, simultaneous,
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`and independent PANs, which are each configured to have a corresponding
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`subset of processors that may communicate via a virtual local area network
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`that is emulated over the PtP mesh. Id. at 3:53–58. An administrator defines
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`the network topology of a PAN. Id. at 5:56–57. The virtual local area
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`network provides communication among a set of computer processors, but
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`excludes processors not in the defined set. Id. at 2:11–15. A virtual storage
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`space is also defined and established with a defined correspondence to the
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`address space of a storage network. Id. at 2:15–16. Logic at the control
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`node translates or transforms the addresses and commands as necessary from
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`a PAN and transmits them accordingly to the SAN, which services the
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`commands. Id. at 21:39–42.
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`The ’430 patent further describes that control node-side networking
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`logic may include a virtual LAN server. Id. at 6:40–47. The virtual LAN
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`server services external connection by moving packets between external
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`Ethernet driver and internal processors. Id. at 15:15–18. It intercepts and
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`process packets from and to the external domain and handles IP address not
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`configured locally. See id. at 15:7–9, 15:27–30
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`B. Illustrative Claim
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`Claims 1, 3, 4, 5, 7, and 8 are independent claims. Claim 3 is
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`illustrative of the subject matter of the claims at issue:
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`3. A platform for automatically deploying at least one
`virtual processing area network, in response to software
`commands, said platform comprising:
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`a plurality of computer processors connected to an
`internal communication network;
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`at least one control node in communication with an
`external communication network and in communication with an
`external storage network having an external storage address
`space. wherein the at least one control node is connected to the
`internal communication network and thereby in communication
`with the plurality of computer processors, said at least one
`control node including logic to receive messages from the
`plurality of computer processors, wherein said received
`messages are addressed to the external communication network
`and to the external storage network and said at least one control
`node including logic to modify said received messages to
`transmit said modified messages to the external communication
`network and to the external storage network;
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`configuration logic for receiving and responding to said
`software commands, said software commands specifying (i) a
`number of processors for a virtual processing area network (ii) a
`virtual local area network topology defining interconnectivity
`and switching functionality among the specified processors of
`the virtual processing area network, and (iii) a virtual storage
`space for the virtual processing area network, said configuration
`logic including logic to select, under programmatic control, a
`corresponding set of computer processors from the plurality of
`computer processors, to program said corresponding set of
`computer processors and the internal communication network
`to establish the specified virtual local area network topology,
`and to program the at least one control node to define a virtual
`storage space for the virtual processing area network, said
`virtual storage space having a defined correspondence to a
`subset of the external storage address space of the external
`storage network;
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`wherein the at least one control node receives, via the
`internal communication network, storage messages from said
`corresponding set of computer processors, and wherein the at
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`least one control node includes logic to extract an address from
`a received storage message, to identify the defined
`corresponding address in the external storage address space,
`and to provide messages on the external storage network
`corresponding to the received storage messages and having the
`corresponding address; and
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`wherein the at least one control node includes logic to
`buffer data corresponding to write messages received from a
`computer processor of said corresponding set of computer
`processors and to provide the buffered data in the
`corresponding message provided to the external storage
`network.
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`C. References
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`Petitioner relies on the following references:
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`1. U.S. Patent No. 6,597,956, issued July 22, 2003 (“Aziz”)
`(Ex. 1006).
`2. U.S. Patent No. 7,089,293, issued Aug. 8, 2006 (“Grosner”)
`(Ex. 1007).
`3. U.S. Patent No. 6,639,901, issued Oct. 28, 2003 (“Katzri”)
`(Ex. 1009).
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`D. Grounds Asserted
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`Petitioner challenges the patentability of the claims of the ’430 patent
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`under 35 U.S.C. § 103(a) over the following combinations of references:
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`References
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`Aziz and Grosner
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`Aziz, Grosner, and Katzri
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`Claims
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`3, 4, 7, 8
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`1, 2, 5, 6
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`E. Related Proceedings
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`Petitioner and Patent Owner identify the following related district
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`court litigation: Egenera, Inc. v. Cisco Systems, Inc. (1-16-cv-11613,
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`D. Mass). Pet. 5; Paper 5, 1. Petitioner also filed a petition for inter partes
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`IPR2017-01341
`Patent 7,231,430 B2
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`review of claims 1–6 of U.S. Patent No. 6,971,044 B2 (IPR2017-01340,
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`Paper 1), which Patent Owner identifies as a related proceeding. Paper 5, 2.
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`II. ANALYSIS
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`A. Claim Construction
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`In an inter partes review, claims of an unexpired patent are
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`interpreted using the broadest reasonable construction in light of the
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`specification of the patent in which they appear. See 37 C.F.R. § 42.100(b);
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`Cuozzo Speed Techs., LLC v. Lee, 136 S. Ct. 2131, 2144–46 (2016). Under
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`that standard, claim terms are generally given their ordinary and customary
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`meaning, as would be understood by one of ordinary skill in the art in the
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`context of the entire disclosure. In re Translogic Tech., Inc., 504 F.3d 1249,
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`1257 (Fed. Cir. 2007).
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`Petitioner does not propose any terms for express construction. Pet.
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`9. Patent Owner proposes a construction for “virtual processing area
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`network.” Prelim. Resp. 44–47.
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`In view of our analysis, we do not find it necessary to construe any
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`terms for purposes of this Decision. See Vivid Techs., Inc. v. Am. Sci. &
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`Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999) (holding that “only those
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`terms need be construed that are in controversy, and only to the extent
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`necessary to resolve the controversy”).
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`B. Obviousness over Aziz and Grosner
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`Petitioner contends that claims 3, 4, 7, and 8 are unpatentable as
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`obvious under 35 U.S.C. § 103(a) over Aziz and Grosner. Pet. 22–82. For
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`the reasons discussed below, Petitioner fails to demonstrate a reasonable
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`likelihood of prevailing on this ground.
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`1. Overview of Aziz
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`Aziz describes controlling and managing highly scalable, highly
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`available and secure data processing sites, based on a wide scale computing
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`fabric (“computing grid”). Ex. 1006, 3:17–22. The computing grid is
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`physically constructed once, and then logically divided up for various
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`organizations on demand. Id. at 3:22–24. Each organization’s logical
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`portion of the computing grid is referred to as a Virtual Server Farm (VSF),
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`which can change dynamically in terms of numbers of central processing
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`units (CPUs), storage capacity, and disk and network bandwidth. Id. at
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`5:11–16. Each VSF is composed of a set of Virtual Local Area Networks
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`(VLANs), a set of computing elements that are attached to the VLANs, and
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`a subset of storage available on a SAN. Id. at 6:66–7:2. A set of Web pages
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`may be provided to enable a customer to create a custom VSF by specifying
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`a number of tiers, the number of computing elements in a particular tier, and
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`the hardware and software platform used for each element. Id. at 23:26–31.
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`Figure 2 of Aziz is reproduced below:
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`Figure 2 is a block diagram of one configuration of extensible computing
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`system 200. Id. at 6:28–30. Extensible computing system 200 includes
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`local computing grid 208, which is composed of a large number of
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`computing elements (CPU1, CPU2, . . . CPUn). Id. at 6:33–35. The
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`computing elements do not store long-lived state information, but instead
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`state information is stored separately on disks (DISK1, DISK2, . . . DISKm)
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`that are coupled to computing elements CPU1–CPUn via a SAN comprising
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`one or more SAN switches 202. Id. at 6:37–44. All of the computing
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`elements are interconnected to each other through one or more VLAN
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`switches 204, which can be divided up into VLANs. Id. at 6:47–49. VLAN
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`switches 204 are coupled to Internet 106. Id. at 6:49–50. Control Plane 206
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`is coupled by SAN Control path, CPU Control path, and VLAN Control path
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`to SAN switches 202, CPU1–CPUn, and VLAN switches 204, respectively.
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`Id. at 6:62–65.
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`Aziz further describes that the control plane performs configuration
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`and control of the computing elements and their associated networking and
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`storage elements. Id. at 5:34–41. The control plane is implemented on a
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`completely independent set of computing elements assigned for supervisory
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`purposes. Id. at 5:44–46. Computers used to implement the control plane
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`are logically invisible to computers in the computing grid (and therefore in
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`any specific VSF) and cannot be attacked or subverted in any way via
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`elements in the computing grid. Id. at 5:56–60.
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`Initially, all storage devices and computing elements are assigned to
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`Idle Pools. Id. at 3:35–36. The supervisory mechanism (control plane)
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`dynamically configures the VLAN switches and SAN switches to couple
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`their ports to one or more computing elements and storage devices. Id. at
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`3:36–39. For example, the control plane may configure a VLAN switch to
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`place ports that are each coupled to a computing element on an indicated
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`VLAN. See id. at Fig. 5, 10:58–60. The control plane may similarly
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`configure a SAN switch to place ports that are each coupled to a disk on a
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`specified SAN zone. See id. at Fig. 5, 10:60–62. As a result, such elements
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`and devices are logically removed from Idle Pools and become part of one or
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`more VSFs. Id. at 3:39–42.
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`2. Overview of Grosner
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`Petitioner asserts that Grosner is prior art under 35 U.S.C. § 102(e)
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`because it is entitled to claim the benefit of the filing date of U.S.
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`Provisional Application No. 60/245,295, filed November 2, 2000 (“the ’295
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`provisional”). Pet. 10–21. Patent Owner argues that Grosner is not prior art
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`to the ’430 patent because the claimed invention was conceived by
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`September 29, 2000, and constructively reduced to practice on April 21,
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`2001. Prelim. Resp. 47–57; see also id. at 5–57 (discussing conception and
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`reduction to practice of the claimed invention). Petitioner responds that
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`Patent Owner’s evidence is not sufficient to support the September 29, 2000
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`conception date because it lacks description of multiple claimed features.
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`Paper 9, 2–5.
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`For the reasons that follow, we determine that even assuming
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`Grosner qualifies as prior art, Petitioner fails to meet its burden in
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`establishing a reasonable likelihood of prevailing on its challenge to claims
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`3, 4, 7, and 8 as obvious over Aziz and Grosner. Therefore, for purposes of
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`this Decision, we do not need to determine whether the ’430 patent is
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`entitled to the earlier priority date.
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`Grosner describes seamlessly interconnecting disparate storage
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`devices and networks that may employ different protocols. Ex. 1008, 3.1
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`Grosner’s software and hardware system (“Pirus box”) enables servers,
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`network-attached storage (NAS) devices, and IP and Fibre Channel switches
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`on SANs, WANs, and LANs to interoperate by routing, switching, and
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`bridging multiple protocols over a variety of links. Id. at 7. The Pirus box
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`performs network address translation (NAT) to translate from one IP address
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`to another IP address and intelligent forwarding and filtering to support load
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`balancing. Id. at 38, 65.
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`3. Claims 3, 4, 7, and 8
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`Claims 3 and 4 recite “at least one control node is connected to the
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`internal communication network . . . , said at least one control node
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`1 Petitioner’s citations to Grosner are to the ’295 provisional (Ex. 1008),
`which is incorporated by reference in Grosner. Pet. 21; see also Ex. 1007,
`1:8–10 (incorporating the ’295 provisional by reference). We similarly cite
`to the ’295 provisional when discussing Grosner and also similarly cite to
`the page numbers added by Petitioner in accordance with 37 C.F.R.
`§ 42.63(d)(2)(ii). See id. at 21–22.
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`including logic to receive messages from the plurality of computer
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`processors” (“control node” limitation). Claims 7 and 8 are method claims
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`that recite limitations substantially similar to the “control node” limitation.
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`Petitioner relies on the combined teachings of Aziz and Grosner to teach the
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`“control node” limitation. See Pet. 40–44, 46–50; see also id. at 73, 77–78,
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`81, 82 (citing to analysis of claim 3 for the similar recitations set forth in
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`claims 4, 7, and 8).
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`Specifically, Petitioner asserts the functions of Aziz’s VLAN
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`switches, SAN switches, and control plane together provide all of the
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`features ascribed to the “at least one control node.” Id. at 40–41 (citing
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`Ex. 1006, Fig. 2 (annotated by Pet.)). Petitioner further asserts Grosner
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`discloses the “control node” through its teachings of a Pirus box that
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`performs control functions, provides servers with VLAN support, and
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`includes similar components as the control node in the ’430 patent. Id. at
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`41–42 (citing Ex. 1008, 7, 10, 24, 31). Petitioner proposes to combine
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`Aziz’s VLAN switches, SAN switches, and control plane into a single
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`“control node” as disclosed by Grosner’s Pirus box and asserts a person of
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`ordinary skill would have known to connect Aziz’s computing elements,
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`external storage network, and external communication network to Grosner’s
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`Pirus box. See id. at 26–27, 43–44.
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`Additionally, Petitioner argues Aziz teaches its VLAN switches,
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`control plane, and computing elements are connected to Aziz’s internal
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`communication network and that it would have been obvious to a person of
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`ordinary skill in the art that Grosner’s Pirus box (“control node”) would
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`similarly have the ability to connect to an internal communication network.
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`Id. at 46–48. Petitioner also argues the combination of Aziz and Grosner
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`teaches that the control node receives messages from the plurality of
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`computer processors because Aziz discloses the VLAN switches (part of the
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`control node) receives messages from the computing elements and Grosner
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`discloses its Pirus box processes packets from servers and would, therefore,
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`have the ability to receive packets from Aziz’s computing elements. Id. at
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`48–50. In support of its assertions, Petitioner relies on the testimony of its
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`expert, Dr. Prashant Shenoy. See Pet. 40–44, 46–50 (citing Ex. 1004).
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`We have reviewed the record and determine Petitioner does not
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`establish sufficiently that the combination of Aziz and Grosner teaches or
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`suggests the “control node” limitation. This limitation requires the control
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`node both be connected to the internal communication network and to
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`receive messages from the plurality of computer processors. Petitioner
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`asserts Aziz’s VLAN switches that can be divided up into VLANs, the
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`control plane, and the CPU Control path disclose the recited “internal
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`communication network.” Id. at 36. In support of this assertion, Petitioner
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`provides an annotated version of Aziz’s Figure 2, depicted below:
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`The annotated version of Figure 2 illustrates Petitioner’s mapping of the
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`claimed internal communication network to the VLAN switches, control
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`plane, and CPU control path disclosed by Aziz.
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`Petitioner then asserts that the functions of Aziz’s VLAN switches,
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`SAN switches, and control plane provide the features ascribed to the “at
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`least one control node.” Id. at 40–41. In support of this assertion, Petitioner
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`provides a second annotated version of Aziz’s Figure 2, depicted below:
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`The second annotated version of Figure 2 illustrates Petitioner’s mapping of
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`the claimed control node functions to the VLAN switches, SAN switches,
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`and control plane disclosed by Aziz. But Petitioner has already mapped the
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`VLAN switches and control plane of Aziz to the internal communication
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`network, and, therefore, identifies these components as both the internal
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`communication network and the control node functions. For instance,
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`Petitioner asserts both: (1) that the VLAN switches interconnected to the
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`computing elements disclose the internal communication network; and
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`(2) that the VLAN switches, as part of the control node, would receive
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`messages from the computing elements. Pet. 36, 49. Such reliance on the
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`same component for multiple claim elements is improper. See Becton,
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`Dickinson & Co. v. Tyco Healthcare Grp., LP, 616 F.3d 1249, 1254 (Fed.
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`Cir. 2010) (“Where a claim lists elements separately, ‘the clear implication
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`of the claim language’ is that those elements are ‘distinct component[s]’ of
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`the patented invention.”). Furthermore, as previously discussed, Petitioner
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`proposes to replace these components with Grosner’s Pirus box. See Pet.
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`26–27, 43–44. Petitioner does not sufficiently establish or explain how the
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`proposed combination discloses both the control node and the internal
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`network to which the control node is coupled. Moreover, we observe that
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`Petitioner relies on Aziz’s control plane and VLAN switches as disclosing
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`additional limitations of claims 3, 4, 7, and 8 but does not explain how those
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`additional limitations would still be taught or suggested if Aziz were
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`modified by Grosner to replace the control plane and VLAN switches with
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`the Pirus box, according to the proposed combination. See, e.g., Pet. 62–63
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`(asserting Aziz’s control plane’s configuring computing elements and
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`VLAN switches to establish the topology of the VSF discloses the recited
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`control node to program the computer processors and internal
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`communication network to establish the specified virtual local area network
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`topology).
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`Additionally, we agree with Patent Owner that Petitioner has not met
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`its burden to show that a person of ordinary skill in the art would have
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`combined Aziz and Grosner in the alleged manner. See Prelim. Resp. 62–
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`67. Petitioner contends the combination is merely the combination of prior
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`art elements according to known methods to yield predictable results and
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`would provide benefits by reducing the number of hardware components,
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`such as reduced cost and complexity and improved reliability. See Pet. 26–
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`33. But, as noted by Patent Owner (Prelim. Resp. 64), Aziz specifically
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`discloses its control plane is implemented on a completely independent set
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`of computing elements and is meant to be logically invisible to computers in
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`the computing grid so that it cannot be attacked or subverted in any way via
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`elements in the computing grid. See Ex. 1006, 5:44–47, 5:56–60. We
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`determine this explicit disclosure teaches away from the combination
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`because it discredits and discourages combining Aziz’s control plane with its
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`VLAN switches into a single box (Grosner’s Pirus box) that would no longer
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`contain an independent set of computing elements invisible to the computers
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`in the computer grid from which it would receive messages. See In re
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`Fulton, 391 F.3d 1195, 1201 (Fed. Cir. 2004); In re Gurley, 27 F.3d 551,
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`553 (Fed. Cir. 1994). Petitioner’s stated reasons for combining Aziz with
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`Grosner are insufficient to overcome this strong teaching away from the
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`combination.
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`For the foregoing reasons, we conclude Petitioner has not
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`demonstrated a reasonable likelihood of prevailing in establishing claims 3,
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`4, 7, and 8 would have been obvious over Aziz and Grosner.
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`C. Obviousness over Aziz, Grosner, and Katzri
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`Petitioner contends that claims 1, 2, 5, and 6 are unpatentable as
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`obvious under 35 U.S.C. § 103(a) over Aziz, Grosner, and Katzri. See Pet.
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`82–91. These claims recite limitations substantially similar to the “control
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`node” limitation that discussed above. Petitioner does not assert that Katzri
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`teaches the “control node” limitation, but rather relies on its analysis for
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`claims 3 and 7 that Aziz and Grosner teach this limitation. See id. at 85, 88,
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`90. Accordingly, Petitioner fails to cure the deficiencies discussed
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`previously in Part II.B.3 supra and has not demonstrated a reasonable
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`likelihood of prevailing on this challenge.
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`16
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`IPR2017-01341
`Patent 7,231,430 B2
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`III. CONCLUSION
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`Petitioner has not demonstrated a reasonable likelihood of prevailing
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`on its challenges to claims 1–8 of the ’430 patent as set forth above.
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`IV. ORDER
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`In view of the foregoing, it is:
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`ORDERED that Petitioner’s request for inter partes review of claims
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`1–8 of U.S. Patent 7,231,430 is denied.
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`17
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`IPR2017-01341
`Patent 7,231,430 B2
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`PETITIONER:
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`David L. McCombs
`Theodore M. Foster
`HAYNES AND BOONE, LLP
`david.mccombs.ipr@haynesboone.com
`ipr.theo.foster@haynesboone.com
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`PATENT OWNER:
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`Christopher Bovenkamp
`John Campbell
`McKOOL SMITH P.C.
`cbovenkamp@mckoolsmith.com
`jcampbell@mckoolsmith.com
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`18
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