Paper 29
`Trials@uspto.gov
`571-272-7822 Entered: November 20, 2018
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`
`
`
`
`
`NVIDIA CORPORATION,
`Petitioner,
`
`v.
`
`POLARIS INNOVATIONS LIMITED,
`Patent Owner.
`
`____________
`
`Case IPR2017-01346
`Patent 8,161,344 B2
`____________
`
`
`
`Before MINN CHUNG, DANIEL J. GALLIGAN, and
`JOHN A. HUDALLA, Administrative Patent Judges.
`
`GALLIGAN, Administrative Patent Judge.
`
`
`FINAL WRITTEN DECISION
`Inter Partes Review
`35 U.S.C. § 318(a)
`
`
`
`
`
`
`Trials@uspto.gov
`571-272-7822 Entered: November 20, 2018
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`
`
`
`
`
`NVIDIA CORPORATION,
`Petitioner,
`
`v.
`
`POLARIS INNOVATIONS LIMITED,
`Patent Owner.
`
`____________
`
`Case IPR2017-01346
`Patent 8,161,344 B2
`____________
`
`
`
`Before MINN CHUNG, DANIEL J. GALLIGAN, and
`JOHN A. HUDALLA, Administrative Patent Judges.
`
`GALLIGAN, Administrative Patent Judge.
`
`
`FINAL WRITTEN DECISION
`Inter Partes Review
`35 U.S.C. § 318(a)
`
`
`
`
`
`
`
`IPR2017-01346
`Patent 8,161,344 B2
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`
`I. INTRODUCTION
`In this inter partes review, NVIDIA Corporation (“Petitioner”)
`challenges the patentability of claims 1, 2, 4, 8–12, 16, 18–20, 22, 26–30,
`43–45, and 48–51 of U.S. Patent No. 8,161,344 B2 (“the ’344 patent,”
`Ex. 1001), which is assigned to Polaris Innovations Limited (“Patent
`Owner”).
`We have jurisdiction under 35 U.S.C. § 6. This Final Written
`Decision, issued pursuant to 35 U.S.C. § 318(a), addresses issues and
`arguments raised during the trial in this inter partes review. For the reasons
`discussed below, we determine that Petitioner has proven by a
`preponderance of the evidence that claims 1, 4, 8–12, 16, 18, 43, 45, and 48–
`51 of the ’344 patent are unpatentable in this proceeding but has not proven
`by a preponderance of the evidence that claims 2, 19, 20, 22, 26–30, and 44
`are unpatentable. See 35 U.S.C. § 316(e) (“In an inter partes review
`instituted under this chapter, the petitioner shall have the burden of proving a
`proposition of unpatentability by a preponderance of the evidence.”).
`A. Procedural History
`On July 25, 2017, Petitioner requested inter partes review of claims 1,
`2, 4, 8–12, 16, 18–20, 22, 26–30, 43–45, and 48–51 of the ’344 patent.
`Paper 2 (“Pet.”). Patent Owner elected not to file a Preliminary Response.
`See Paper 7 (waiving right to file Preliminary Response). We instituted trial
`on all grounds of unpatentability, which are as follows:
`1. Whether claims 1, 2, 4, 8–12, 19, 20, 22, 26–30, 43–45, and 48–51
`
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`are unpatentable under 35 U.S.C. § 102(b) over ADSL;1
`2. Whether claims 16 and 18 are unpatentable under 35 U.S.C.
`§ 103(a) over the combined teachings of ADSL and Voith;2 and
`3. Whether claims 1, 2, 4, 8–12, 16, 18–20, 22, 26–30, 43–45, and
`48–51 are unpatentable under 35 U.S.C. § 103(a) over Grube. 3
`Paper 8 (“Dec. on Inst.”), 23.
`During the trial, Patent Owner filed a Response (Paper 14, “PO
`Resp.”), and Petitioner filed a Reply (Paper 18, “Pet. Reply”). An oral
`hearing was held on August 17, 2018, a transcript of which appears in the
`record. Paper 25 (“Tr.”). Following the hearing, with our authorization
`(Paper 26), the parties filed additional briefing addressing the broadest
`reasonable interpretation of “data arrangement alteration.” Papers 27, 28.
`B. Real Parties in Interest
`Patent Owner identifies itself, Wi-LAN Inc., and Quarterhill Inc. as
`real parties-in-interest. Paper 6, 2.
`C. Related Matters
`Petitioner and Patent Owner cite the following judicial matter
`involving the ’505 patent: Polaris Innovations Ltd. v. Dell Inc. & NVIDIA
`Corp., Case No. 4:16-cv-07005 (N.D. Cal.). Pet. 97; Paper 4, 2–3. The
`’344 patent is also at issue in IPR2017-01781, in which we are issuing a
`final written decision concurrently with this Decision.
`
`
`1 American National Standard for Telecommunications – Network and
`Customer Installation Interfaces – Asymmetric Digital Subscriber Line
`(ADSL) Metallic Interface, ANSI T1.413-1998 c.1 (© 1999) (Ex. 1004).
`2 US 5,737,337, issued Apr. 7, 1998 (Ex. 1006).
`3 US 5,606,577, issued Feb. 25, 1997 (Ex. 1005).
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`D. The ’344 Patent and Illustrative Claim
`The ’344 patent generally relates to circuits for error coding.
`Ex. 1001, Abstract, 1:11–12. Figure 1A, reproduced below, illustrates an
`embodiment of such a circuit.
`
`
`Figure 1A illustrates an error coding circuit having controller 110, input 102,
`first error coding path 120, second error coding path 130, and output 104.
`Ex. 1001, 3:27–30. As illustrated in Figure 1A, each of error coding paths
`120 and 130 has a data arrangement alteration device and an error coder.
`Ex. 1001, 3:30–34. The ’344 patent explains that control indicator 116 is
`used to select between the first and second error coding paths. Ex. 1001,
`4:41–47.
`Of the claims at issue in the present proceeding, claims 1, 16, 19, and
`43 are independent claims. Claim 1 is illustrative and is reproduced below.
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`A circuit for creating an error coding data block for a first
`1.
`data block, the circuit comprising:
`a first error coding path adapted to selectively create a first
`error coding data block in accordance with a first error coding;
`and
`
`a second error coding path adapted to selectively create a
`second error coding data block in accordance with a second error
`coding;
`the first error coding path and the second error coding path
`being selected as a function of a control indicator, and at least the
`first error coding path comprising a data arrangement alteration
`device.
`
`
`II. ANALYSIS
`A. Level of Ordinary Skill in the Art
`Petitioner’s declarant, Dr. Tredennick, testifies that “[a] person of
`ordinary skill in the art as of the time of the ’344 patent (POSITA) would
`have had a Bachelor’s degree in Electrical Engineering and at least 2 years
`of experience working in the field of semiconductor logic design.” Ex. 1003
`¶ 13. Neither Patent Owner, nor its declarant, Dr. Przybylski, offers a
`different assessment of the level of ordinary skill in the art. See Ex. 2002
`¶ 38 (“I am applying the definition of the level of experience of a person of
`ordinary skill in the art that has been put forward by Dr. Tredennick in his
`declaration. I do not necessarily agree with the definition offered there, but I
`do not presently believe that the exact level of experience of a person of
`ordinary skill impacts my opinions offered herein.”).
`Based on the evidence of record, we adopt Dr. Tredennick’s statement
`of the level of ordinary skill in the art with the exception of the language “at
`least.” Thus, we determine that the skill level of a person of ordinary skill in
`the art would have been that of a person with a bachelor’s degree in
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`electrical engineering and two years of experience working in the field of
`semiconductor logic design.
`B. Claim Interpretation
`In an inter partes review, claim terms in an unexpired patent are
`interpreted according to their broadest reasonable construction in light of the
`specification of the patent in which they appear. 37 C.F.R. § 42.100(b)
`(2016). In applying a broadest reasonable construction, claim terms
`generally are given their ordinary and customary meaning, as would be
`understood by one of ordinary skill in the art in the context of the entire
`disclosure. See In re Translogic Tech., Inc., 504 F.3d 1249, 1257
`(Fed. Cir. 2007). This presumption may be rebutted when a patentee, acting
`as a lexicographer, sets forth an alternate definition of a term in the
`specification with reasonable clarity, deliberateness, and precision. In re
`Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994). Furthermore, only terms that
`are in controversy need to be construed, and only to the extent necessary to
`resolve the controversy. See Nidec Motor Corp. v. Zhongshan Broad Ocean
`Motor Co., 868 F.3d 1013, 1017 (Fed. Cir. 2017) (citing Vivid Techs., Inc. v.
`Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999)). We determine
`it is necessary to construe expressly only the claim terms discussed below to
`resolve the disputed issues before us in this proceeding.
`1. Data Arrangement Alteration
`Each of the challenged claims recites a “data arrangement alteration
`device” or a “data arrangement alteration algorithm.” The broadest
`reasonable interpretation of “data arrangement alteration” is at issue in this
`case and in IPR2017-01781, but the disputes in each proceeding are
`different. Here, there are two main disputes, namely (1) what types of
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`operations are encompassed within “data arrangement alteration” and
`(2) whether data arrangement alteration must be performed at a block level.
`Following oral argument, we authorized the parties to file additional briefing
`addressing the broadest reasonable interpretation of “data arrangement
`alteration.” Papers 26, 27, 28.
`a. Operations encompassed within “data arrangement alteration”
`Petitioner argues that the “[t]he ’344 patent imposes no requirements
`on how ‘data arrangement alteration’ is achieved.” Paper 27, 2. In support,
`Petitioner cites the following disclosure in the ’344 patent: “Any
`implementations which may change an arrangement of data such that these
`data will be processed in an optimum manner for a subsequent error
`detection or correction algorithm may be considered as a potential data
`arrangement alteration device 222.” Ex. 1001, 10:34–38, cited in
`Paper 27, 3. According to Petitioner, “[t]hrough this disclosure, the
`’344 patent places no limit on how ‘data []arrangement alteration’ is
`achieved, and covers any rearrangement whether it is achieved through bit
`reordering, inversion, or other types of logical bit operations.” Paper 27, 3;
`see also Pet. Reply 6 (arguing that “alter[ing] the arrangement of the data by
`randomizing the data in a deterministic way that can be descrambled in the
`receiver” is within the broadest reasonable interpretation of “data
`arrangement alteration”). Patent Owner argues that Petitioner’s proposed
`interpretation “is so broad as to encompass a myriad of alterations that are
`understandable and reversible (e.g., y = x3) but which clearly are not
`arrangement alterations.” Paper 28, 5. We agree with Patent Owner. Even
`if the ’344 patent does not limit how data arrangement alteration is achieved,
`the arrangement of the data must be altered to give full effect to the claim
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`language. The portions of the specification of the ’344 patent cited by
`Petitioner confirm this.
`In one instance, the ’344 patent states:
`In the first error coding path 120, the first data
`arrangement alteration device 122 is adapted to create a second
`data block on the basis of the first data block, which comprises
`the given number of data in a second arrangement, and to output
`it to the first error coder 124.
`Ex. 1001, 3:63–67 (emphasis added), cited in Paper 27, 2. Another passage
`states:
`
`The data arrangement alteration device 222 is adapted to
`receive, at the input 222E or 102, a first data block comprising a
`given number of data in the first arrangement, and to generate,
`on the basis of the first data block, a second data block
`comprising
`the given number of data
`in a second
`arrangement . . . .
`Ex. 1001, 6:14–18 (emphasis added), cited in Paper 27, 2. These passages
`show that data arrangement alteration takes data and puts those data into a
`different arrangement. Petitioner also cites the ’344 patent’s disclosure of a
`deserializer changing the “representation” of data. Paper 27, 2–3 (citing
`Ex. 1001, 8:58–62, 9:2–7). But, in this operation, “the second data
`block 440 . . . comprises the same data, namely the 72 bits of the first data
`block 435 in a second arrangement which is different from the first
`arrangement of the first data block.” Ex. 1001, 9:32–35 (emphasis added).
`Petitioner also cites an example in the ’344 patent in which the burst length
`is halved from eight time pulses to four time pulses. Ex. 1001, 11:52–61,
`cited in Paper 27, 4. The ’344 patent describes that, in this scenario, only
`half of the bits (36 out of 72) “will be occupied with processable data.”
`Ex. 1001, 11:59–60. Petitioner contends that this describes an output of 72
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`bits that is larger and different than the input of only 36 bits. Paper 27, 4.
`The ’344 patent, however, describes providing “a further subarea of the
`matrix 420 for this mode, and to control the multiplexer 430, via the mode
`register 110, such that this subarea will be read out, so that, for example,
`only 36 of the 72 bits will be occupied with processable data.” Ex. 1001,
`11:56–60 (emphasis added). Thus, it is the subarea having the 36 bits of
`processable data that is read out. But even if Petitioner is correct that the
`output is larger than the input in this example, data arrangement alteration
`still requires an alteration of the arrangement of the input data, even if the
`output contains additional data.
`In all of the examples in the specification of the ’344 patent, therefore,
`the arrangement of the data is altered. We see nothing in the intrinsic record
`to support a conclusion that merely altering data satisfies the requirement of
`data arrangement alteration. Petitioner also cites Dr. Przybylski’s testimony
`that the word “alter” means “[t]o change in an understandable way.”
`Ex. 1020, 119:12–15, cited in Pet. Reply 18–19. Petitioner contends, under
`this definition of “alter,” “a reversible operation” that “changes the data in
`an ‘understandable way,’” allowing the original data to be regenerated, is
`within the broadest reasonable interpretation of “data arrangement
`alteration.” Pet. Reply. 19. But this describes data alteration, not
`necessarily data arrangement alteration.
`Petitioner also cites testimony from both parties’ declarants that
`Petitioner argues supports its contention that data arrangement alteration
`encompasses inverting data, which is an operation relied upon by Petitioner
`in IPR2017-01781 to teach data arrangement alteration. Paper 27, 2 (citing
`Ex. 1019 ¶¶ 60–61; Ex. 1029, 50:12–51:5; Ex. 1030, 148:13–150:1). This
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`extrinsic evidence, however, fails to explain how “data arrangement
`alteration,” as described in the ’344 patent, would have been understood. In
`light of the intrinsic record discussed above, we do not find the extrinsic
`evidence to be particularly useful in determining the broadest reasonable
`interpretation of “data arrangement alteration.” See Phillips v. AWH Corp.,
`415 F.3d 1303, 1318 (Fed. Cir. 2005) (en banc) (authorizing the
`consideration of extrinsic evidence in determining the meaning of claims but
`noting that it is “in general . . . less reliable than the patent and its
`prosecution history in determining how to read claim terms”).
`For its part, Patent Owner argues that “a ‘data arrangement alteration
`device’ should be interpreted as a device that can alter the arrangement of
`data in a data block.” PO Resp. 8–9 (emphasis added). As explained above,
`however, the specification of the ’344 patent describes a data arrangement
`alteration device as a device that alters the arrangement of data, not a device
`that merely has the capability to do it. Consider a data block of eight bits,
`having four 0s and four 1s, that goes into a device that inverts each bit. The
`result of the inversion operation will be eight bits having 1s where the 0s
`were and 0s where the 1s were. Although the device alters the data by
`inverting each bit, the arrangement of the data is also changed because the
`input data were evenly divided between 0s and 1s. This arrangement
`alteration, however, is merely a circumstance of the input data. Patent
`Owner’s proposed construction would encompass seemingly any data
`alteration device because there likely will be some input to the device that
`will result in the data’s arrangement being altered. This is not consistent
`with the description of the claimed subject matter in the specification of the
`’344 patent. See In re Smith Int’l, Inc., 871 F.3d 1375, 1382–83 (Fed. Cir.
`
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`2017) (quoting In re Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997)) (stating
`that the broadest reasonable interpretation “is an interpretation that
`corresponds with what and how the inventor describes his invention in the
`specification, i.e., an interpretation that is ‘consistent with the
`specification’”).
`Thus, “data arrangement alteration” requires the alteration of the
`arrangement of data, not merely the alteration of data.
`b. Data arrangement alteration at a block level
`Patent Owner argues that data arrangement alteration must be
`performed at a block level such that “each data block is encoded by itself
`completely and independently, without influence from any other data block
`coming before or after the processed data block.” PO Resp. 10; see also
`Paper 28, 1–4. Petitioner disagrees. Pet. Reply 8–11; Paper 27, 5. The
`following passage from the ’344 patent is instructive:
`A piece of data may be, for example, a bit, and a data word may
`consist of several bits, for example. It is possible for a data word
`to be formed of several bits which are received in a serial manner,
`i.e., successive in time, or to be formed by several bits which are
`received at the same time (parallel interface). In this context,
`what is meant by data block is a serial data word, a parallel data
`word, or a serial sequence of parallel data words, as is depicted,
`for example, by reference numeral 435 in FIG. 4. Embodiments
`of the data arrangement alteration device 222 are adapted to
`change any of these types of data blocks or all of them in
`accordance with at least one data arrangement alteration
`algorithm so as to optimize error detection, or at least to improve
`error detection as compared to an approach without any change
`in the data arrangement, by means of the subsequent error coding
`algorithms.
`Ex. 1001, 11:66–12:14. A data word may be several bits and a “data block”
`may be a data word. Thus, the ’344 patent uses the term “data block” to
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`refer to a grouping of data.
`Determining whether an arrangement of data is altered requires
`looking at a particular grouping of data from input to output. To that extent,
`we agree with Patent Owner that the ’344 patent describes performing data
`arrangement alteration on data blocks. The term “data block,” however, is
`not limited by the ’344 patent to any particular structure or length.
`Dr. Przybylski testifies that “[a] block of data as it is used in the
`’344 specification, and generally in the industry, is a unit of data that is
`conceptually, physically, or temporally treated as a single unit.” Ex. 2002
`¶ 48. Patent Owner argues that “[a] data block is an associated, delimited set
`of data.” PO Resp. 10. These definitions are not helpful in understanding
`what a data block is beyond how it is described in the ’344 patent—as a
`grouping of data.
`As to Patent Owner’s argument that in the claims “each data block is
`encoded by itself completely and independently, without influence from any
`other data block coming before or after the processed data block” (PO
`Resp. 10), we find no intrinsic support for imposing this negative limitation,
`which is not found in the claims, on “data arrangement alteration.” Rather,
`as discussed above, the specification of the ’344 patent describes that data
`arrangement alteration requires altering the arrangement of data. It does not
`impose a restriction that data arrangement alteration must be performed
`“without influence from any other data block coming before or after the
`processed data block.”
`Nor do the challenged claims require that all data in a particular block,
`or grouping of data, be rearranged. Claim 8 is instructive on this point.
`Claim 8 recites:
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`The circuit as claimed in claim 1, wherein the data arrangement
`alteration device is adapted to create a second data block,
`comprising a given number of data in a second arrangement, on
`the basis of the first data block comprising the given number of
`data in a first arrangement, in accordance with a data
`arrangement alteration algorithm.
`Ex. 1001, 14:59–64 (emphases added). Claim 8, therefore, uses the open-
`ended term “comprising,” which means that each data block may have data
`in addition to the “given number of data,” but the claim requires putting the
`“given number of data” into a different (second) arrangement. Thus, the
`challenged claims do not require that all data in a particular grouping of data
`be rearranged. By contrast, claim 39, which is not challenged, recites a
`device “adapted to convert a first data block to a parallel intermediate
`arrangement, so that all data of the first data block are arranged in parallel
`with one another.” Ex. 1001, 17:36–41 (emphasis added).
`c. Conclusion as to data arrangement alteration
`Based on the foregoing and upon considering the complete record, we
`determine that “data arrangement alteration device” is a device that alters the
`arrangement of data in a grouping of data. A “data arrangement alteration
`algorithm,” similarly, is an algorithm that specifies how to alter an
`arrangement of data in a grouping of data.
`2. Means-Plus-Function Limitations
`In the Decision on Institution, we addressed, but did not adopt,
`Petitioner’s proposed constructions for several means-plus-function
`limitations, and, instead, we set forth our own constructions. Dec. on Inst.
`5–9. For purposes of this Decision, it is necessary to discuss only two
`means-plus-function limitations, for which Petitioner’s proposed
`constructions are set forth in the table below.
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`Limitation
`
`Claim 19: means for selectively
`performing a first error coding so as
`to create a first error coding data
`block
`
`Claim 19: means for performing a
`data arrangement alteration
`algorithm
`
`Petitioner’s Proposed
`Function and Structure
`Function: selectively performing
`a first error coding so as to create a
`first error coding data block
`
`Structure: one or more devices,
`including a first error coder.
`Pet. 13–14 (citing Ex. 1001, 3:27–
`34, 3:57–4:25, 7:16–24, 13:45–67).
`Function: performing a data
`arrangement alteration algorithm
`
`Structure: a data arrangement
`alteration device. Id. at 14–15
`(citing Ex. 1001, 6:14–25, 6:42–65,
`7:10–24).
`
`In the Decision on Institution, we construed these terms as set forth in
`the table below.
`Limitation
`Claim 19: means for selectively
`performing a first error coding so as
`to create a first error coding data
`block
`
`Function and Structure
`Function: selectively performing
`a first error coding so as to create a
`first error coding data block
`
`Structure: first error coding path
`120 and equivalents. See Ex. 1001,
`3:27–34, 3:57–4:25, 5:53–64,
`Figs. 1A, 1E.
`Function: performing a data
`arrangement alteration algorithm
`
`Structure: data arrangement
`alteration devices 122, 132, and
`222 and equivalents. See id. at
`3:27–34, 5:65–6:25, 6:42–65,
`8:55–57, 10:34–45, Figs. 1–4.
`
`Claim 19: means for performing a
`data arrangement alteration
`algorithm
`
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`Dec. on Inst. 8–9.
`Patent Owner argues that our preliminary determination for “means
`for selectively performing a first error coding so as to create a first error
`coding data block” does not address the selectivity recited in the claim and
`argues that the corresponding structure includes the structure that adds
`selectivity, such as switches 112 and 114. Petitioner argues that switching
`structure is unnecessary because the paths selectively perform error coding
`based on whether they have received data. Pet. Reply 21–22. Petitioner also
`argues that claim 19’s recitation that the first and second means are “selected
`as a function of a control indicator” “confirms that the selection is between
`the two, distinct means and, thus, necessarily prior to and outside of either
`one.” Pet. Reply 22.
`This dispute is about whether additional structure, beyond that stated
`in our previous construction above, is required for performing the recited
`functions. Neither party asserts that the corresponding structure for “means
`for selectively performing a first error coding” does not include at least what
`we identify as corresponding structure above. Because Petitioner has not
`shown that either ADSL or Grube teaches the same or equivalent structure
`using our constructions outlined above, we need not address the parties’
`dispute as to whether additional structure is required. We, therefore, apply
`the constructions outlined in our Decision on Institution for “means for
`selectively performing a first error coding so as to create a first error coding
`data block” and “means for performing a data arrangement alteration
`algorithm.” See Dec. on Inst. 8–9.
`
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`C. Principles of Law
`To establish anticipation, each and every element in a claim, arranged
`as recited in the claim, must be found in a single prior art reference. Net
`MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1371 (Fed. Cir. 2008).
`Although the elements must be arranged or combined in the same way as in
`the claim, “the reference need not satisfy an ipsissimis verbis test,” i.e.,
`identity of terminology is not required. In re Gleave, 560 F.3d 1331, 1334
`(Fed. Cir. 2009).
`A patent claim is unpatentable under 35 U.S.C. § 103(a) if the
`differences between the claimed subject matter and the prior art are such that
`the subject matter, as a whole, would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said
`subject matter pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`(2007). The question of obviousness is resolved on the basis of underlying
`factual determinations including (1) the scope and content of the prior art;
`(2) any differences between the claimed subject matter and the prior art;
`(3) the level of ordinary skill in the art; and (4) any secondary
`considerations, if in evidence. Graham v. John Deere Co., 383 U.S. 1, 17–
`18 (1966).
`
`D. Anticipation by ADSL
`(Claims 1, 2, 4, 8–12, 19, 20, 22, 26–30, 43–45, and 48–51)
`Petitioner contends claims 1, 2, 4, 8–12, 19, 20, 22, 26–30, 43–45, and
`48–51 of the ’344 patent are unpatentable under 35 U.S.C. § 102(b) as
`anticipated by ADSL. Pet. 1, 4–9, 16–46.
`1. ADSL
`ADSL is a publication of the American National Standards Institute
`(ANSI) entitled Network and Customer Installation Interfaces – Asymmetric
`16
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`Digital Subscriber Line (ADSL) Metallic Interface, and it bears a copyright
`date of 1999. Ex. 1004. Citing the Declaration of Jessica Coral Sheldon-
`Hess, Petitioner contends ADSL is prior art under 35 U.S.C. § 102(b). Pet. 2
`(citing Ex. 1014, 4–5). Ms. Sheldon-Hess testifies that, based on ADSL’s
`Machine Readable Cataloging (MARC) record obtained from Illinois State
`Library, ADSL was available to the public as of 1999. Ex. 1014 ¶¶ 8–10.
`Patent Owner does not dispute the prior art status of ADSL.
`Petitioner’s evidence establishes that ADSL was publicly available as
`a printed publication more than one year before the U.S. filing date for the
`’344 patent, which is March 11, 2008. See Ex. 1001, [22]. Based on this
`evidence, we determine that ADSL qualifies as a prior art printed
`publication under 35 U.S.C. § 102(b).
`ADSL is a “standard [that] describes the interface between the
`telecommunications network and the customer installation in terms of their
`interaction and electrical characteristics. The requirements of this standard
`apply to a single asymmetric digital subscriber line (ADSL).” Ex. 1004, 1. 4
`ADSL describes an ADSL Transceiver Unit (ATU) supporting
`asynchronous transfer mode (ATM) having “[t]wo paths . . . between the
`Mux/Sync control and Tone ordering; the ‘fast’ path provides low latency;
`the interleaved path provides very low error rate and greater latency.”
`Ex. 1004, 10.
`
`
`4 We cite to the page numbers of the reference itself rather than to the
`Exhibit page numbers assigned by Petitioner.
`17
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`2. Claim 1
`a. First and second error coding paths
`Independent claim 1 is reproduced above and is directed to “[a] circuit
`for creating an error coding data block for a first data block.” Petitioner
`contends ADSL’s ATU-C (ADSL transceiver unit, central office end)
`discloses the claimed “circuit.” Pet. 16–17 (citing Ex. 1004, vi, 11, 25–40,
`Figs. 1, 3; Ex. 1003 ¶¶ 60–72).
`Claim 1 recites that the circuit comprises “a first error coding path
`adapted to selectively create a first error coding data block in accordance
`with a first error coding” and “a second error coding path adapted to
`selectively create a second error coding data block in accordance with a
`second error coding.” Claim 1 further recites “the first error coding path and
`the second error coding path being selected as a function of a control
`indicator.”
`With its anticipation analysis, Petitioner provides an annotated version
`of Figure 3 from ADSL, which is reproduced below.
`
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`In this annotated version of Figure 3 from ADSL, Petitioner identifies a
`“first error coding path” in red and a “second error coding path” in green.
`Pet. 17. Referring to Figure 3, ADSL discloses that “[t]wo paths are shown
`between the Mux/Sync control and Tone ordering; the ‘fast’ path provides
`low latency; the interleaved path provides very low error rate and greater
`latency.” Ex. 1004, 11.
`Petitioner contends that the “interleaved path” of ADSL’s Figure 3
`discloses the claimed “first error coding path” and that the “fast path”
`discloses the claimed “second error coding path.” Pet. 20–23. Petitioner
`contends each of these paths includes two error coding devices, CRC (cyclic
`redundancy check) device and FEC (forward error correction) encoder.
`19
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`Pet. 18–19 (citing Ex. 1004, 25; Ex. 1003 ¶¶ 60–72). According to
`Petitioner, both paths “create[] CRC and FEC codes, both of which are error
`coding blocks for message data that serves as a first data block.” Id. at 21,
`22 (citing Ex. 1004, 25–26, 32–33, 38–39, 87–88; Ex. 1003 ¶¶ 73–89).
`Petitioner contends these paths are “selected as a function of a control
`indicator,” as recited in claim 1. Id. at 23–25. In particular, Petitioner
`argues Virtual Path Identifier and Virtual Connection Identifier disclose the
`claimed control indicator. Id. Although Patent Owner does not provide
`specific arguments regarding these particular limitations of claim 1, the
`burden remains on Petitioner to demonstrate unpatentability. See Dynamic
`Drinkware LLC, v. Nat’l Graphics, Inc., 800 F.3d 1375, 1378 (Fed. Cir.
`2015). For the reasons explained below, we are persuaded by Petitioner’s
`arguments and evidence.
`ADSL discloses performing cyclic redundancy checks (CRC) in both
`the fast and the interleaved paths, after which a “Mux data frame” is
`generated, which is “the multiplexed, synchronized data after the crc has
`been inserted.” Ex. 1004, 25, 32–33. ADSL discloses Reed-Solomon
`coding as the forward error correction (FEC) coding, as a result of which a
`“FEC output data frame” is generated. Ex. 1004, 26, 38–39. Dr. Tredennick
`testifies that “ADSL uses the CRC codes and the FEC Reed-Solomon codes
`as error coding data blocks for error coding purposes” and that the CRC
`device and the FEC encoder are adapted to create error coding data blocks.
`Ex. 1003 ¶¶ 72, 73, 78. Based on this evidence, we find ADSL describes “a
`first error coding path adapted to selectively create a first error coding data
`block in accordance with a first error coding” and “a second error coding
`
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`path adapted to selectively create a second error coding data block in
`accordance with a second error coding.”
`We further find ADSL describes “the first error coding path and the
`second error coding path being selected as a function of a control indicator.”
`In particular, ADSL discloses that “[t]he ATM Layer performs cell
`multiplexing from and demultiplexing to the appropriate physical port (i.e.
`latency path - fast or i
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