Trials@uspto.gov
`Tel: 571-272-7822
`
`
`Paper 7
`Entered: November 20, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`PROMOS TECHNOLOGIES, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-01417
`Patent 7,375,027 B2
`____________
`
`
`Before JAMESON LEE, KEVIN F. TURNER, and
`JOHN A. HUDALLA, Administrative Patent Judges.
`
`LEE, Administrative Patent Judge.
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108(b)
`
`
`
`
`
`
`Tel: 571-272-7822
`
`
`Paper 7
`Entered: November 20, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`PROMOS TECHNOLOGIES, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-01417
`Patent 7,375,027 B2
`____________
`
`
`Before JAMESON LEE, KEVIN F. TURNER, and
`JOHN A. HUDALLA, Administrative Patent Judges.
`
`LEE, Administrative Patent Judge.
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108(b)
`
`
`
`
`
`
`
`IPR2017-01417
`Patent 7,375,027 B2
`
`I.
`
`INTRODUCTION
`
`A. Background and Summary
`
`On May 12, 2017, Petitioner1 filed a Petition (Paper 1, “Pet.”) to
`
`institute inter partes review of claims 1–10 of U.S. Patent No. 7,357,027 B2
`
`(Ex. 1001, “the ’027 patent”). Patent Owner2 did not file a preliminary
`
`response. To institute an inter partes review, we must determine that the
`
`information presented in the Petition shows “that there is a reasonable
`
`likelihood that the petitioner would prevail with respect to at least 1 of the
`
`claims challenged in the petition.” 35 U.S.C. § 314(a). Having considered
`
`the Petition and its supporting evidence, we determine that Petitioner has
`
`shown a reasonable likelihood that it would prevail in establishing the
`
`unpatentability of each of claims 1–10 of the ’027 patent.
`
`B. Related Matters
`
`Both Petitioner and Patent Owner have identified the following action
`
`as involving the ’027 patent: ProMOS Technologies, Inc. v. Samsung
`
`Electronics Co., Ltd., No. 1:16-cv-00335-SLR (D. Del.). Pet. 1, Paper 4. In
`
`that action, Patent Owner has asserted other patents against Petitioner.
`
`Pet. 1. Petitioner has filed inter partes review petitions against those other
`
`patents in IPR2017-01412, IPR2017-01413, IPR2017-01414, IPR2017-
`
`01415, IPR2017-01416, IPR2017-01418, and IPR2017-01419. Paper 4.
`
`Petitioner identifies these inter partes review proceedings, initiated by
`
`petitions filed by Petitioner, as involving additional patents asserted by
`
`Patent Owner against Petitioner in ProMOS Technologies, Inc. v. Samsung
`
`Electronics Co., Ltd., No. 1:15-cv-00898-SLR-SRF (D. Del.): IPR2017-
`
`
`1 Samsung Electronics Co., Ltd.
`
`2 ProMOS Technologies, Inc.
`
`2
`
`
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`IPR2017-01417
`Patent 7,375,027 B2
`
`00032; IPR2017-00033; IPR2017-00035; IPR2017-00036; IPR2017-00037;
`
`IPR2017-00038; IPR2017-00039; and IPR2017-00040. Pet. 1–2.
`
`C.
`
`The ’027 Patent
`
`
`
`The ’027 patent is directed to the field of manufacturing
`
`semiconductor devices, and more particularly to opening a contact via to a
`
`surface of a material in a semiconductor device. Ex. 1001, 1:6–9. The
`
`’027 patent explains that a problem with preexisting method of opening a
`
`contact via to a surface of a material in a semiconductor device is that the
`
`semiconductor material at the bottom of the contact via is etched twice, thus
`
`subjecting that material to damage. Id. at 1:13–30. Specifically, the
`
`’027 patent describes that in the prior art, a first etching step is applied
`
`which goes through a photoresist layer down to the surface of the
`
`semiconductor material, subjecting the surface to the effects of etching once.
`
`Id. at 1:19–21. After the first etching step, a liner material is applied to the
`
`via and the surface of the semiconductor material within the via. Id. at 1:21–
`
`23. Then, an anisotropic etching step is performed to remove the liner
`
`material at the bottom of the aperture, which has the undesirable effect of
`
`subjecting the surface of the semiconductor material within the via to the
`
`effects of etching a second time. Id. at 1:23–37.
`
`
`
`The ’027 patent discloses a method of providing a contact via to a
`
`surface of a material that avoids the damaging effects of the second etching
`
`step in prior art techniques. Id. at 1:38–48. Specifically, the ’027 patent
`
`describes:
`
`In one aspect of the invention, a contact via to a surface of a
`material is performed by forming a first dielectric layer on the
`surface, forming a second dielectric layer on the first dielectric
`layer, providing a first aperture which extends from a surface of
`the second dielectric layer toward the contact surface area of the
`
`3
`
`
`
`IPR2017-01417
`Patent 7,375,027 B2
`
`material for a distance which is less than a combined technique
`of the first and second dielectric layers. Next, a third dielectric
`layer is provided covering a surface of the aperture and an
`exposed surface of the first dielectric layer. A portion of the third
`dielectric layer and a portion of the first dielectric layer are
`removed to expose a portion of the contact surface area of the
`material.
`
`Id. at 1:48–59.
`
`
`
`Of all challenged claims, claim 1 is the only independent claim.
`
`Claim 1 is reproduced below:
`
`A method of providing a contact via to a surface
`1.
`
`of a substrate, the method comprising:
`
`forming a first dielectric layer on the surface;
`
`forming a second dielectric layer on the first dielectric layer;
`
`providing a first aperture which extends from a surface of the
`second dielectric layer toward the surface of the substrate
`for a distance which is less than a combined thickness of
`the first and second dielectric layers;
`
`providing a third dielectric layer covering a surface of the first
`aperture and an exposed surface of the first dielectric layer;
`and
`
`removing a portion of the third dielectric layer and a portion of
`the first dielectric layer to expose a portion of the surface of
`the substrate.
`
`Ex. 1001, 4:17–32.
`
`
`
`Notably, in the “providing a first aperture” step, the aperture
`
`does not extend all the way to the surface of the substrate because it
`
`starts at the surface of the second dielectric layer and extends for a
`
`distance that is less than the combined thickness of the first and
`
`second dielectric layers. The surface of the substrate is not exposed
`
`until the step of “removing a portion of the third dielectric layer and a
`
`portion of the first dielectric layer.”
`
`4
`
`
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`IPR2017-01417
`Patent 7,375,027 B2
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`
`
`Figure 3 of the ’027 patent is reproduced below:
`
`
`
`
`
`Figure 3 illustrates a cross-section of the semiconductor
`
`structure in the midst of contact via formation. Ex. 1001, 2:19–27.
`
`Protective layer 8 constitutes a first dielectric layer. Id. at 2:55–57.
`
`Reference numeral 9 designates a second dielectric layer that has been
`
`applied over first dielectric layer 8. Id. at 2:66–67. Initial via 11 has
`
`been etched through second dielectric layer 9 but does not extend
`
`through to the surface of semiconductor substrate 1. Id. at 3:3–6.
`
`
`
`Figure 5 of the ’027 patent is reproduced below:
`
`
`
`Figure 5 illustrates the deposition of third dielectric layer 15
`
`over the initial aperture and the exposed surface of the first dielectric
`
`
`
`5
`
`
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`IPR2017-01417
`Patent 7,375,027 B2
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`layer. Id. at 2:30–32; 3:35–45.
`
`
`
`Figure 6 of the ’027 patent is reproduced below:
`
`
`
`Figure 6 illustrates the results of an anisotropic etching step that
`
`completes the contact via by removing the portion of third dielectric
`
`layer 15 that sits atop dielectric layer 9 and the portion of dielectric
`
`layer 15 that sits atop first dielectric layer 8. Id. at 3:46–50. In
`
`addition, the portion of first dielectric layer 8 that covers source
`
`region 6. Id. at 3:50–53. Contact via 18, extending to the surface of
`
`substrate 1, has been formed. Id. at 3:58–60.
`
`C.
`
`Evidence Relied Upon by Petitioner
`
`Petitioner relies on the following references3:
`
`
`
`
`
`3 The ’027 patent was filed on October 12, 2004 and does not claim priority
`to any earlier application. Ex. 1001, [22].
`
`6
`
`
`
`IPR2017-01417
`Patent 7,375,027 B2
`
`Date
`Reference
`Koyama U.S. Pat. Pub. 2003/0049920 A1 March 13, 2003
`Ngo
`U.S. Pat. No. 6,060,393
`May 9, 2000
`Ono
`Jap. Pat. App. Pub. H10-144788 May 29, 1998
`Cronin
`U.S. Pat. No. 5,654,238
`Aug. 5, 1997
`
`Petitioner also relies on the Declaration of Gary Rubloff, Ph.D.
`
`Exhibit
`Ex. 1005
`Ex. 2012
`Ex. 10094
`Ex. 1008
`
`(Ex. 1002).
`
`E.
`
`The Asserted Grounds
`
`Petitioner asserts the following grounds of unpatentability (Pet. 3–4):
`
`Claim(s) Challenged
`
`Basis
`
`References
`
`1, 2, 4, 6–8, and 10
`
`§ 102(b)
`
`Ono
`
`3 and 5
`
`9
`
`§ 103(a)
`
`§ 103(a)
`
`Ono and Ngo
`
`Ono and Cronin
`
`1, 2, 4, 6–8, and 10
`
`§ 102(b)
`
`Koyama
`
`3 and 5
`
`9
`
`§ 103(a)
`
`§ 103(a)
`
`Koyama and Ngo
`
`Koyama and Cronin
`
`
`II.ANALYSIS
`
`To establish anticipation, each and every element in a claim, arranged
`
`as recited in the claim, must be found in a single prior art reference.
`
`Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1369 (Fed. Cir. 2008);
`
`Karsten Mfg. Corp. v. Cleveland Golf Co., 242 F.3d 1376, 1383 (Fed. Cir.
`
`2001). While the elements must be arranged in the same way as is recited in
`
`
`4 Exhibit 1009 is a compilation including Ono (pages 9–16), an English
`translation of Ono (pages 1–8), and an affidavit certifying the translation
`(page 17). Pet. 3 n.1.
`
`7
`
`
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`IPR2017-01417
`Patent 7,375,027 B2
`
`the claim, “the reference need not satisfy an ipsissimis verbis test.” In re
`
`Gleave, 560 F.3d 1331, 1334 (Fed. Cir. 2009); In re Bond, 910 F.2d 831,
`
`832–33 (Fed. Cir. 1990)). Identity of terminology between the anticipatory
`
`prior art reference and the claim is not required. For a reference to constitute
`
`a statutory bar, its disclosure must be “such that a skilled artisan could take
`
`its teachings in combination with his own knowledge of the particular art
`
`and be in possession of the invention.” In re LeGrice, 301 F.2d 929, 1134
`
`(CCPA 1962). Prior art references must be “‘considered together with the
`
`knowledge of one of ordinary skill in the pertinent art.’” In re Paulsen,
`
`30 F.3d 1475, 1480 (Fed. Cir. 1994).
`
`Also, “it is proper to take into account not only specific teachings of
`
`the reference but also the inferences which one skilled in the art would
`
`reasonably be expected to draw therefrom.” In re Preda, 401 F.2d 825, 826
`
`(CCPA 1968). As the Court of Appeals for the Federal Circuit recently
`
`explained, for anticipation, the dispositive question is whether one skilled in
`
`the art would reasonably understand or infer from a prior art reference that
`
`every claim element is disclosed in that reference. Eli Lilly v. Los Angeles
`
`Biomedical Research Institute, 849 F.3d 1073, 1074–75 (Fed. Cir. 2017).
`
`The question of obviousness is resolved on the basis of underlying
`
`factual determinations including: (1) the scope and content of the prior art;
`
`(2) any differences between the claimed subject matter and the prior art;
`
`(3) the level of ordinary skill in the art; and (4) objective evidence of
`
`nonobviousness. Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
`
`One seeking to establish obviousness based on more than one reference also
`
`must articulate sufficient reasoning with rational underpinning to combine
`
`teachings. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007).
`
`8
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`IPR2017-01417
`Patent 7,375,027 B2
`
`With regard to the level of ordinary skill in the art, we determine that
`
`no express finding is necessary, on this record, and that the level of ordinary
`
`skill in the art is reflected by the prior art of record. See Okajima v.
`
`Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001); In re GPAC Inc., 57 F.3d
`
`1573, 1579 (Fed. Cir. 1995); In re Oelrich, 579 F.2d 86, 91 (CCPA 1978).
`
`A. Claim Construction
`
`In an inter partes review, claim terms in an unexpired patent are
`
`interpreted according to their broadest reasonable construction in light of the
`
`specification of the patent in which they appear. 37 C.F.R. § 42.100(b);
`
`Cuozzo Speed Techs., LLC v. Lee, 136 S. Ct. 2131, 2142–46 (2016).
`
`Consistent with that standard, claim terms are generally given their ordinary
`
`and customary meaning, as would have been understood by one of ordinary
`
`skill in the art in the context of the entire disclosure. See In re Translogic
`
`Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007). There are, however, two
`
`exceptions to that rule: “1) when a patentee sets out a definition and acts as
`
`his own lexicographer,” and “2) when the patentee disavows the full scope
`
`of a claim term either in the specification or during prosecution.” Thorner v.
`
`Sony Comp. Entm’t Am. LLC, 669 F.3d 1362, 1365 (Fed. Cir. 2012).
`
`
`
`If an inventor acts as his or her own lexicographer, the definition must
`
`be set forth in the specification with reasonable clarity, deliberateness, and
`
`precision. Renishaw PLC v. Marposs Societa’ per Azioni, 158 F.3d 1243,
`
`1249 (Fed. Cir. 1998). “[T]he claims must ‘not be read restrictively unless
`
`the patentee has demonstrated a clear intention to limit the claim scope using
`
`words or expressions of manifest exclusion or restriction.’” Williamson v.
`
`Citrix Online, LLC, 792 F.3d 1339, 1347 (Fed. Cir. 2015).
`
`Only terms which are in controversy need to be construed, and only to
`
`the extent necessary to resolve the controversy. See Wellman, Inc. v.
`
`9
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`IPR2017-01417
`Patent 7,375,027 B2
`
`Eastman Chem. Co., 642 F.3d 1355, 1361 (Fed. Cir. 2011); Vivid Techs.,
`
`Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999). We see
`
`no need to construe expressly any claim term.
`
`B. Alleged Anticipation of Claims 1, 2, 4, 6–8, and 10 by Ono
`
`1.
`
`Ono
`
`
`
`Ono is directed to a method for manufacturing semiconductor devices
`
`having contacts. Ex. 1009 ¶ 1. Ono describes certain problems in prior art
`
`manufacturing techniques, including “formation of a damage layer at the
`
`bottom of contacts,” “enlargement of the contact diameter during etching of
`
`the bottom of contacts,” and increases of “contact resistance” or “junction
`
`leakage current.” Id. at [57]. Ono explains:
`
`The cause of [increases in contact resistance and junction leakage
`current] has been ascertained to be the presence of a layer
`containing oxygen and carbon, which is known as a so-called
`damage layer, in the contacts. Various methods of removing this
`damage layer have been reported at academic conferences and
`the like, but mass production technology capable of completely
`removing damage layers has not been established.
`
`Id. ¶ 3. Ono also describes how the damage layer is formed:
`
`The portion known as the damage layer is formed as a
`
`result of oxygen and carbon being driven into the substrate
`during etching of the interlayer insulation film having SiO2 as
`the main component using a resist having carbon as the main
`component as the mask, and as a result of oxygen in the
`interlayer insulation film being driven into the substrate due to
`reverse sputtering being performed for native oxide film
`removal prior to embedding of conductors into the contact
`holes.
`
`Id. ¶ 4.
`
`To solve the problem, Ono describes the following:
`
`semiconductor device manufacturing method
`[A]
`
`characterized in that it comprises: a step of forming a
`
`10
`
`
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`IPR2017-01417
`Patent 7,375,027 B2
`
`semiconductor coating layer which coats a semiconductor
`substrate; a step of forming an interlayer insulation film which
`covers said semiconductor coating layer; a step of forming a
`mask layer on said interlayer insulation film; a step of forming
`contact holes which penetrate said mask layer and said
`interlayer insulation film and reach said semiconductor coating
`layer; a step of forming a side wall layer which coats at least the
`side walls of said contact holes; and a step of etching said
`semiconductor coating layer to expose the surface of said
`semiconductor substrate.
`
`Id. ¶ 10 (emphases added).
`
`2.
`
`Claim 1
`
`
`
`Claim 1 recites: A method of providing a contact via to a surface of a
`
`substrate.” Ex. 1001, 4:17–18. As is noted by Petitioner (Pet. 10), Ono
`
`discloses such a method. Ex. 1009 ¶¶ 1, 9, 10, 25–23 (cited by Petitioner at
`
`Pet. 10). Petitioner’s assertion also is supported by the testimony of
`
`Dr. Rubloff. Ex. 1002 ¶¶ 53–58.
`
`
`
`Claim 1 further recites: “forming a first dielectric layer on the
`
`surface.” Ex. 1001, 4:19. Ono’s Figure 1(a) is reproduced below:
`
`Figure 1(a) illustrates Ono’s semiconductor device manufacturing method
`
`up to the step of forming a semiconductor coating layer. Ex. 1009 ¶ 49.
`
`
`
`Ono describes:
`
`Next, a silicon oxide gate electrode coating insulation film 21 is
`deposited through CVD over the entire surface to a thickness of
`approximately 20 nm, and on top of that, silicon nitride is
`
`11
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`
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`IPR2017-01417
`Patent 7,375,027 B2
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`deposited by CVD to approximately 40 nm to form a
`semiconductor coating layer 22, leading to the state of FIG. 1(a).
`
`Id. ¶ 26 (wherein “CVD” stands for chemical vapor deposition; see Ex. 1002
`
`¶ 83).
`
`
`
`Petitioner identifies the combined layers of (1) silicon oxide gate
`
`electrode coating insulation film 21 and (2) semiconductor coating layer 22
`
`formed of silicon nitride as a dielectric layer satisfying the first dielectric
`
`layer of claim 1. Pet. 11. Dr. Rubloff testifies that both silicon oxide and
`
`silicon nitride are dielectric materials. Ex. 1002 ¶ 60. On this record, we do
`
`not read “layer” so restrictively as to exclude internal sublayers.
`
`Furthermore, Dr. Rubloff explains that because source and drain regions 11
`
`are within the substrate and because the surface of source and drain regions
`
`11 is coplanar with the surface of the substrate, the surface of source and
`
`drain regions 11 is the same as the surface of semiconductor substrate 10.
`
`Id. ¶ 62. For purposes of this Decision, we are satisfied that Ono’s chemical
`
`vapor deposition of film 21 and layer 22 discloses the step of forming a first
`
`dielectric layer in the surface of the substrate.
`
`
`
`Claim 1 further recites: “forming a second dielectric layer on the first
`
`dielectric layer.” Ex. 1001, 4:20–21. Ono discloses this step. Specifically,
`
`Ono states: “Next, as shown in FIG. 1(b), interlayer insulation film 23 is
`
`formed over semiconductor coating layer 22, for example, by depositing
`
`BPSG to about 500 nm.” Ex. 1009 ¶ 27 (cited by Petitioner at Pet. 17). Ono
`
`further interlayer insulation film 23 comprises silicon oxide. Id. ¶ 23 (cited
`
`by Petitioner at Pet. 17). Petitioner identifies interlayer insulation film 23 as
`
`the second dielectric layer. Pet. 17–18. Dr. Rubloff testifies that Ono
`
`discloses that the interlayer insulating film is a silicon oxide film or a BPSG
`
`film, and that silicon oxide or BPSG is a dielectric material. Ex. 1002 ¶ 70.
`
`12
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`IPR2017-01417
`Patent 7,375,027 B2
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`Petitioner has sufficiently shown that Ono discloses the step of forming a
`
`second dielectric layer on the first dielectric layer.
`
`
`
`Claim 1 further recites: “providing a first aperture which extends
`
`from a surface of the second dielectric layer toward the surface of the
`
`substrate for a distance which is less than a combined thickness of the first
`
`and second dielectric layers.” Ex. 1001, 4:22–25. Ono’s Figure 1(b) is
`
`reproduced below:
`
`Figure 1(b) illustrates the process of Ono’s manufacturing method up to the
`
`step of forming contact holes stopping at the semiconductor coating layer.
`
`Ex. 1009 ¶ 49. Ono describes:
`
`
`
`Next, anisotropic etching is performed along the mask layer 24,
`forming contact holes CH which penetrate through the interlayer
`insulation film 23. At this stage, the semiconductor coating layer
`22 is used as an etching stopper layer and etching is terminated
`once the surface of the semiconductor coating layer 22 has been
`exposed.
`
`Id. ¶ 27 (emphasis added) (cited by Petitioner at Pet. 18). Dr. Rubloff
`
`explains that the underlying gate insulating film 21 is not etched at all
`
`because coating layer 22 covers insulating film 21 and etching is terminated
`
`at the surface of semiconductor coating layer 22. Ex. 1002 ¶ 72. This is
`
`supported by Ono’s disclosure. Ex. 1009 ¶ 27 (“[T]he semiconductor
`
`13
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`IPR2017-01417
`Patent 7,375,027 B2
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`coating layer 22 is used as an etching stopper layer and etching is terminated
`
`once the surface of the semiconductor coating layer 22 has been exposed.”).
`
`
`
`Petitioner explains that Ono discloses providing a contact hole (first
`
`aperture) in Figure 1(b) extending from a surface of the interlayer insulating
`
`film 23 (second dielectric layer) toward the surface of semiconductor
`
`substrate 10 for a distance which is less than a combined thickness of (1) the
`
`second dielectric layer, and (2) the semiconductor coating layer 22 and
`
`silicon oxide gate electrode coating insulation film 21 (collectively the “first
`
`dielectric layer”). Pet. 18 (citing Ex. 1009 ¶ 27). The explanation is
`
`supported by the above-quoted disclosure of Ono (Ex. 1009 ¶ 27), as well as
`
`by the testimony of Dr. Rubloff (Ex. 1002 ¶ 72). Petitioner has sufficiently
`
`shown that Ono discloses the step of “providing a first aperture which
`
`extends from a surface of the second dielectric layer toward the surface of
`
`the substrate for a distance which is less than a combined thickness of the
`
`first and second dielectric layers.”
`
`
`
`Claim 1 further recites: “providing a third dielectric layer covering a
`
`surface of the first aperture and an exposed surface of the first dielectric
`
`layer.” Ex. 1001, 4:27–29. Figure 1(c) of Ono is reproduced below:
`
`
`
`14
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`IPR2017-01417
`Patent 7,375,027 B2
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`Figure 1(c) of Ono illustrates the process of Ono’s manufacturing method up
`
`to the step of forming a contact hole coating layer. Ex. 1009 ¶ 49.
`
`
`
`Petitioner identifies layer 25 in Figure 1(c) as the third dielectric layer.
`
`Pet. 20. In that regard, Ono describes: “[T]he inside walls and bottom
`
`surfaces of the contact holes CH and the outside of the contact holes are
`
`coated, performing CVD of e.g., silicon nitride to approximately 40 nm to
`
`form a contact hole coating layer 25.” Id. ¶ 28 (cited by Petitioner at
`
`Pet. 20). Dr. Rubloff testifies that silicon nitride is a dielectric material. Ex.
`
`1002 ¶ 74.
`
`
`
`As is evident from Figure 1(c), the contact hole coating layer covers
`
`aperture CH and the exposed surface of the combined layers of
`
`semiconductor coating layer 22 and silicon oxide gate electrode coating
`
`insulation film 21. In light of this evidence, Petitioner has sufficiently
`
`shown that Ono discloses the step of “providing a third dielectric layer
`
`covering a surface of the first aperture and an exposed surface of the first
`
`dielectric layer.”
`
`
`
`Claim 1 further recites: “removing a portion of the third dielectric
`
`layer and a portion of the first dielectric layer to expose a portion of the
`
`surface of the substrate.” Ex. 1001, 4:30–32. Figure 2(d) of Ono is
`
`reproduced below:
`
`
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`15
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`IPR2017-01417
`Patent 7,375,027 B2
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`Figure 2(d) of Ono illustrates the process of Ono’s manufacturing method up
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`to the step of forming a contact hole through which the semiconductor
`
`substrate is exposed. Ex. 1009 ¶ 49.
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`
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`Ono describes:
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`Next, as shown in FIG. 2(d), anisotropic etching such as RIE
`(reactive ion etching) is performed to remove the contact hole
`coating layer 25, semiconductor coating layer 22 and gate
`electrode coating insulation film 21 corresponding to the bottom
`of contacts to expose the source/drain diffusion layer surface at
`the bottom of the contacts.
`
`Id. ¶ 29 (cited by Petitioner at Pet. 21–22). Dr. Rubloff testifies that the
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`anisotropic etching step illustrated in Ono’s Figure 2(d) satisfies the claimed
`
`step of “removing a portion of the third dielectric layer and a portion of the
`
`first dielectric layer to expose a portion of the surface of the substrate.”
`
`Ex. 1002 ¶¶ 75–76. On this record, we agree. Petitioner has sufficiently
`
`shown that Ono discloses the step of “removing a portion of the third
`
`dielectric layer and a portion of the first dielectric layer to expose a portion
`
`of the surface of the substrate.”
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`
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`For the foregoing reasons, Petitioner has shown a reasonable
`
`likelihood that it would prevail in establishing that Ono anticipates claim 1.
`
`3.
`
`Claims 2, 4, 6–8, and 10
`
`
`
`Claim 2 depends from claim 1 and further recites: “wherein forming a
`
`first dielectric layer on the surface comprises depositing a layer of silicon
`
`nitride on the surface.” Ex. 1001, 4:33–35. Ono discloses this added
`
`limitation because it states that silicon nitride is deposited by CVD to
`
`approximately 40 nm to form a semiconductor coating layer 22, leading to
`
`the state of Figure 1(a). Ex. 1009 ¶ 26 (cited by Petitioner at Pet. 24). Dr.
`
`Rubloff’s testimony supports this understanding and reading of Ono. Ex.
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`16
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`IPR2017-01417
`Patent 7,375,027 B2
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`1002 ¶ 79.
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`Petitioner argues that “nothing in the language of the claims or the
`
`specification of the ’027 patent requires the formation of layers ‘on the
`
`surface’ to be interpreted to mean formation ‘directly on the surface.’”
`
`Pet. 24. For purposes of this Decision, we agree with Petitioner and
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`determine that Ono’s chemical vapor deposition of layer 22 over film 21—
`
`which is on the surface of substrate 10—discloses “depositing a layer of
`
`silicon nitride on the surface.” On this record, we do not read the depositing
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`step so narrowly as to require that there be nothing else, e.g., another layer,
`
`between the silicon nitride and the surface of the semiconductor substrate.
`
`Direct contact between the silicon nitride layer and the surface of the
`
`substrate is not required. Thus, the fact that there is a silicon oxide gate
`
`electrode coating insulation film layer 21 beneath the silicon nitride layer
`
`and between the silicon nitride layer and the surface of the substrate does not
`
`undermine satisfaction of the step required by claim 2. Accordingly,
`
`Petitioner has shown a reasonable likelihood that it would prevail in
`
`establishing that Ono anticipates claim 2.
`
`
`
`Claim 4 depends from claim 2 and further recites: “wherein
`
`depositing a layer of silicon nitride comprises depositing the layer of silicon
`
`nitride using a chemical vapor deposition process.” Ex. 1001, 4:39–41. As
`
`discussed above in the context of claim 2, Ono discloses depositing a layer
`
`of silicon nitride on the surface of the semiconductor substrate. Dr. Rubloff
`
`testifies that a person of ordinary skill in the art would have readily
`
`understood that “CVD” as used by Ono means chemical vapor deposition.
`
`Ex. 1002 ¶ 83. Petitioner has shown a reasonable likelihood that it would
`
`prevail in establishing that Ono anticipates claim 4.
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`IPR2017-01417
`Patent 7,375,027 B2
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`
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`Claim 6 depends from claim 1 and further recites: “wherein removing
`
`a portion of the third dielectric layer and the first dielectric layer to expose a
`
`portion of the surface of the material comprises performing an anisotropic
`
`etch process.” Ex. 1001, 4:47–50. We recognize, as Petitioner has pointed
`
`out (Pet. 27 n.7), that the term “the material” has no antecedent basis either
`
`within claim 6 itself or within base claim 1. However, because the term
`
`refers to material to be exposed by removal of the first dielectric layer, we
`
`understand the term as specifically identifying the surface of the substrate.
`
`A different interpretation would be unreasonable.
`
`
`
`As cited by Petitioner (Pet. 27), Ono describes: “[A]s shown in FIG.
`
`2(d), anisotropic etching such as RIE (reactive ion etching) is performed to
`
`remove the contact hole coating layer 25, semiconductor coating layer 22
`
`and gate electrode coating insulation film 21 corresponding to the bottom of
`
`contacts to expose the source/drain diffusion layer surface at the bottom of
`
`the contacts.” Ex. 1009 ¶ 29 (emphasis added). Petitioner has shown a
`
`reasonable likelihood that it would prevail in establishing that Ono
`
`anticipates claim 6.
`
`
`
`Claim 7 depends from claim 1 and further recites: “wherein forming a
`
`second dielectric layer on the first dielectric layer comprises forming a layer
`
`of silicon dioxide on the first dielectric layer. Ex. 1001, 4:51–53. As
`
`discussed above, Petitioner identifies Ono’s interlayer insulating film 23 as
`
`the second dielectric layer. Ono describes interlayer insulating film 23 as
`
`comprising silicon oxide. Ex. 1009 ¶ 23. Also as cited by Petitioner
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`(Pet. 28), Ono also describes interlayer insulation film 23 as being formed
`
`by depositing BPSG to about 500 nm. Id. ¶ 27.
`
`
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`Dr. Rubloff testifies that a person of ordinary skill in the art would
`
`have understood that silicon oxide is not stoichiometrically balanced and
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`18
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`IPR2017-01417
`Patent 7,375,027 B2
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`that, in the context of semiconductor fabrication techniques, the term
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`“silicon oxide” is used to refer to “silicon dioxide” which is
`
`stoichiometrically balanced. Ex. 1009 ¶ 86. Additionally, Dr. Rubloff
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`testifies:
`
`In my opinion, a person of ordinary skill in the art would have
`understood that Ono’s disclosure that the interlayer insulation
`film 23 being formed by depositing BPSG (Id. ¶ [0027])
`discloses that the interlayer insulation film 23 is made of silicon
`dioxide. In particular, a person of ordinary skill in the art would
`have known that BPSG includes silicon dioxide because BPSG
`is a material including silicon dioxide doped with boron (B) and
`phosphorous (P). (Ex. 1010 (Vaartstra) at ¶¶ [0002], [0020], Ex.
`1011 (Li) at ¶ [0050].)
`
`Ex. 1002 ¶ 86 (footnote omitted).
`
`
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`Based on the above-noted testimony of Dr. Rubloff, Petitioner has
`
`shown a reasonable likelihood that it would prevail in establishing that Ono
`
`anticipates claim 7.
`
`
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`Claim 8 depends from claim 1 and further recites: “wherein providing
`
`the first aperture comprises performing an etch process.” Ex. 1001, 4:54–55.
`
`This step is disclosed by Ono. Ono describes that an anisotropic etching
`
`step is performed to form contact holes which penetrate through interlayer
`
`insulation film 23. Ex. 1009 ¶ 27 (cited by Petitioner at Pet. 29). Ono also
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`describes that etching is terminated once the surface of the semiconductor
`
`coating layer 22 has been exposed. Id. Petitioner has shown a reasonable
`
`likelihood that it would prevail in establishing that Ono anticipates claim 8.
`
`
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`Claim 10 depends from claim 1 and further recites: “wherein
`
`removing a portion of the third dielectric layer and the first dielectric layer
`
`comprises performing a reactive ion etch.” Ex. 1001, 4:59–61. Ono’s
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`manufacturing method satisfies this requirement. Specifically, as cited by
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`19
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`IPR2017-01417
`Patent 7,375,027 B2
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`Petitioner (Pet. 30), Ono identifies reactive ion etching as an example of the
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`anisotropic etching step used to remove the contact hole coating layer 25
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`(third dielectric layer), and the semiconductor coating layer 22 and gate
`
`electrode coating insulating film 21 (together forming the first dielectric
`
`layer) to expose the source/drain diffusion layer surface at the bottom of the
`
`contact holes. Ex. 1009 ¶ 29. Petitioner has shown a reasonable likelihood
`
`that it would prevail in establishing that Ono anticipates claim 10.
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`C. Alleged Obviousness of Claims 3 and 5 over Ono and Ngo
`
`1.
`
`Ngo
`
`
`
`Ngo is directed to a semiconductor device manufacturing process.
`
`Ex. 1012, 1:14–15. Specifically, the method includes the formation of a stop
`
`layer on the semiconductor substrate and a subsequent formation of an
`
`overlying dielectric layer. Id. at 2:54–62. Thereafter, a step is performed
`
`that forms a conductive path that extends through the two layers to the
`
`device. Id. at 3:1–4.
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`2.
`
`Claim 3
`
`
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`Claim 3 depends from claim 1 and further recites: “wherein forming a
`
`first dielectric layer on the surface comprises depositing a layer of silicon
`
`oxynitride on the surface.” Ex. 1001, 4:36–38. Ono by itself does not meet
`
`this limitation, because in Ono the first dielectric layer, as discussed above,
`
`includes silicon oxide gate electrode coating insulation film 21 and silicon
`
`nitride semiconductor coating layer 22. Pet. 11. Dr. Rubloff testifies,
`
`however, that “[a] person of ordinary skill in the art would have been
`
`motivated to modify Ono such that the semiconductor coating layer 22 is a
`
`silicon oxynitride film based on the teachings of Ngo.” Ex. 1002 ¶ 93. Ngo
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`20
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`IPR2017-01417
`Patent 7,375,027 B2
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`describes depositing stop layer 22', “for example silicon oxynitride” on a
`
`semiconductor substrate. Ex. 1012, 6:12–15.
`
`
`
`With regard to that motivation, Dr. Rubloff testifies:
`
`Ngo’s stop layer 22' has a function
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