Trials@uspto.gov
`Tel: 571-272-7822
`
`
`Paper 33
`Entered: November 27, 2018
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`
`v.
`
`PROMOS TECHNOLOGIES, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-01418
`Patent 6,559,044 B1
`____________
`
`
`Before JAMESON LEE, KEVIN F. TURNER, and
`JOHN A. HUDALLA, Administrative Patent Judges.
`
`LEE, Administrative Patent Judge.
`
`
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a)
`
`
`
`
`
`

`

`IPR2017-01418
`Patent 6,559,044 B1
`
`INTRODUCTION
`I.
`A. Background and Summary
`Petitioner1 filed a Petition (Paper 1, “Pet.”) to institute inter partes
`review of claims 1–23 of U.S. Patent No. 6,559,044 B1 (Ex. 1001, “the
`’044 patent”). We instituted review of claims 1–23 on all grounds asserted
`in the Petition. Paper 7 (“Decision on Institution”). Patent Owner2 filed a
`Patent Owner Response.3 Paper 13 (“PO Resp.”). Petitioner filed a Reply. 4
`Paper 19. An oral hearing was held on August 16, 2018. A copy of the
`transcript for the oral hearing has been entered as Paper 32.
`Petitioner has shown, by a preponderance of the evidence, that each of
`claims 1–4, 6, 8–14, 16–18, and 20–22 is unpatentable. Petitioner has not,
`however, shown that any of claims 5, 7, 15, 19, and 23 is unpatentable.
`
`B. Related Matters
`Both Petitioner and Patent Owner have identified the following action
`as involving the ’044 patent: ProMOS Technologies, Inc. v. Samsung
`
`
`1 Samsung Electronics Co., Ltd.
`2 ProMOS Technologies, Inc.
`3 Patent Owner has not submitted objective evidence of nonobviousness, i.e.,
`secondary considerations, for consideration. Patent Owner submitted the
`declaration of Mr. Dhaval Brahmbhatt in support of the Patent Owner
`Response. Ex. 2004.
`4 Patent Owner filed a paper styled as a “Motion to Exclude” (Paper 24), but
`the substance of the paper is actually a motion to strike. By way of
`explanation, a motion to exclude must be based on admissibility issues under
`the Federal Rules of Evidence, but Patent Owner’s motion is not of that type.
`We informed the parties that Patent Owner’s motion will be treated as a
`Motion to Strike. Paper 28. Petitioner filed an Opposition. Paper 29. The
`Motion to Strike is addressed in Section II.L. below.
`
`
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`IPR2017-01418
`Patent 6,559,044 B1
`Electronics Co., Ltd., No. 1:16-cv-00335-SLR (D. Del.). Pet. 1; Paper 4. In
`that action, Patent Owner also asserted other patents against Petitioner.
`Pet. 1. Petitioner has filed inter partes review petitions against those other
`patents in IPR2017-01412, IPR2017-01413, IPR2017-01414,
`IPR2017-01415, IPR2017-01416, IPR2017-01417, and IPR2017-01419.
`Paper 4.
`Petitioner also identifies these inter partes review proceedings,
`initiated by petitions filed by Petitioner, as involving additional patents
`asserted by Patent Owner against Petitioner in ProMOS Technologies, Inc. v.
`Samsung Electronics Co., Ltd., No. 1:15-cv-00898-SLR-SRF (D. Del.):
`IPR2017-00032, IPR2017-00033, IPR2017-00035, IPR2017-00036,
`IPR2017-00037, IPR2017-00038, IPR2017-00039, and IPR2017-00040.
`Pet. 1–2.
`The ’044 Patent
`C.
`
`The ’044 patent pertains generally to a method for manufacturing a
`semiconductor device and particularly to a method for forming contacts in
`such a device. Ex. 1001, 1:7–9. The ’044 patent describes that in a
`conventional process, (1) a plurality of active devices, such as transistors and
`memory cells, are formed over a semiconductor substrate, (2) one or more
`metal layers are formed over the active devices, and (3) contacts, through
`vias, serve to electrically connect certain active regions of the active devices
`to one of the metal layers. Id. at 1:19–25. With that background, the
`’044 patent states that it is desirable to reduce the number of required
`processing steps associated with forming an integrated circuit. Id. at 1:32–
`34. The ’044 patent disclosure, however, does not articulate how the
`disclosed invention, relative to the prior art methods of manufacturing a
`
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`IPR2017-01418
`Patent 6,559,044 B1
`semiconductor device, reduces the number of required processing steps
`associated with forming an integrated circuit.
`
`The ’044 patent summarizes its invention as follows:
`
`In accordance with the invention, there is provided a
`method for manufacturing a semiconductor device that includes
`providing at least two active devices over a substrate, each of the
`active devices includes a gate electrode provided over a gate
`oxide, a silicide formed over the gate electrode, a cap formed
`over the silicide, and a pair of spaced-apart diffused regions
`formed in the substrate. The method also includes depositing a
`first layer of dielectric material over the substrate and active
`devices, providing a first photoresist over the first layer of
`dielectric material, defining and patterning the first photoresist,
`etching the first layer of dielectric material unmasked by the first
`photoresist to form a first opening, wherein the first opening
`exposes a first silicide of a first active device, removing the first
`photoresist, depositing a second layer of dielectric material over
`the first layer of dielectric material and in the first opening,
`providing a mask over the second layer of dielectric material,
`providing a second photoresist over the mask, defining and
`patterning the second photoresist, and forming a second opening
`and a third opening, wherein the second opening is aligned with
`the first opening and exposes the first silicide of the first active
`device, and the third opening exposes one of the pair of the
`spaced-apart diffused regions of a second active device.
`
`Also in accordance with the present invention, there is
`provided a method for forming contacts in a semiconductor
`device including a plurality of active devices over [ ] a substrate
`that includes depositing a first layer of dielectric material over
`the substrate and plurality of active devices, forming a first
`opening in the first layer of dielectric material, depositing a
`second layer of dielectric material over the first layer of dielectric
`material and in the first opening, providing a mask over the
`second layer of dielectric material, wherein the mask material is
`distinguishable over silicon oxides, and forming a second
`opening and a third opening in the second layer of dielectric
`material, wherein the second opening is aligned with the first
`opening and exposes a first silicide of a first active device, and
`
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`IPR2017-01418
`Patent 6,559,044 B1
`the third opening exposes one of diffused regions of a second
`active device.
`Id. at 1:40–2:12.
`
`Figure 1D of the ’044 patent is reproduced below:
`
`
`Figure 1D illustrates a cross-sectional view of the semiconductor structure at
`a point in the fabrication process after the formation of the second and third
`openings. Id. at 2:41–43, 3:66–4:6. The ’044 patent states the following
`regarding Figure 1D:
`
`Referring to FIG. 1D, with hardmask 34 in place, an
`etching step is performed to form vertical openings 38 and 40.
`Vertical opening 38, aligned with vertical opening 30 shown in
`FIG. 1C, exposes silicide 18, and will later become a contact for
`gate electrode 16. Vertical opening 40 extends through to
`substrate 10, exposing diffused region 22-2, and will later
`become a contact for one of the source and drain regions of active
`device 12-2. In one embodiment, the etching step is a
`self-aligned contact step that forms vertical openings for gate and
`source/drain contacts of an active device at the same time. In
`addition, etchants for the etching step may be one of C5F8 or
`C4F8. Conventional semiconductor processes follow to fill
`vertical openings 38 and 40 with conductive materials to
`complete formation of contacts.
`Id. at 3:66–4:12.
`
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`IPR2017-01418
`Patent 6,559,044 B1
`Of the challenged claims, claims 1 and 16 are the only
`independent claims. Claims 1 and 16 are reproduced below:
`
`1.
`A method for manufacturing a semiconductor
`device, comprising:
`providing at least two active devices over a substrate, each of
`the active devices includes a gate electrode provided over a
`gate oxide, a silicide formed over the gate electrode, a cap
`formed over the silicide, and a pair of spaced-apart diffused
`regions formed in the substrate;
`depositing a first layer of dielectric material over the substrate
`and active devices;
`providing a first photoresist over the first layer of dielectric
`material;
`defining and patterning the first photoresist;
`etching the first layer of dielectric material unmasked by the
`first photoresist to form a first opening, wherein the first
`opening exposes a first silicide of a first active device;
`removing the first photoresist;
`depositing a second layer of dielectric material over the first
`layer of dielectric material and in the first opening;
`providing a mask over the second layer of dielectric material;
`providing a second photoresist over the mask;
`defining and patterning the second photoresist; and
`forming a second opening and a third opening, wherein the
`second opening is aligned with the first opening and
`exposes the first silicide of the first active device, and the
`third opening exposes one of the pairs of the spaced-apart
`diffused regions of a second active device.
`Ex. 1001, 4:20–49.
`
`16. A method for forming contacts in a semiconductor
`device including a plurality of active devices formed over a
`substrate, comprising:
`depositing a first layer of dielectric material over the substrate
`and plurality of active devices;
`
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`IPR2017-01418
`Patent 6,559,044 B1
`forming a first opening in the first layer of dielectric material;
`depositing a second layer of dielectric material over the first
`layer of dielectric material and in the first opening;
`providing a mask over the second layer of dielectric material,
`wherein the mask material is distinguishable over silicon
`oxides; and
`forming a second opening and a third opening in the second
`layer of dielectric material, wherein the second opening is
`aligned with the first opening and exposes a first silicide of
`a first active device, and the third opening exposes one of
`diffused regions of a second active device.
`Id. at 5:24–6:7.
`Evidence Relied Upon by Petitioner
`D.
`Petitioner relies on the following references5:
`
`
`
`Ho
`
`Reference
`U.S. Pat. No. 6,620,733 B2
`
`Fujimoto U.S. Pat. No. 6,399,470 B1
`
`Date
`Sept. 16, 2003,
`filed Feb. 12, 2001
`June 4, 2002,
`filed Feb. 13, 2001
`Dec. 26, 2000
`Dec. 5, 2000
`July 18, 2000
`April 28, 1992
`
`Exhibit
`Ex. 1007
`
`Ex. 1005
`
`U.S. Pat. No. 6,165,880
`Yaung
`U.S. Pat. No. 6,156,637
`Sonego
`Ohkawa U.S. Pat. No. 6,091,154
`Paterson U.S. Pat. No. 5,108,941
`
`Petitioner also relies on the Declarations of Gary Rubloff, Ph.D.
`(Exs. 1002, 1029).
`The Asserted Grounds
`E.
`Petitioner asserts the following grounds of unpatentability (Pet. 3–4):
`
`Ex. 1006
`Ex. 1013
`Ex. 1025
`Ex. 1008
`
`
`5 The ’044 patent was filed on September 10, 2002 and does not claim
`priority to any earlier application. Ex. 1001, [22].
`
`7
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`IPR2017-01418
`Patent 6,559,044 B1
`Claim(s) Challenged
`1–4, 6–8, and 12–14
`5
`9–11
`16, 19, and 22
`17, 18, and 20
`21
`15
`23
`
`
`
`Basis
`§ 103(a)
`§ 103(a)
`§ 103(a)
`§ 103(a)
`§ 103(a)
`§ 103(a)
`§ 103(a)
`§ 103(a)
`
`References
`Fujimoto, Yaung, and Ho
`Fujimoto, Yaung, Ho, and Paterson
`Fujimoto, Yaung, Ho, and Sonego
`Fujimoto and Ho
`Fujimoto, Ho, and Yaung
`Fujimoto, Ho, and Sonego
`Fujimoto, Yaung, Ho, and Ohkawa
`Fujimoto, Ho, and Ohkawa
`
`A.
`
`II. ANALYSIS
`The Law on Obviousness
`The question of obviousness is resolved on the basis of underlying
`factual determinations including (1) the scope and content of the prior art;
`(2) any differences between the claimed subject matter and the prior art;
`(3) the level of ordinary skill in the art; and (4) objective evidence of
`nonobviousness. Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
`Prior art references must be “considered together with the knowledge of one
`of ordinary skill in the pertinent art.” In re Paulsen, 30 F.3d 1475, 1480
`(Fed. Cir. 1994) (citation omitted). Also, “it is proper to take into account
`not only specific teachings of the reference but also the inferences which one
`skilled in the art would reasonably be expected to draw therefrom.” In re
`Preda, 401 F.2d 825, 826 (CCPA 1968). One seeking to establish
`obviousness based on more than one reference also must articulate sufficient
`reasoning with rational underpinning to combine teachings. See KSR Int’l
`Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007).
`
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`IPR2017-01418
`Patent 6,559,044 B1
`Level of Ordinary Skill in the Art
`B.
`Petitioner proposes that a person of ordinary skill in the art at the time
`of the alleged invention of the ’044 patent “would have had a master’s
`degree or higher in a field relating to semiconductor manufacturing
`processes, such as material science, physics, electrical engineering, or other
`related subjects, and three to four years of experience in the design and
`fabrication of semiconductor devices. (Ex. 1002, ¶¶ 19-20.)” Pet. 5.
`Petitioner also states that “[m]ore education can supplement practical
`experience and vice versa.” Id. Patent Owner’s declarant, Mr. Brahmbhatt,
`testifies that one of ordinary skill in the art at the time of the invention “is a
`person with a Bachelor’s of Science degree in material science, physics,
`electrical engineering, or chemical engineering and three to four years of
`practical experience in the development, design, processing, and
`manufacturing/testing of semiconductor chips and technology.” Ex. 2004
`¶ 33.
`
`We find Petitioner’s proposal vague insofar as it includes the qualifier
`“or higher” to describe the level of education. The qualifier results in a
`range that is too broad to provide a meaningful indication of what
`knowledge and skills would have been possessed by one with ordinary skill
`in the art. Also, by definition, the level of ordinary skill is less than that of
`an expert. A “master’s degree or higher” is an advanced degree. Without
`Petitioner explaining why the level of “ordinary skill” is reflected by an
`advanced degree, we are not persuaded by Petitioner’s articulation of the
`level of ordinary skill.
`For the foregoing reasons, we credit the testimony of Mr. Brahmbhatt
`and find the level of ordinary skill is reflected by a bachelor of science
`degree in material science, physics, electrical engineering, or chemical
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`Patent 6,559,044 B1
`engineering, and three to four years of practical experience in the
`development, design, processing, and manufacturing/testing of
`semiconductor chips and technology.
`C. Claim Construction
`In an inter partes review, claim terms in an unexpired patent are
`interpreted according to their broadest reasonable construction in light of the
`specification of the patent in which they appear. 37 C.F.R. § 42.100(b)
`(2016); Cuozzo Speed Techs., LLC v. Lee, 136 S. Ct. 2131, 2142–46 (2016).
`Consistent with that standard, claim terms are generally given their ordinary
`and customary meaning, as would have been understood by one of ordinary
`skill in the art in the context of the entire disclosure. See In re Translogic
`Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007). There are, however, two
`exceptions to that rule: “1) when a patentee sets out a definition and acts as
`his own lexicographer,” and “2) when the patentee disavows the full scope
`of a claim term either in the specification or during prosecution.” Thorner v.
`Sony Comp. Entm’t Am. LLC, 669 F.3d 1362, 1365 (Fed. Cir. 2012).
`Only terms that are in controversy need to be construed, and only to
`the extent necessary to resolve the controversy. See Wellman, Inc. v.
`Eastman Chem. Co., 642 F.3d 1355, 1361 (Fed. Cir. 2011); Vivid Techs.,
`Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
`Petitioner has not proposed an express construction for any claim
`term. In the Decision on Institution, we determined that there was no need
`to construe expressly any term, but also stated that the claim term “mask” is
`generic and not limited to a hardmask, noting that the specification of the
`’044 patent identifies three different types of masks, a hardmask, a
`photoresist mask, and a reticle mask. Paper 7, 10, 24. In the Patent Owner
`Response, Patent Owner argues that “mask” must be construed as only
`
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`IPR2017-01418
`Patent 6,559,044 B1
`covering a hardmask, because all claims require a photoresist over the mask
`and no person of ordinary skill would form a photoresist on top of a
`photoresist, and because in the field of semiconductor processing, there are
`only two types of masks, a hardmask or a photoresist. PO Resp. 24–25. We
`need not resolve the issue of whether the claimed “mask” is limited to a
`hardmask, because the grounds of unpatentability as presented by Petitioner
`all rely on a hardmask to meet the claimed “mask.” Thus, it remains the
`case that no term requires an express construction.
`D. Alleged Unpatentability of Claims 1–4, 6–8,
`and 12–14 as Obvious over Fujimoto, Yaung, and Ho
`Fujimoto
`1.
`Fujimoto relates to a method for manufacturing a semiconductor
`device, and more particularly to a method for forming contact holes for
`conductive strips passing through an insulating film, such as an interlayer
`insulating film. Ex. 1005, 1:9–13. Fujimoto explains that in conventional
`semiconductor devices, it is often required to provide two contact holes:
`(1) a contact hole that opens to the surface of the semiconductor substrate,
`and (2) another contact hole that opens to a conductor, such as a gate
`electrode under a protective film. Id. at 1:49–54. In that regard, Fujimoto
`further explains:
`
`In the former [(1)], the contact hole can be formed by a
`single etching process in a specified position of the insulating
`film. In the latter [(2)], however, after the insulating film has
`been etched, the exposed protective film needs to be etched.
`Because the protective film has a different etching-resistant
`characteristic from that of the insulating film, their etching
`conditions differ to a large extent in the forming process of the
`two contact holes.
`
`For this reason, in the conventional manufacturing
`method, it is necessary to separately carry out an etching process
`
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`IPR2017-01418
`Patent 6,559,044 B1
`using a mask for the contact hole that opens to the surface of the
`semiconductor substrate, and an etching process using a mask for
`the contact hole that opens to the conductive line under the
`protective film.
`Id. at 1:55–2:1. According to the method of Fujimoto, “the protective film
`above the conductor, where the second contact hole is to be formed, is
`removed in advance, when the etched-away opening is formed to expose the
`top portion of the corresponding conductor from the surface of the insulating
`film, and the etched-away opening is refilled.” Id. at 2:41–45. Fujimoto
`summarizes as follows:
`Therefore, according to the above-mentioned method of
`the present invention, a final etching process to form the first and
`second contact holes after refilling of the etched-away opening
`can be carried out substantially under the same condition, and
`therefore both contact holes can be formed collectively by an
`etching process using a single etching mask having arranged
`therein two opening patterns for the first and second contact
`holes.
`Id. at 2:58–65.
`Yaung
`2.
`Yaung is directed to a method for making contacts in semiconductor
`transistors. Ex. 1006, 1:8–27, 2:31–37, 4:16–20. Yaung discloses a field
`effect transistor that includes gate oxide 12 formed under polysilicon
`layer 14. Id. at 4:47–54.
`Ho
`3.
`Ho is directed to a method for etching features in an integrated circuit
`wafer that incorporates at least one dielectric layer. Ex. 1007, Abstr. The
`wafer comprises a dielectric layer placed over a substrate. Id. at 7:17–18. A
`hardmask layer is placed over the dielectric layer, and a bottom
`antireflective coating (BARC) is placed over the hardmask layer. Id. at
`
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`IPR2017-01418
`Patent 6,559,044 B1
`7:20–22. A photoresist mask is placed over the hardmask layer. Id. at 7:22–
`23.
`
`4.
`
`Claim 1
`
`a.
`Claim 1 recites: “A method for manufacturing a semiconductor
`device.” Ex. 1001, 4:20–21. As is noted by Petitioner (Pet. 8), Fujimoto
`discloses such a method. Ex. 1005, 1:9–13; 2:10–3:9 (cited at Pet. 8).
`Petitioner’s assertion also is supported by the testimony of Dr. Rubloff.
`Ex. 1002 ¶¶ 53–55. We find that Fujimoto discloses a method for
`manufacturing a semiconductor device.
`b.
`Claim 1 further recites: “providing at least two active devices over a
`
`substrate, each of the active devices includes a gate electrode provided over
`a gate oxide, a silicide formed over the gate electrode, a cap formed over the
`silicide, and a pair of spaced-apart diffused regions formed in the substrate.”
`Ex. 1001, 4:22–26. Petitioner asserts that Fujimoto either alone or in
`combination with Yaung disclose this limitation. Pet. 8. For reasons
`discussed below, we find that Fujimoto alone and alternatively, Fujimoto in
`combination with Yaung, teach this limitation.
`
`Fujimoto’s Figure 1(a), cited by Petitioner at page 10 of the Petition,
`is reproduced below:
`
`
`
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`Patent 6,559,044 B1
`Figure 1(a) illustrates an intermediate structure in the execution of a
`semiconductor device manufacturing method according to Fujimoto.
`Ex. 1005, 3:13–15. With regard to Figure 1(a), Fujimoto states that a
`plurality of gate electrodes 11 for MOS (metal-oxide-semiconductor)
`transistors are formed in parallel and mutually spaced apart in an active
`region of a silicon semiconductor substrate 10. Id. at 3:37–40. Petitioner
`asserts that Fujimoto’s stacked layer structure “includes a polysilicon
`layer 12, tungsten silicide layer 13, and protective film 14 (made of silicon
`nitride) in that order.” Pet. 10–11 (citing Ex. 1005, 3:41–54, Fig. 1(a);
`Ex. 1002 ¶ 60). The assertion is supported by the cited evidence including
`the testimony of Dr. Rubloff. Ex. 1002 ¶ 60.
`
`Petitioner identifies Fujimoto’s polysilicon layer 12 as the recited
`“gate electrode provided over a gate oxide.” Pet. 10. Petitioner explains
`that although Fujimoto itself identifies the entire stack structure, including
`polysilicon layer 12, tungsten silicide paler 13, and protective film 14,
`collectively, as forming “gate electrode 11,” one with ordinary skill in the art
`would have readily understood that polysilicon layer 12, on its own, is a gate
`electrode in the context of the ’044 patent. Pet. 10. That assertion is
`supported by the testimony of Dr. Rubloff. Ex. 1002 ¶ 59. Dr. Rubloff
`points out that the stacked structure of the ’044 patent, including gate
`electrode 16, silicide 18 over the gate electrode, and cap 20-2 over
`silicide 18, and the stacked structure of Fujimoto, including polysilicon
`layer 12, tungsten silicide layer 13 over polysilicon layer 12, and protective
`film 14 over the tungsten silicide layer 13, are the same. Id. ¶ 60.
`
`With regard to identifying Fujimoto’s polysilicon layer 12 as the gate
`electrode provided over a gate oxide, Petitioner explains: “Although the
`figures of Fujimoto do not explicitly disclose that its polysilicon layer 12
`
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`(‘gate electrode’) is provided over a gate oxide, a [person of ordinary skill in
`the art] would have understood based on Fujimoto’s disclosure that it
`necessarily discloses a gate oxide film underneath the polysilicon layer 12.”
`Pet. 11. The assertion is supported by the testimony of Dr. Rubloff, who
`explains:
`Fujimoto discloses “removing unwanted portions of the stacked
`structure and the gate oxide film by selective etching with the
`protective film [14] used as the etching mask” after forming the
`gate electrodes 11 having the stacked structure (i.e., polysilicon
`layer 12, tungsten silicide layer 13, and protective film 14).
`(Ex. 1005 at 3:46–54 (emphasis added).) A person having
`ordinary skill in the art would have understood that “a gate oxide
`film” is an oxide layer underneath a “gate” that separates the gate
`electrode from the substrate, which was a typical configuration
`in semiconductor devices known to such a person prior to the
`alleged invention.
`Ex. 1002 ¶ 61 (citing Pet. 11). Dr. Rubloff further explains:
`Given that Fujimoto discloses that its figure 1 embodiment is
`directed to “MOS [metal oxide semiconductor] transistors”
`(Ex. 1005 at 3:37–40 (emphasis added)), a person having
`ordinary skill in the art would have known that the “gate oxide
`film” disclosed in Fujimoto would necessarily be included
`underneath the polysilicon layer 12 (“gate electrode”). This is
`because the structure of a MOS transistor (e.g., a MOS field
`effect transistor (MOSFET)) resembles a capacitor, and a
`dielectric film (e.g., gate oxide film) would necessarily be
`provided under the polysilicon layer for the MOSFET to perform
`its intended function. (Ex. 1002 at 112–113.)
`Id. We credit the above-quoted testimony of Dr. Rubloff, and find it to be
`persuasive. Accordingly, for all of the reasons as discussed above, we find
`that Fujimoto’s polysilicon layer 12 is “a gate electrode provided over a gate
`oxide,” as recited in claim 1.
`
`In the alternative, Petitioner asserts that in light of the combined
`teachings of Fujimoto and Yaung, it would have been obvious to one with
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`ordinary skill in the art “to form a gate oxide film underneath the polysilicon
`layer 12.” Pet. 12. The assertion is persuasive, as explained below.
`
`Yaung is directed to a method for making contacts in semiconductor
`transistors. Ex. 1006, 1:8–27, 2:31–37, 4:16–20 (cited at Pet. 12). Yaung
`discloses a field effect transistor that includes gate oxide 12 formed under
`polysilicon layer 14. Id. at 4:47–54 (cited at Pet. 12). Thus, Petitioner
`correctly asserts that Yaung discloses forming a polysilicon layer over gate
`oxide for a field effect transistor. Pet. 12. Petitioner further asserts that in
`light of Fujimoto’s own disclosure regarding a “gate oxide film” in its
`MOSFET, and Yaung’s disclosure of forming gate oxide underneath a
`polysilicon layer, it would have been obvious to one with ordinary skill in
`the art to modify Fujimoto’s manufacturing process to form a MOSFET
`device such that its polysilicon layer is formed over a gate oxide film. Pet.
`13. The assertion is supported by the testimony of Dr. Rubloff. Ex. 1002 ¶
`63. Specifically, Dr. Rubloff testifies:
`A person having ordinary skill in the art would have been
`motivated to modify Fujimoto’s process in this way to ensure
`proper operation of the manufactured device. For example, as I
`discussed above, a person having ordinary skill in the art would
`have understood that a MOSFET functions like a capacitor, and
`a dielectric film (e.g., gate oxide film) would be needed under
`the polysilicon layer for the MOSFET to perform its intended
`function. (Ex. 1020 at 112–113.) Therefore, in my opinion, a
`skilled person would have recognized that the combined
`Fujimoto-Yaung method would have involved the combination
`of known elements (e.g., a gate oxide similar to the one disclosed
`by Yaung underneath the polysilicon layer 12 of Fujimoto) using
`a known technique (e.g., “gate oxide is typically formed by
`thermal oxidation” before forming
`the polysilicon
`layer
`(Ex. 1006 at 4:47–54)) that would have yielded the expected
`result of fabricating an operational MOSFET device. Given the
`disclosures of Fujimoto and Yaung, and the knowledge of one
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`skilled in the art, a person having ordinary skill in the art would
`have found using such techniques, as I discussed above, a
`predictable implementation at the time of the alleged invention
`of the ’044 patent. Additionally, a person having ordinary skill
`in the art would have known and had the capability to implement
`the above modifications in such a way to ensure the process of
`manufacturing the semiconductor device disclosed by Fujimoto
`would be workable, as well as the resulting device being formed.
`Ex. 1002 ¶ 63. We credit the above-quoted testimony of Dr. Rubloff because
`it is consistent with and supported by the cited evidence of record.
`
`Petitioner identifies Fujimoto’s tungsten silicide layer 13 as satisfying
`the recited “silicide formed over the gate electrode” of claim 1. Pet. 14.
`According to Petitioner, silicide is formed in Fujimoto after formation of the
`polysilicon layer, so one with ordinary skill in the art would have understood
`that the tungsten silicide layer 13 is formed over polysilicon layer 12.
`Pet. 14–15. The assertion is supported by the testimony of Dr. Rubloff.
`Ex. 1002 ¶ 64. The relative positions of the layers also are illustrated in
`Figure 1(a) of Fujimoto reproduced above (cited at Pet. 15–16). For these
`reasons, we find that Fujimoto discloses the claimed silicide of claim 1.
`
`Petitioner identifies Fujimoto’s protective film 14 as satisfying the
`recited “cap formed over the silicide” of claim 1. Pet. 15. Petitioner cites to
`column 3, lines 46–51, of Fujimoto, which describes that stack structures 11
`are provided by depositing polysilicon and silicide, in that order, and then
`forming protective film 14 of silicon nitride on the stack structures. Id. That
`reading of Fujimoto is supported by the testimony of Dr. Rubloff. Ex. 1002
`¶ 65. For these reasons, we find that Fujimoto discloses the claimed cap
`over the silicide.
`
`With regard to claim 1’s recited “pair of spaced-apart diffused regions
`formed in the substrate,” Petitioner asserts: “Although Fujimoto’s figures do
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`not include a depiction of the source and drain regions, Fujimoto discloses
`this feature by noting that source and drain regions are formed spaced apart
`in the substrate 10.” Pet. 16 (citing Ex. 1005, 3:55–59). Fujimoto states:
`“Though not illustrated, by using the gate electrodes 11 each having a
`protective film 14 at the top portion as a mask, impurity atoms to form the
`source and drain regions are injected into the substrate 10 on either side of
`the gate electrodes 11 by ion implantation, for example.” Ex. 1005, 3:55–
`59. Petitioner’s assertion is supported by the testimony of Dr. Rubloff.
`Ex. 1002 ¶ 66 (cited at Pet. 16–17). Dr. Rubloff presents an annotated
`version of Fujimoto’s Figure 1(a), reproduced below:
`
`
`Id. The annotated version of Fujimoto’s Figure 1(a) shows active devices in
`red circles and marks in green the general location of the source and drain
`regions in the substrate, within an intermediate structure in the execution of
`a semiconductor device manufacturing method according to Fujimoto. Id.
`
`Dr. Rubloff testifies that Fujimoto’s source and drain regions are
`spaced-apart because they are formed on either side of gate electrodes 11 in
`the substrate. Id. Dr. Rubloff further testifies that a person having ordinary
`skill in the art would have known that the source and drain regions in
`Fujimoto are diffused regions. Id. ¶ 67. For these reasons, we find that
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`Fujimoto discloses the claimed “pair of spaced-apart diffused regions
`formed in the substrate.”
`
`c.
`Claim 1 further recites: “depositing a first layer of dielectric material
`
`over the substrate and active devices.” Ex. 1001, 4:27–28. Petitioner
`identifies Fujimoto’s interlayer insulating film 15 as the recited first
`dielectric layer of claim 1, as shown in Petitioner’s annotated version of
`Fujimoto’s Figure 1(c), reproduced below (Pet. 18–19):
`
`
`The annotated version of Fujimoto’s Figure 1(c) shows a cross-sectional
`view of an intermediate structure undergoing the fabrication process of
`Fujimoto, and shows the deposition of interlayer insulating film 15.
`Ex. 1005, 3:13–15, 4:8–11. As noted by Petitioner (Pet. 19), Fujimoto
`describes that interlayer insulation film is made of silicon oxide film.
`Ex. 1005, 4:8–12. Dr. Rubloff testifies that a person of ordinary skill in the
`art would have known that silicon oxide is a dielectric material. Ex. 1002
`¶ 70. We find that Fujimoto discloses “depositing a first layer o