`Trials@uspto.gov
`571-272-7822 Entered: December 4, 2017
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`BROADCOM CORPORATION,
`Petitioner,
`
`v.
`
`TESSERA, INC.,
`Patent Owner.
`____________
`
`Case IPR2017-01470
`Patent 6,856,007 B2
`____________
`
`
`
`Before BARBARA A. PARVIS, ROBERT J. WEINSCHENK, and
`STACY B. MARGOLIES, Administrative Patent Judges.
`
`MARGOLIES, Administrative Patent Judge.
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`I. INTRODUCTION
`Broadcom Corporation (“Petitioner”) filed a Petition for inter partes
`review of claims 1, 11–13, 16, and 18 of U.S. Patent No. 6,856,007 B2
`(Ex. 1001, “the ’007 patent”). Paper 1 (“Pet.”). Tessera, Inc. (“Patent
`Owner”) filed a Preliminary Response. Paper 7 (“Prelim. Resp.”).
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`Institution of an inter partes review is authorized by statute when “the
`information presented in the petition . . . and any response . . . shows that
`there is a reasonable likelihood that the petitioner would prevail with respect
`to at least 1 of the claims challenged in the petition.” 35 U.S.C. § 314(a);
`see 37 C.F.R. § 42.108. Upon consideration of the Petition and the
`Preliminary Response, we conclude that the information presented shows
`that there is a reasonable likelihood that Petitioner would prevail in
`establishing the unpatentability of claim 18 of the ’007 patent.
`
`A. Related Matters
`The parties identify the following matters in which the ’007 patent has
`been asserted: (1) In re Matter of Certain Semiconductor Devices,
`Semiconductor Device Packages, and Products Containing Same, ITC
`Investigation No. 337-TA-1010 (“ITC 1010 Investigation”)1; and (2)
`Tessera, Inc. v. Broadcom Corporation, Civil Action No. 1:16-cv-00379 (D.
`Del). Pet. 1–2; Paper 4, 1; see 37 C.F.R. § 42.8(b)(2).
`
`B. The ’007 Patent
`The ’007 patent, titled “High-Frequency Chip Package,” describes as
`background that semiconductor chips used in cellular telephones and
`wireless data communication devices to process radio frequency (RF)
`signals “typically generate substantial amounts of heat.” Ex. 1001, [54],
`2:6–10. The ’007 patent states that RF chips connections to a circuit board
`
`
`1 The preliminary record here is different from the record before the ALJ in
`the ITC 1010 Investigation, including different declarants providing
`testimony in support of Broadcom’s unpatentability/invalidity contentions.
`Compare Pet. 15–53 (citing Ex. 1002 (Declaration of Dr. Suhling)), with Ex.
`2001, 163–192 (citing Direct Witness Statement of Dr. Lall).
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`“should be made with low-inductance leads having controlled, predictable
`impedance at the frequencies handled by the chip.” Id. at 2:10–15. The
`’007 patent also states that “it would be desirable to provide packages which
`are particularly well suited to RF chips using the same production equipment
`and techniques used with other package designs.” Id. at 2:17–20.
`The ’007 patent describes “a chip carrier having a large thermal
`conductor which can be solder-bonded to a circuit board so as to provide
`enhanced thermal conductivity to the circuit board and electromagnetic
`shielding” and “a conductive enclosure which partially or completely
`surrounds the packaged chip to provide additional heat dissipation and
`shielding.” Id. at Abstract. Figure 1 of the ’007 patent, below, illustrates a
`sectional view of an embodiment of the chip assembly:
`
`
`Id. at 7:14–15. As illustrated in Figure 1 above, the chip assembly includes
`packaged chip 10 mounted to circuit board 12. Id. at 7:16–17. Packaged
`chip 10 includes die 14 and chip carrier 16. Id. at 7:17–18. According to the
`’007 patent, chip carrier 16 “has a large metallic thermal conductor 20 in a
`central region and a plurality of terminals 22 in a peripheral region
`surrounding the central region.” Id. at 7:23–26. The patent discloses that
`each terminal 22 has a terminal lead 26 associated with it and that “[t]he
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`terminals, leads and thermal conductor form an electrically continuous
`structure.” Id. at 7:28–29, 7:48–49.
`The ’007 patent states that “[t]he packaged semiconductor chip is
`provided with thin layers of solder 50 on the terminals 22, 22a and with a
`thin layer of solder 52 on thermal conductor 20.” Id. at 9:48–50; see id. at
`Fig. 2 (showing terminals 22, 22a). According to the ’007 patent,
`“[d]esirably, the solder layers are less than about 75 microns thick, most
`preferably between 20 and 50 microns thick.” Id. at 9:53–55.
`The ’007 patent states that, “using conventional surface-mounting
`soldering techniques, the terminals are soldered to the contact pads 54 of the
`circuit board, whereas the thermal conductor 20 is soldered to the thermal
`conductor mounting 56 of the circuit board.” Id. at 9:61–65. The patent
`adds that “[m]ost preferably, the bond between the thermal conductor and
`the thermal conductor mounting covers substantially the entire surface area
`of the thermal conductor, as, for example, at least 80% of the thermal
`conductor surface area.” Id. at 9:65–10:2. The ’007 patent states that “the
`bond between the thermal conductor 20 and the thermal conductor mounting
`of the circuit panel 12 . . . covers a substantial area and thus has substantial
`strength and fatigue resistance.” Id. at 9:40–44.
`
`C. Illustrative Claims
`Claims 1, 11, 12, and 18 are illustrative of the subject matter of the
`challenged claims and read as follows:
`1. A packaged semiconductor chip comprising:
`(a) a first semiconductor chip having a front face, a rear
`face, edges bounding said faces and contacts exposed at said
`front face; and
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`(b) a chip carrier having inner and outer surfaces, the inner
`surface of said chip carrier facing in an upward direction toward
`said chip, said chip carrier having a plurality of terminals and a
`metallic thermal conductor having a unitary solder-wettable area
`exposed at said outer surface, said unitary solder-wettable area
`having an area larger than the area of each of said terminals, said
`thermal conductor being at least partially aligned with said chip,
`at least some of said terminals being electrically connected to at
`least some of said contacts of said chip.
`11. An assembly comprising
`a packaged chip as claimed in claim 1,
`a circuit panel having contact pads and a thermal
`conductor mounting, and
`a unitary layer of solder bonded to said thermal conductor
`mounting,
`said chip carrier being disposed on said circuit panel with
`said outer face of said chip carrier facing downwardly toward
`said circuit panel, said terminals of said chip carrier being
`connected to said contact pads of said circuit panel,
`wherein substantially all of said unitary solder-wettable
`area of said thermal conductor of said chip carrier is bonded by
`said unitary layer of solder to said thermal conductor mounting
`of said circuit panel.
`12. A packaged chip as claimed in claim 1, further
`comprising a unitary layer of solder covering substantially all of
`said unitary solder wettable area.
`18. A packaged semiconductor chip comprising:
`(a) a first semiconductor chip having a front face, a rear
`face, edges bounding said faces and contacts exposed at said
`front face;
`(b) a chip carrier having inner and outer surfaces, the inner
`surface of said chip carrier facing in an upward direction toward
`said chip, said chip carrier having a plurality of terminals and a
`metallic thermal conductor exposed at said outer surface, said
`thermal conductor having area larger than the area of each of said
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`terminals, said thermal conductor being at least partially aligned
`with said chip, at least some of said terminals being electrically
`connected to at least some of said contacts of said chip; and
`(c) a circuit panel having contact pads and a thermal
`conductor mounting, said chip carrier being disposed on said
`circuit panel with said outer face of said chip carrier facing
`downwardly toward said circuit panel, said terminals of said chip
`carrier being connected to said contact pads of said circuit panel,
`said thermal conductor of said chip carrier being bonded to said
`thermal conductor mounting of said circuit panel at a spacing of
`between about 25 µm and 50 µm.
`Id. at 22:39–53, 23:20–33, 24:26–49, Certificate of Correction (emphasis
`added to disputed limitations and indentations added to claim 11).
`
`D. Asserted Grounds of Unpatentability
`Petitioner contends that claims 1, 11–13, 16, and 18 of the ’007 patent
`are unpatentable based on the following specific grounds (Pet. 2–3, 15–54):
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`Reference(s)
`
`MLF Application Notes2
`MLF Application Notes,
`Clech,4 Gustafsson,5 Luo,6
`and Syed7
`Sharma8
`Sharma, Clech, Gustafsson,
`Luo, and Syed
`
`Basis
`35 U.S.C.
`§ 102(a)3
`
`Challenged Claim(s)
`
`1, 11–13, 16, and 18
`
`35 U.S.C. § 103
`
`1, 11–13, 16, and 18
`
`35 U.S.C. § 102(e) 1
`35 U.S.C. § 103
`11–13, 16, and 18
`
`In its analysis, Petitioner relies on the declaration testimony of Dr. Jeffrey C.
`Suhling (Ex. 1002).
`
`
`2 Application Notes for Surface Mount Assembly of Amkor’s
`MicroLeadFrame (MLF) Packages, Amkor Technologies (March 2001) (Ex.
`1015, “MLF Application Notes”).
`3 The Leahy-Smith America Invents Act (“AIA”), Pub. L. No. 112-29, 125
`Stat. 284, 287–88 (2011), revised 35 U.S.C. §§ 102 and 103, effective March
`16, 2013. Because the challenged patent was filed before March 16, 2013,
`we refer to the pre-AIA versions of §§ 102 and 103 in this Decision.
`4 Clech, Solder Reliability Solutions: A PC-Based Design-for-Reliability,
`ESPI (Sept. 1996) (Ex. 1009, “Clech”).
`5 Gustafsson, Solder Joint Reliability of a Lead-Less RF-transistor, 1998
`Electronic Components and Technology Conference 87–91 (Ex. 1010,
`“Gustafsson”).
`6 Luo et al., Effect of the Thickness of a Thermal Interface Material (Solder)
`on Heat Transfer Between Copper Surfaces, 24(2) Int’l J. of Microcircuits
`and Electronic Packaging 141–147 (2nd Q 2001) (Ex. 1011, “Luo”).
`7 Syed et al., LGA vs. BGA: What is more Reliable? A 2nd Level Reliability
`Comparison, Surface Mount Technology Association International
`Conference Proceedings (Sept. 24, 2000) (Ex. 1019, “Syed”).
`8 U.S. Patent No. 6,420,779 B1, filed Sept. 14, 1999, issued July 16, 2002
`(Ex. 1018, “Sharma”).
`
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`II. DISCUSSION
`
`A. Claim Construction
`In an inter partes review, we construe claim terms in an unexpired
`patent according to their broadest reasonable construction in light of the
`specification of the patent in which they appear. 37 C.F.R. § 42.100(b);
`Cuozzo Speed Techs., LLC v. Lee, 136 S. Ct. 2131, 2144–46 (2016)
`(upholding the use of the broadest reasonable interpretation standard).
`Consistent with the broadest reasonable construction, claim terms are
`presumed to have their ordinary and customary meaning as understood by a
`person of ordinary skill in the art in the context of the entire patent
`disclosure. In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir.
`2007). In addition, the Board may not “construe claims during [an inter
`partes review] so broadly that its constructions are unreasonable under
`general claim construction principles.” Microsoft Corp. v. Proxyconn, Inc.,
`789 F.3d 1292, 1298 (Fed. Cir. 2015) (emphasis omitted). An inventor may
`provide a meaning for a term that is different from its ordinary meaning by
`defining the term in the specification with reasonable clarity, deliberateness,
`and precision. In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994).
`Petitioner proposes constructions for “chip carrier,” “unitary solder
`wettable area,” and “unitary layer of solder,” arguing that the phrases
`“should be construed consistent with the ALJ’s construction” in the ITC
`1010 Investigation. Pet. 13. For example, Petitioner proposes that “unitary
`layer of solder” should be construed to be consistent with “a single
`continuous layer of solder.” Id. at 13 (citing Ex. 1002, 17–20 (ALJ
`construing the phrase as “a single, continuous layer of solder”)). Petitioner
`also argues that the ALJ’s construction of “substantially all of said unitary
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`solder-wettable area of said thermal conductor” “is indefinite” but that the
`challenged claims “are invalid in view of the grounds set forth [in the
`Petition] under either the ALJ’s construction or the more specific
`construction offered by Respondents” in the ITC 1010 Investigation. Id. at
`14. Petitioner also argues that the phrases “said unitary layer of solder has a
`thickness of between 25 µm and 50 µm” and “bonded to said thermal
`conductor mounting of said circuit panel at a spacing of between 25 µm and
`50 µm” should be construed according to their plain and ordinary meaning,
`and asserts that Dr. Suhling’s testimony in the ITC 1010 Investigation
`regarding the “accustomed meaning” is correct. Id. at 14–15. Petitioner
`adds that “the claims are invalid based on the grounds asserted in this
`proceeding regardless of whether the Board adopts Dr. Suhling’s testimony
`[from the ITC 1010 Investigation].” Id. at 15. Finally, with respect to the
`phrase “at least partially aligned,” Petitioner argues that no construction of
`the term is required “[b]ecause the prior art relied upon . . . shows a
`packaged chip in which the thermal conductor of the chip carrier is fully
`aligned with the chip.” Id. at 15.
`Patent Owner does not propose any claim constructions, asserting that
`“no issued raised by [its] Preliminary Response depends on the proper
`construction of the claims.” Prelim. Resp. 23.
`We determine that we do not need to construe any claim term or
`phrase to determine whether or not to institute inter partes review. We
`address the “unitary layer of solder” limitation below in analyzing
`Petitioner’s proposed grounds of unpatentability.
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`B. Level of Ordinary Skill
`Petitioner’s declarant, Dr. Suhling, opines that a person of ordinary
`skill in the art of the ’007 patent would have had “a Bachelor’s degree in
`physics or engineering and about four years of experience in semiconductor
`packaging.” Ex. 1002 ¶ 16.9
`Patent Owner does not propose an alternative definition for the level
`of ordinary skill in the art, or otherwise comment on Dr. Suhling’s proposed
`definition. See Prelim. Resp. 23.
`We determine on the current record that the level of ordinary skill
`proposed by Dr. Suhling is consistent with the challenged patent and the
`asserted prior art and we therefore adopt that level for the purposes of this
`decision.
`
`C. Asserted Anticipation and Obviousness Based on
`the MLF Application Notes
`Petitioner contends that claims 1, 11–13, 16, and 18 of the ’007 patent
`are unpatentable under 35 U.S.C. § 102(a) as anticipated by the MLF
`Application Notes and as obvious over MLF Application Notes and
`“knowledge of a person of ordinary skill” as evidenced by Clech,
`Gustafsson, Luo, and Syed. Pet. 2–3, 16–43. Relying in part on the
`testimony of Dr. Suhling, Petitioner explains how the MLF Application
`Notes disclose each limitation of the claims for purposes of anticipation,
`how the references allegedly teach or suggest the claim limitations for
`
`
`9 In support of its assertion regarding the level of ordinary skill in the art,
`Petitioner miscites to paragraph 13 of Dr. Suhling’s declaration. See Pet. 4
`(citing Ex. 1002 ¶ 13).
`
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`purposes of obviousness, and provides purported reasoning for combining
`the teachings of the references. Id. at 16–43.
`
`1. Summary of the MLF Application Notes
`The MLF Application Notes are purportedly from Amkor
`Technology’s website10 and are titled “Application Notes for Surface Mount
`Assembly of Amkor’s MicroLeadFrame (MLF) Packages.” Ex. 1015, 1.
`According to the MLF Application Notes, the MLF package “is a leadless
`package where electrical contact to the [printed circuit board (PCB)] is made
`by soldering the lands on the bottom surface of the package to the PCB,
`instead of the conventional formed perimeter leads.” Id. at 3.
`Figure 1 of the MLF Application Notes, shown below, illustrates a
`cross section of the MLF package:
`
`Id. As shown in Figure 1 above, and according to the MLF Application
`Notes, the MLF package has “a copper leadframe substrate” and an
`“exposed die attach paddle on the bottom,” which “efficiently conducts heat
`to the PCB.” Id.
`
`
`
`
`10 Section II.C.6.a below addresses the issue of whether Petitioner has shown
`sufficiently that the MLF Application Notes are prior art to the challenged
`claims.
`
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`The MLF Application Notes discloses that “[s]ince the package does
`not have any solder balls or bumps, the electrical connections between the
`package and the motherboard is made by printing the solder paste on the
`motherboard and reflowing it after component placement.” Id. at 4.
`According to the MLF Application Notes, “[i]n order to form reliable solder
`joints, special attention is needed in designing the motherboard pad pattern
`and solder paste printing.” Id.
`Figure 2 of the MLF Application Notes, shown below, illustrates the
`bottom and side views of the package, indicating the dimensions needed in
`connection with designing the pad pattern for the PCB:
`
`
`
`Id. As shown in Figure 2 above and as described in the MLF Application
`Notes, “[s]ince most packages are square with [dimensions] D=E and the
`leads are along the E direction for dual packages, the side view dimensions
`(D, S, D2, and L) are used to determine the land length on the PCB.” Id.
`Figure 3 of the MLF Application Notes, shown below, illustrates the
`PCB pad pattern dimensions that also need to be determined:
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`Id. Figure 3 above illustrates, among other dimensions, dimensions for the
`width and length of the pad and clearances to avoid solder bridging. Id.
`Table 1 of the MLF Application Notes identifies particular package and PCB
`land pattern dimensions for packages of different sizes, including 3x3, 7x7,
`and 10x10 mm. Id. at 7.
`The MLF Application Notes discloses that the thermal pad “provides
`a solderable surface on the top surface of the PCB (to solder the package die
`paddle on the board).” Id. at 8. The MLF Application Notes also states that
`“[n]ormally, the size of the thermal pad should at least match the exposed
`die paddle size.” Id.
`The MLF Application Notes describes designing the solder paste
`stencil for the thermal pad. Id. at 12. The MLF Application Notes states:
`“In order to effectively remove the heat from the package and to enhance
`electrical performance[,] the die paddle needs to be soldered to the PCB
`thermal pad, preferably with minimum voids. However, eliminating voids
`may not be possible because of presence of thermal vias and the large size of
`the thermal pad for larger size packages.” Id. The MLF Application Notes
`recommends that “smaller multiple openings in [the] stencil should be used
`instead of one big opening for printing solder paste on the thermal pad
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`region,” and states that “[t]his will typically result in 50 to 80% solder paste
`coverage.” Id. Example stencil designs are illustrated in Figure 11 below:
`
`
`
`Id. According to the MLF Application Notes, Figure 11 above illustrates
`thermal pad stencil designs for 7x7 and 10x10 mm MLF packages, with
`solder paste coverages ranging from 48% to 81%. Id.
`
`2. Summary of Clech
`Clech is an article titled “Solder Reliability Solutions: A PC-Based
`Design-for-Reliability Tool.” Ex. 1009, 1. Petitioner asserts that Clech was
`published on September 10, 1996 at the Surface Mount International
`Conference, and made available through the Surface Mount Technology
`Association (SMTA) Knowledgebase website. Pet. 22 (citing Ex. 1002
`¶ 63). Patent Owner, in its Preliminary Response, does not challenge
`Petitioner’s assertion that Clech is prior art under Section 102(b).
`Clech describes a solder joint fatigue model “to capture the main
`effects of solder joint deformations and joint interaction with the attached
`component and substrate.” Ex. 1009, 14. According to Clech, the model
`“has been implemented as a PC-based design-for-reliability tool that applies
`to the grand families of surface mount components from [Leadless Ceramic
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`Chip Carriers (LCCCs)] to leaded assemblies, area-array and emerging chip-
`scale packages.” Id. Clech discloses that the model was applied to
`castellated LCCCs, the solder joint parameters of which are shown in Figure
`6 of Clech below:
`
`
`Id. at 6–7. As shown in Figure 6 above, and according to Clech, castellated
`LCCCs “have a low stand-off height (h1) and toe fillets that run up the
`castellations.” Id. at 7. Clech states that dimensions h1, A1, and A2 “are
`estimated from solder joint cross sections and crack areas.” Id. at 7. Clech
`discloses h1 values of 1.4 mil and 1.6 mil.11 Id. Clech discloses that
`“[s]older joint cracking initiates in the heel fillet under the component and
`propagates under the LCCC termination (crack area A1).” Id. Clech adds
`that “[p]rovided that solder volume is large enough, a significant fraction of
`the fatigue life is spent propagating cracks through the toe fillet (crack area
`A2).” Id.
`
`3. Summary of Luo
`Luo is a journal article bearing a date of “Second Quarter, 2001” and
`is titled “Effect of the Thickness of a Thermal Interface Material (Solder) on
`
`11 Petitioner asserts that a range of 1.4 to 1.6 mil is “around 35 µm – 41 µm.”
`Pet. 22.
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`Heat Transfer Between Copper Surfaces.” Ex. 1011, 1. Petitioner asserts
`Luo is prior art under Section 102(b). Pet. 20–21 (citing, e.g., Ex. 1002
`¶ 74). Patent Owner, in its Preliminary Response, does not challenge
`Petitioner’s assertion that Luo is prior art under Section 102(b).
`Luo describes a study of “[t]he effect of solder thickness (from 10 to
`30 µm12) on the heat transfer between two copper surfaces.” Id. at 2. Luo
`states that “[h]eat dissipation[] is a critical problem that limits the reliability,
`performance and further miniaturization of microelectronics.” Id. at 1. Luo
`states that “[a]lthough solder is commonly used and the solder thickness can
`vary greatly in practice, the effect of its thickness on the heat transfer has not
`been previously addressed.” Id. at 2 (noting that previous work has
`addressed solder thickness on the electrical resistance of a soldered joint).
`According to Luo, “the greater the solder thickness in the copper-
`solder-copper sandwich, . . . the slower is the heat transfer.” Id. at 3. Luo
`states that “[i]ncreasing the solder thickness from 10 to 30 µm causes a 25%
`increase” in heat transfer time. Id. at 4; see also id. at 1. Thus, according to
`Luo, “minimization of the solder thickness is recommended in practice.” Id.
`at 1, 4.
`
`4. Summary of Gustafsson
`Gustafsson is a journal article titled “Solder Joint Reliability of a
`Lead-Less RF-transistor.” Ex. 1010, 1. Petitioner asserts that Gustafsson
`was published in 1998 in the Proceedings of the 48th Electronic Components
`and Technology Conference. Pet. 23 (citing Ex. 1002 ¶ 63). Patent Owner,
`
`
`12 Both Petitioner and Patent Owner refer to Luo’s disclosure of the
`measurement in terms of micrometers. Pet. 21; Prelim. Resp. 15.
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`in its Preliminary Response, does not challenge Petitioner’s assertion that
`Gustafsson is prior art under Section 102(b).
`Gustafsson describes a study of “the solder joint life of a lead-less RF-
`transistor mounted on a 2-layer PCB.” Ex. 1010, 1. Gustafsson states that
`“[a]lthough the solder joint reliability of lead-less ceramic chip carriers has
`been studied for many years, this component is different because the
`package material is aluminum nitride and almost the entire bottom surface of
`the package is soldered to the board to achieve good thermal conduction.”
`Id.
`
`Figure 2 of Gustafsson is shown below:
`
`
`Id. at 2. According to Gustafsson, Figure 2 above illustrates a cross section
`on one of the solder joints of the lead-less RF transistor component. Id. at
`1–2. Gustafsson states that “the solder thickness underneath the component
`was typically 0.04 mm.” Id. at 2.
`
`5. Summary of Syed
`Syed is an article titled “LGA vs. BGA: What Is More Reliable? A
`2nd Level Reliability Comparison.” Ex. 1019, 1. Petitioner asserts that Syed
`was published September 2000 in the Proceedings of the SMTA
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`International Conference, available through the SMTA website. Pet. 24
`(citing Ex. 1002 ¶ 63). Patent Owner, in its Preliminary Response, does not
`challenge Petitioner’s assertion that Syed is prior art under Section 102(b).
`Syed discloses that a land grid array (LGA) “is an area array package
`similar to the [ball grid arrays (BGAs)] but without solder sphere or balls
`attached to the package.” Ex. 1019, 1. According to Syed, the LGA
`package is “mounted on the motherboard by printing and reflowing solder
`paste on the board resulting in solder joint height of 2 to 3 mils13 as opposed
`to 8 to 15 mils for a fine pitch BGA package.” Id. Syed states that “[t]his
`not only reduces the overall mounted height of the package (a plus of slim
`portable electronic products) but has also been thought to improve the board
`level reliability for cyclic bending and drop.” Id.
`
`6. Analysis
`a. Whether Petitioner Has Made a Sufficient Showing that the MLF
`Application Notes Are Prior Art under § 102(a)
`Petitioner contends that the MLF Application Notes are prior art to the
`’007 patent under 35 U.S.C. § 102(a). Pet. 2–3, 16–18. Petitioner asserts
`that “the MLF Application Notes were publicly accessible to persons
`interested in the art prior to the filing date” of the ’007 patent. Id. at 18.14
`Petitioner relies on the date appearing on the MLF Application Notes—
`
`
`13 A range of 2 to 3 mils equals a range of 50.8 to 76.2 µm. See Pet. 24;
`Prelim. Resp. 21.
`14 Petitioner refers to both the filing date of the ’007 patent and to “the
`August 28, 2001 priority date” of the ’007 patent. Pet. 17 (“The MLF
`Application Notes bear a date of March, 2001, i.e., five months prior to the
`August 28, 2001 priority date of the ‘007 patent”), 18 (referring to “the filing
`date” of the patent).
`
`18
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`IPR2017-01470
`Patent 6,856,007 B2
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`March 2001—and a printout from the Internet Archive’s “Wayback
`Machine” purportedly indicating that the Notes were “publicly accessible to
`persons of ordinary skill through Amkor’s website.” Id. at 17 (citing Exs.
`1015, 1016). Although Petitioner asserts that Internet Archive printout
`shows access to the Notes as of April 2000, we understand Petitioner to
`assert access as of April 2001 because the Internet Archive printout actually
`lists a date of March 26, 2001 next to the title of the MLF Application Notes
`document. Compare Pet. 17, with Ex. 1016. Petitioner further relies on an
`Information Disclosure Statement (IDS) submitted in August 2001 by
`Micron to the Patent and Trademark Office which cites the MLF Application
`Notes. Pet. 18 (citing Ex. 1017).
`Patent Owner argues that Petitioner fails to make a threshold showing
`that the MLF Application Notes were available to the interested public
`before August 28, 2001, the filing date of the related provisional application
`identified on the front page of the ’007 patent. See Prelim. Resp. 25–29; Ex.
`1001, [60]. Patent Owner argues that Petitioner fails to explain how the
`Internet Archive printout establishes that the MLF Application Notes “were
`sufficiently accessible to the public interested in the art before the critical
`date.” Prelim. Resp. 26–27. With respect to Micron’s citation of the MLF
`Application Notes in an IDS, Patent Owner argues that “[t]here is no
`evidence in the record about how Micron obtained the document, nor
`whether Micron complied with any applicable restrictions on use by
`identifying the document by name to the USPTO.” Id. at 28.
`On the current record, there is sufficient evidence showing that the
`MLF Application Notes is a prior art printed publication under 35 U.S.C.
`§ 102(a) to the challenged claims of the ’007 patent. Petitioner relies on a
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`document with a URL for the Internet Archive illustrating that a document
`with the identical title and date as that of the MLF Application Notes was
`available on Amkor’s website by April 2001. Pet 17 (citing Ex. 1016).
`Petitioner also cites to an August 2001 IDS filed by a third party (Micron)
`that cites the identically-titled and dated MLF Application Notes. Id. at 18
`(citing Ex. 1017). Petitioner also relies on Dr. Suhling’s testimony that “[i]t
`was commonplace in the industry for chip manufacturers to make soldering
`guidelines publicly available to its customers without restrictions on use.”
`Id. (citing Ex. 1002 ¶ 92). Considering the evidence as a whole, Petitioner
`has a made a sufficient showing for institution purposes.
`b. Claim 1
`Patent Owner requests that “the Board cancel claim 1” of the ’007
`patent and that, “pursuant to 37 C.F.R. § 42.73(b),” “the Board enter adverse
`judgment against claim 1 in this proceeding.” Prelim. Resp. 24. On
`November 29, 2017, Patent Owner filed a statutory disclaimer, disclaiming
`claim 1 of the ’007 patent. See Paper 8, 1; Ex. 2004.
`Under 37 C.F.R. § 42.107(e), “[t]he patent owner may file a statutory
`disclaimer under 35 U.S.C. 253(a)[,] disclaiming one or more claims in the
`patent.” According to Rule 42.107(e), “[n]o inter partes review will be
`instituted based on disclaimed claims.” Because Patent Owner filed a
`statutory disclaimer disclaiming claim 1, we do not institute review as to
`claim 1 of the ’007 patent.
`c. Anticipation of Claims 11, 12, 13, and 16
`Each of claims 11, 12, 13, 16 requires “a unitary layer of solder.”
`Claim 11 recites, among other limitations, “a circuit panel having contact
`pads and a thermal conductor mounting” and “a unitary layer of solder
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`bonded to said thermal conductor mounting.” Claim 12 requires, among
`other components, a packaged semiconductor chip including a “a chip
`carrier[,] said chip carrier having . . . a metallic thermal conductor having a
`unitary solder-wettable area” (recited in claim 1), the packaged chip “further
`comprising a unitary layer of solder covering substantially all of said unitary
`solder wettable area” (recited in claim 12). Claims 13 and 16 depend from
`claims 11 and 12, respectively.
`Petitioner applies the ALJ’s construction in the ITC 1010
`Investigation—“a single, continuous layer of solder”—and contends that the
`MLF Application Notes discloses a single, continuous layer of solder. Pet.
`28–33 (analyzing limitation in claim 12), 40–41 (in addressing limitation in
`claim 11, relying on analysis of claim 12 for how “the MLF Application
`Notes describe a unitary layer of solder that is applied to the thermal pad”).
`Specifically, Petitioner argues that the “[t]he MLF Application Notes make
`clear that layer of solder is applied to the large rectangular PCB land pattern
`shown in Figure 3” of the MLF Application Notes, and that the Notes state
`that “the thermal pad provides a solderable surface on the top surface of the
`PCB (to solder the package die paddle on the board).” Pet. 28–29.
`Petitioner asserts that “solder applied to the thermal pad would adhere to the
`entire surface of both the thermal pad and exposed die paddle during reflow”
`and “[c]onsequently, there would be a unitary layer of solder covering
`substantially all of said unitary solder wettable area.” Id. at 29–30.
`Pet