Paper 9
`Trials@uspto.gov
`Entered: December 21, 2017
`Tel: 571-272-7822
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`TOSHIBA CORPORATION, TOSHIBA MEMORY CORPORATION, and
`TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.,
`Petitioners,
`v.
`MACRONIX INTERNATIONAL CO., LTD.,
`Patent Owner.
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
`
`
`
`
`Before KEN B. BARRETT, JENNIFER S. BISK, and JASON M. REPKO,
`Administrative Patent Judges.
`REPKO, Administrative Patent Judge.
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`Trials@uspto.gov
`Entered: December 21, 2017
`Tel: 571-272-7822
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`TOSHIBA CORPORATION, TOSHIBA MEMORY CORPORATION, and
`TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.,
`Petitioners,
`v.
`MACRONIX INTERNATIONAL CO., LTD.,
`Patent Owner.
`
`Case IPR2017-01632
`Patent 8,035,417 B1
`
`
`
`
`
`Before KEN B. BARRETT, JENNIFER S. BISK, and JASON M. REPKO,
`Administrative Patent Judges.
`REPKO, Administrative Patent Judge.
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`
`
`IPR2017-01632
`Patent 8,035,417 B1
`
`INTRODUCTION
`I.
`A. Background and Summary
`Toshiba Corporation, Toshiba Memory Corporation, and Toshiba
`America Electronic Components, Inc. (collectively, “Petitioners”) filed a
`petition (Paper 1, “Pet.”)1 to institute an inter partes review of claims 1–7,
`11–16, and 18 of U.S. Patent No. 8,035,417 B1 (Ex. 1001, the “’417
`patent”). 35 U.S.C. § 311. Macronix International Co., Ltd. (“Patent
`Owner”) filed a Preliminary Response. Paper 8 (“Prelim. Resp.”).
`For the reasons that follow, we institute an inter partes review for all
`the challenged claims.
`
`
`B. Related Matters
`According to Petitioners, the ’417 patent is involved in matters before
`the United States International Trade Commission (Inv. No. 337-TA-1046)
`and the United States District Court for the Southern District of California
`(Case No. 17-cv-0462). Pet. 1–2.
`
`
`The ’417 Patent
`C.
`The ’417 patent describes an output buffer circuit with a variable
`output drive strength. Ex. 1001, Abstract. An output buffer drives a load by
`setting a voltage on an output line. Id. at 5:61–62. The driver capability,
`however, should be suitable for its application. See id. at 5:61–67. An
`
`
`1 In an email message to the Board on August 21, 2017, Petitioners
`requested authorization to file a corrected version of the petition. In
`response, the Board requested that the parties meet and confer regarding this
`request and update the Board. However, no update has been received. We
`have entered these emails as Exhibit 3001.
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`unsuitable driver capability may slow performance or create power noise.
`See id. To reduce power noise and meet speed and loading requirements, the
`’417 patent describes combining multiple output buffer circuits to vary the
`drive strength. Id. at 8:49–55. For example, Figure 6 of the ’417 patent,
`reproduced below, illustrates a block diagram of multiple output buffer
`circuits sharing output DQ.
`
`
`As shown in Figure 6 above, the output buffers receive control-input signals
`(OPON1–OPONM and OPONB1–OPONBM). Id. at 8:35–38. These
`control-input signals can enable some output buffer circuits and disable
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`others. Id. at 8:39–48. The combined drive strength equals the sum of the
`drive strengths of the enabled output buffers. Id. at 8:49–53. Accordingly,
`the ’417 patent discloses varying the combined drive strength by selectively
`enabling and disabling the buffers. Id. at 8:42–55.
`
`
`D. Illustrative Claim
`Of the challenged claims, claims 1, 11, and 18 are independent.
`Claims 2–7 and 12–16 depend directly or indirectly from claims 1 or 11.
`Claim 1 is illustrative:
`1.
`An apparatus, comprising:
`a plurality of output buffer circuits coupled in parallel to
`provide a combined output drive strength, each output buffer
`circuit of the plurality of output buffer circuits including:
`a buffer data input receiving a data input signal shared
`across the plurality of output buffer circuits;
`a first buffer enable input receiving a first buffer enable
`signal shared across the plurality of output buffer circuits;
`a second buffer enable input receiving a second buffer
`enable signal customized across the plurality of output buffer
`circuits;
`a buffer data output providing a data output signal having
`a drive strength,
`wherein the data output signal is combined across the plurality
`of output buffer circuits to provide a combined data output
`signal having the combined output drive strength, and the
`combined output drive strength is tuned by the second buffer
`enable signals customized across the plurality of output buffer
`circuits,
`wherein buffer enable signals are received together with
`complements of the buffer enable signals, and the buffer enable
`signals and the complements of the buffer enable signals
`control pairs of transistors having opposite conductivity types,
`and the buffer enable signals include the first buffer enable
`signal and the second buffer enable signal.
`
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`Id. at 9:35–62.
`
`E. Applied References
`Petitioners rely upon the references listed below. Pet. 4.
`
`Reference
`U.S. Patent No. 7,307,836 B2 to Yen et al.
`
`Exhibit
`1003
`
`U.S. Patent Application No. 2007/0247194 A1 to Jain
`
`Asserted Grounds of Unpatentability
`F.
`Petitioners assert the following grounds of unpatentability. Pet. 4.
`
`1004
`
`References
`Yen et al.
`
`Claims challenged
`Basis
`Pre-AIA2 35 U.S.C. § 102(a) and (b) 1–7, 11–16, and 18
`
`Yen et al. and Jain
`
`
`Pre-AIA 35 U.S.C. § 103
`
`1–7, 11–16, and 18
`
`II. ANALYSIS
`A. Claim Construction
`In an inter partes review, claim terms in an unexpired patent are given
`their broadest reasonable construction in light of the specification of the
`patent in which they appear. 37 C.F.R. § 42.100(b). Under the broadest
`reasonable interpretation standard, claim terms generally are given their
`ordinary and customary meaning, as would be understood by one of ordinary
`
`
`2 Because the claims at issue have a filing date prior to March 16, 2013, the
`effective date of the Leahy-Smith America Invents Act, Pub. L. No. 112-29,
`125 Stat. 284 (2011) (“AIA”), the pre-AIA version of 35 U.S.C. §§ 102 and
`103 applies here.
`
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`skill in the art in the context of the entire disclosure. See In re Translogic
`Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007).
`Only those claim terms and elements that are in controversy need to
`be construed and only to the extent necessary to resolve the controversy.
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir.
`1999). The parties propose constructions for “customized across,” “enable,”
`and “disable.” Pet. 14–18; Prelim. Resp. 8–11. For purposes of this
`Decision, we find it necessary to address only the claim term “customized
`across.”
`Of the three independent claims challenged, only claims 1 and 11
`recite the term “customized across.” Ex. 1001, 9:35–62, 11:54–12:3, 12:49–
`65. In particular, claim 1 recites, in part, “a second buffer enable input
`receiving a second buffer enable signal customized across the plurality of
`output buffer circuits.” Id. at 9:45–47 (emphasis added). Similarly, claim
`11 recites, in part, “the combined output drive strength is tuned by buffer
`enable signals customized across the plurality of output buffer circuits.”
`Id. at 11:63–65 (emphasis added).
`Petitioners and Patent Owner each propose a construction of
`“customized across.” Pet. 15–17; Prelim. Resp. 11. Under Petitioners’
`construction, the term means “individually enabling each of.” Pet. 16.
`Under Patent Owner’s construction, the term means “individually enable or
`disable each of.” Prelim. Resp. 11 (citing Ex. 1001, 2:9–13) (emphasis
`added).
`There is not a meaningful difference between the parties’ positions as
`it relates to the analysis below. Nevertheless, for clarity and completeness,
`we do agree with Patent Owner that the term can also cover signals having a
`
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`disable value. Prelim. Resp. 11. For example, the Specification discloses a
`second buffer enable signal having a disable value: “OPON=low in some
`embodiments.” Ex. 1001, 2:9–13, quoted in Prelim. Resp. 11. Thus, for the
`purposes of this Decision, we adopt Patent Owner’s construction of
`“customized across.”
`
`
`B. Level of Ordinary Skill in the Art
`In determining the level of ordinary skill in the art, various factors
`may be considered, including the “type of problems encountered in the art;
`prior art solutions to those problems; rapidity with which innovations are
`made; sophistication of the technology; and educational level of active
`workers in the field.” In re GPAC, Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995)
`(citation omitted).
`Petitioners’ expert, Dr. Noel R. Strader II, testifies that a person
`having ordinary skill in the art at the time of invention “would have had a
`Bachelor’s Degree in electrical engineering and either 2 years of experience
`in transistor-level circuit design or a Master’s Degree in electrical
`engineering and one year of equivalent experience.” Ex. 1005 (“Strader
`Decl.”) ¶ 34, cited in Pet. 14–13.
`Patent Owner does not propose an alternative definition for the level
`of ordinary skill in the art. See generally Prelim. Resp.
`We further find that the prior art in this proceeding reflects the level
`of ordinary skill in the art at the time of the invention. See Okajima v.
`Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001). Considering the current
`record, we apply Dr. Strader’s definition of the level of skill in the art in our
`analysis below.
`
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`
`C. Anticipation
`Petitioners assert that claims 1–7, 11–16, and 18 (all challenged
`claims) are unpatentable under 35 U.S.C. § 102 as anticipated by Yen.
`Pet. 7, 18–60. For the reasons discussed below, Petitioners have shown a
`reasonable likelihood of prevailing on this ground of unpatentability.
`1. Overview of Yen
`Yen discloses a programmable-strength output buffer. Ex. 1003,
`Abstract. In particular, Yen connects several outputs together to provide the
`buffer’s final, programmed output signal. See, e.g., id. at 5:16–20, 6:35–47,
`Figs. 3, 4. In response to a control signal, Yen’s configuration varies the
`strength of at least some output signals. Id., Abstract. In this way, Yen’s
`output buffer customizes the output signal for the connected load. Id.
`2. Analysis
`I
`Petitioners annotate Yen’s Figures 3 and 4 to illustrate the
`correspondence between Yen and the challenged claims. Pet. 21–22 (citing
`Ex. 1005 ¶¶ 49–56). Yen’s Figure 3 is reproduced below with Petitioners’
`annotations.
`
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`
`
`Yen’s Figure 3 is shown above with Petitioners’ annotations on drivers 44,
`48, and 50 and their corresponding AND gates. Pet. 21.
`According to Yen, Figure 3 is a “block/schematic diagram” of Yen’s
`programmable-strength output buffer. Ex. 1003, 3:15–16. Yen’s diagram
`shows drivers 44, 48, and 50 with corresponding AND gates. Id. at 5:38–41,
`5:48–50. According to Petitioners, each driver together with the associated
`AND gate corresponds to one of the recited output buffer circuits. Pet. 21
`(citing Ex. 1005 ¶ 51).
`Petitioners explain that Yen’s Figure 4 also shows the recited output
`buffer circuits. Pet. 21–23. Petitioners’ annotated version of this figure is
`reproduced below. Id. at 22.
`
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`
`
`Yen’s Figure 4 is shown above with Petitioners’ annotations on transistors
`MP4, MP3, MN3, MN4, MP6, MP5, MN5, and MN6 as well as the
`associated AND and OR gates. Id.
`As shown above, Figure 4 is a “schematic diagram” of Yen’s output buffer.
`Ex. 1003, 3:15–18. According to Petitioners, transistors MP4, MP3, MN3,
`and MN4 together with their associated AND and OR gates correspond to
`the recited output buffer circuit. Pet. 23 (citing Ex. 1005 ¶¶ 53–56).
`Petitioners further explain that transistors MP6, MP5, MN5, and MN6
`together with their AND and OR gates form another output buffer circuit.
`Pet. 23 (citing Ex. 1005 ¶¶ 54–56).
`Patent Owner argues that Petitioners’ anticipation analysis is based,
`improperly, on multiple distinct teachings. Prelim. Resp. 12–15. In
`particular, Patent Owner contends that Petitioners have not shown that
`Figure 3 discloses the same implementation as Figure 4. Id. According to
`Patent Owner, Yen suggests that these figures are separate and distinct
`implementations of the buffer circuit. Id. at 13. To support this position,
`
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`Patent Owner points to Yen’s description of the figures. Id. (citing
`Ex. 1003, 3:15–18, 5:9–11, 6:23–25). Patent Owner contends that (1) Yen
`describes each figure as “a” diagram, (2) Yen suggests separate
`embodiments because the figures are described as an “exemplary
`embodiment” and “one possible implementation,” and (3) Yen does not state
`that the figures depict the same embodiment. Prelim. Resp. 13–14.
`The cited portion from Yen, however, describes Figure 4 as “a
`schematic diagram” and Figure 3 as “a block/schematic diagram.” Ex. 1003,
`3:15–18 (emphasis added), cited in Prelim. Resp. 13. The most natural
`reading of these figures, based on the current record, is that because Figure 3
`is partly a block diagram, Figure 3 shows fewer features than Figure 4, but
`those features are of the same embodiment. Ex. 1003, Figs. 3, 4. For
`example, Yen’s Figure 3 does not show individual transistors, but Figure 4
`does. Compare id. Fig. 4, MP4, MP3, MN3, and MN4 with id. Fig. 3, item
`44. Thus, on the current record, we are unpersuaded that Petitioners have
`improperly relied on separate and distinct implementations, as argued. See
`Prelim. Resp. 12–15.
`Even if we accept Patent Owner’s argument that Yen’s figures are
`distinct embodiments (id.), Petitioners, nevertheless, have relied on the
`features of Yen’s Figure 4 for each limitation of claims 1, 11, and 18.
`Pet. 19–40. Thus, in Petitioners’ anticipation analysis, Yen’s Figure 3 is
`cumulative to, not mixed with, Figure 4’s disclosure. See id. For the
`purpose of institution, Petitioners sufficiently show that Yen’s output
`buffer—in both Figures 3 and 4—includes the recited inputs, output, and
`remaining limitations, which we turn to next.
`
`11
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`
`II
`As discussed above, we interpret “customized across the plurality of
`output buffers” to mean that the signals “individually enable or disable each
`of” the recited buffers. Supra § II A (citing Prelim. Resp. 11) (emphasis
`added).
`According to Petitioners’ proposed mapping, not all of Yen’s buffer
`circuits correspond to the recited “plurality of output buffers.” Pet. 23–24.
`Petitioners explain that claim 1 uses the term “comprising” and, therefore,
`does not exclude additional, unrecited elements. Id. at 24 (citing Genentech,
`Inc. v. Chiron Corp., 112 F.3d 495, 501 (Fed. Cir. 1997)). Based on this
`interpretation, Petitioners then conclude that Yen anticipates claim 1 even
`though Yen discloses additional output drivers. Pet. 24–25 (citing
`Ex. 1005 ¶¶ 49–60). Petitioners note that Yen’s Figure 3 shows driver 42,
`and Yen’s Figure 4 shows an additional output driver comprising transistors
`MP1, MP2, MN1 and MN2.3 Pet. 23–24. So, although these drivers do not
`receive a second buffer enable signal (Yen’s OS1, OS2, and OS3) like the
`recited output buffer circuits, Petitioners explain that Yen’s additional output
`drivers (e.g., driver 42) should not be considered one of the recited “plurality
`of output buffer circuits” under their mapping. Id. at 24, 29–30.
`
`
`3 We note that Petitioners state the additional output circuit comprises
`“transistors MP2, MP2, MN1 and MN2.” Pet. 23–24 (emphasis added).
`Consistent with Patent Owner’s reading of this statement, we also
`understand the repeated “MP2” to be a typographical error that should be
`read as “MP1.” See, e.g., Prelim. Resp. 24–25 (“Toshiba excludes from its
`mapping . . . the output driver consisting of transistors MP1, MP2, MN1,
`and MN2 of Yen’s Figure 4 circuit.”) (citing Pet. 21, 23).
`
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`Patent Owner argues that Petitioners’ mapping of the output buffer
`circuits is inconsistent with the mapping for the “combined output drive
`strength.” Prelim. Resp. 22–30. In particular, Patent Owner argues that the
`recited drive strength must be tuned by signals that are “customized across
`the plurality of output buffers.” Id. at 29. Here, Patent Owner contends
`“customized across” means “individually enable or disable each of.”
`Id. at 24. Patent Owner notes that, unlike the claimed buffers, Yen’s buffer
`circuit comprising MP1, MP2, MN1, and MN2 (Yen’s Figure 4) or output
`driver 42 (Yen’s Figure 3) does not receive the customized signal. Id. at 29–
`30. In Patent Owner’s view, Yen discloses additional drivers that always
`contribute to the drive strength. Id. at 26. Thus, Patent Owner concludes
`that Yen’s additional drivers are not individually enabled or disabled by a
`customized signal, as required. Id. at 29–30.
`Patent Owner illustrates this point by annotating Yen’s Figure 3,
`which is reproduced below. Id.
`
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`
`Yen’s Figure 3 is shown above with Patent Owner’s annotations. Id. at 26.
`In the annotated figure, Patent Owner shows that driver 42 does not receive
`a buffer enable signal (OS1, OS2, or OS3). Id.
`We, however, are persuaded that Petitioners have demonstrated a
`reasonable likelihood of prevailing on the assertion that Yen’s configuration
`is covered by the claim. Even if the customized-across limitation requires
`that the system “individually enable or disable each of” the recited output
`buffer circuits (Prelim. Resp. 24), Petitioners do not consider the additional
`driver (e.g., Yen’s driver 42) to be one of the recited output buffer circuits.
`Pet. 24. Moreover, we see nothing in the current record that limits the claim
`such that any additional, unrecited drivers must also be enabled or disabled.
`Rather, claim 1 only recites that the signals are “customized across the
`plurality of output buffers”—e.g., the set of buffers excluding Yen’s
`
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`additional drivers, under Petitioners’ mapping. See Ex. 1001, 9:46–47
`(emphasis added); Pet. 24, 37–38.
`Given this understanding of the claim and the provided mapping,
`Petitioners have shown, sufficiently at this stage, that Yen discloses the
`recited inputs and outputs.
`
`III
`Independent claim 1 further recites, in part, that the “buffer enable
`signals and the complements of the buffer enable signals control pairs of
`transistors having opposite conductivity types, and the buffer enable signals
`include the first buffer enable signal and the second buffer enable signal.”
`Ex. 1001, 9:57–62; see also id. at 11:67–12:3, 12:60–65 (reciting similar
`limitations in claims 11 and 18).
`Petitioners explain that Yen’s output enable (OUTPUT ENABLE) and
`control bit (OS1 and OS2) signals correspond to the recited first and second
`buffer enable signals, respectively. Pet. 29–30 (citing Ex. 1005 ¶¶ 65–67),
`Pet. 32–33 (citing Ex. 1005 ¶¶ 68–70). According to Petitioners, Yen’s
`output enable signal is “shared across” the output buffers, like the recited
`first buffer enable signal, and Yen’s control bit signals are “customized
`across” the output buffers, like the recited second buffer enable signal.
`Pet. 30 (citing Ex. 1005 ¶¶ 65–67). Petitioners’ annotated version of Yen’s
`Figure 4 is shown below.
`
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`
`Yen’s Figure 4 is shown above with Petitioners’ annotations. Pet. 33.
`Petitioners annotate Yen’s Figure 4 by highlighting the second buffer
`enable signals and their complements in purple and green. Id. That is,
`
`Petitioners explain that signals OS1, OS1�����, OS2, and OS2����� individually enable
`
`their respective buffers. Id. Likewise, Petitioners assert that Figure 3 also
`shows the first buffer enable signal (OUTPUT ENABLE) and second buffer
`enable signals (OS1, OS2, and OS3). Id. at 29–32.
`Patent Owner points out that independent claims 1, 11, and 18 recite
`that the “buffer enable signals and the complements of the buffer enable
`signals control pairs of transistors having opposite conductivity types.”
`Prelim. Resp. 15 (citing Ex. 1001, 9:57–60, 11:67–12:3, 12:59–62)
`(emphasis in original). In Patent Owner’s view, this limitation requires that
`“each buffer-enable signal pair ([i.e.], a buffer enable signal and its
`complement signal) controls pairs (i.e., more than one pair) of transistors,”
`unlike Yen’s single-pair control. Prelim. Resp. 15–16. For example, Patent
`
`16
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`Owner annotates Figure 2 of the ’417 patent to illustrate this feature, which
`is reproduced below. Id. at 17.
`
`
`Figure 2 of the ’417 patent is shown above with Patent Owner’s annotations.
`Id.
`Patent Owner explains that Z and ZB—the signal and its complement—
`control more than just one pair of transistors. Id. at 17–18. Rather, Z and
`ZB influence the bias voltages at the gates of transistors 202 and 204
`through the pair formed by transistors 210 and 212 and another pair formed
`by transistors 214 and 216. Id. (citing Ex. 1001, 7:5–10).
`Patent Owner points out that Petitioners only show that Yen’s OS1
`
`and OS1����� control one pair of transistors (MN4 and MP4), and OS2 and OS2�����
`
`control another (MN6 and MP6). Prelim. Resp. 21 (citing Pet. 39–40,
`Ex. 1005 ¶¶ 80–84).
`Patent Owner’s arguments are not persuasive at this preliminary stage
`and on the current record. See Prelim. Resp. 15–22. In particular, we are
`not persuaded that the claim requires that each buffer-enable signal pair
`
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`controls more than one pair of transistors. Id. at 15–16. In the claims, the
`word “each” does not modify the recited signal pair. See Ex. 1001, 9:57–62,
`11:67–12:3, 12:60–65. Rather, the buffer enable signals and the
`complements are recited as the compound subject for the word “control.”
`See id. Thus, Patent Owner has not shown, sufficiently, how the language
`limits the claim to “each” pair. Prelim. Resp. 15–16.
`On the current record, Petitioners have shown a reasonable likelihood
`of prevailing on the interpretation that the last wherein clause covers signal
`pairs that collectively, rather than individually, control the recited transistor
`pairs. See Pet. 39–40. In other words, Petitioners’ position requires that,
`although each signal and its complement control only a single transistor pair
`(instead of more than one pair), other signal-complement pairs control other
`transistor pairs. See id. Although Petitioners have sufficiently shown a
`reasonable likelihood of prevailing in this regard, we encourage the parties
`to address this issue in their post-institution briefing.
`We conclude that, based on the current record, Petitioners have
`demonstrated a reasonable likelihood of prevailing on their challenges to
`independent claims 1, 11, and 18 as anticipated by Yen.
`We have also reviewed Petitioners’ analysis of dependent claims 2–7
`and 12–16 at pages 40–51 of their Petition. We conclude that, based on the
`current record, Petitioners also have demonstrated a reasonable likelihood of
`prevailing on their challenges of those claims as anticipated by Yen.
`
`
`D. Obviousness
`Petitioners assert that claims 1–7, 11–16, and 18 (all challenged
`claims) are unpatentable under 35 U.S.C. § 103 as obvious in view of Yen
`
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`and Jain. Pet. 53–59. Petitioners base their obviousness rationale on the
`understanding that the claims are not open ended. See id. at 54. Under this
`interpretation, Petitioners assume that the claims exclude any additional
`output buffer circuits beyond those recited, such as Yen’s additional driver
`42 in Figure 3. Id. Petitioners then rely on Jain to modify Yen. Id. at 54–
`57. Apart from interpreting the claims in this way, Petitioners present the
`same mapping to Yen as in their anticipation analysis. See id. at 58–59
`(referring to Pet. §§ VIII.B.1.c–i).
`For the reasons discussed in connection with the anticipation grounds,
`Petitioners, on this record, provide sufficient evidence that Yen teaches the
`limitations for which it is relied upon in the proposed combination. See
`Pet. 53–59. We are not persuaded by Patent Owner’s arguments regarding
`Petitioners’ sole reliance on Yen’s Figure 3. Prelim. Resp. 31–33. Patent
`Owner’s arguments regarding the deficiencies in Yen’s Figure 3 are based
`on the reasoning that we addressed above. See id. Specifically, Patent
`Owner argues that Yen’s Figure 3 and 4 show separate embodiments, and
`Yen’s Figure 3 lacks complements of the buffer enable signals. Id. at 32
`(citing Prelim. Resp. § IV.A.1.) But at this stage, Petitioners have shown,
`sufficiently, that Yen’s Figures 3 and 4 describe the same embodiment for
`the above-discussed reasons.
`For the reasons discussed below, Petitioners have also shown a
`reasonable likelihood of prevailing on the obviousness ground of
`unpatentability over Yen as modified by Jain.
`1. Overview of Jain
`Jain teaches an output buffer for driving AC-coupled, resistively
`terminated transmission lines. Ex. 1004 ¶ 22. Jain’s output buffer has at
`
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`least two drive circuits. Id. ¶ 23. Each drive circuit is coupled to an input
`signal and provides a drive signal that is responsive to the input signal’s
`transitions. Id. Jain sums the drive signals to provide the buffer’s output
`signal. Id.
`
`2. Analysis
`Unlike in the anticipation-based challenge, Petitioners interpret the
`claims to exclude Yen’s driver 42 in the obviousness-based challenge.
`Pet. 56–57. To remedy Yen’s deficiencies under this interpretation,
`Petitioners assert that Jain teaches buffer enable signals that are spread and
`customized across all buffers. Id. at 55–56 (quoting Ex. 1004 ¶ 39).
`According to Petitioners, Jain teaches multiple output buffer circuits coupled
`in parallel to provide a combined output strength. Pet. at 54 (quoting
`Ex. 1004 ¶¶ 38, 39). Petitioners annotate Jain’s Figure 6 to highlight the
`output buffer circuits. Pet. 55. We reproduce annotated Figure 6 below.
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`Patent 8,035,417 B1
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`
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`Figure 6 of Jain is shown above with Petitioners’ annotations. Id.
`As shown above, Petitioners explain that Jain spreads the OUTPUT
`ENABLE signal across all output buffer circuits. Id. Likewise, according to
`Petitioners, Jain customizes control signals ADD0, ADD1 through ADDX
`across all output buffer circuits. Id.
`Petitioners conclude that it would have been obvious to modify Yen to
`remove output driver 42 so that the buffer enable signals are shared and
`customized across all buffers as taught by Jain. Id. at 56–57 (citing
`Ex. 1005 ¶¶ 118–124). Petitioners articulate several rationales for this
`modification. Pet. 57 (citing Ex. 1005 ¶ 124). Specifically, Petitioners
`explain that the modification leads to increased flexibility because
`independently controlling the output buffers allows any single circuit to be
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`Patent 8,035,417 B1
`used by itself. Pet. 57 (citing Ex. 1005 ¶ 124). Petitioners explain that
`doing so is useful if the driver-output strengths are different, among other
`reasons. Pet. 57 (citing Ex. 1005 ¶ 124). According to Petitioners, one of
`ordinary skill in the art would view the proposed modification as a design
`choice based on the similarities of Yen and Jain. Pet. 57
`(citing Ex. 1005 ¶ 124). Lastly, Petitioners note that the Yen-Jain
`combination would yield predictable results: independently operable
`circuits producing a combined output drive strength that is more easily
`tunable. Pet. 57 (citing Ex. 1005 ¶ 124).
`Patent Owner argues that Yen teaches away from the proposed
`combination. Prelim. Resp. 33–36. “A reference that ‘merely expresses a
`general preference for an alternative invention but does not criticize,
`discredit, or otherwise discourage investigation into’ the claimed invention
`does not teach away.” Meiresonne v. Google, Inc., 849 F.3d 1379, 1382
`(Fed. Cir. 2017) (quoting Galderma Labs., L.P. v. Tolmar, Inc., 737 F.3d
`731, 738 (Fed. Cir. 2013)). Here, although Patent Owner has explained that
`Yen’s output driver 42 always contributes to the output data value, Patent
`Owner has not identified where Yen criticizes, discredits, or otherwise
`discourages investigation into alternatives that do not rely on this driver. See
`Prelim. Resp. 33–36. Therefore, on the current record, we are unpersuaded
`by Patent Owner’s teaching-away argument. See id.
`Patent Owner also characterizes Yen’s driver 42 as “an essential
`component.” Id. at 35. Thus, Patent Owner reasons that removing this
`driver would “change the core operation” and modifying Yen in this way is
`hindsight reconstruction. Id. at 35–36. In Patent Owner’s view, removing
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`Patent 8,035,417 B1
`driver 42 is unnecessary because Yen’s buffer can already provide a floating
`value. Id. at 36–37.
`Petitioners, however, identify the similarities between Yen’s and
`Jain’s circuit configuration and operating principles. Pet. 56 (citing
`Ex. 1005 ¶ 124). Petitioners explain how the references both provide a
`combined output drive strength. Pet. 57. Petitioners then explain how the
`proposed modification enhances the flexibility this feature by allowing the
`selection of any single buffer. Id. In fact, Petitioners support their reasoning
`by citing a specific aspect of Yen’s operation that would be enhanced by the
`modification—i.e., when the driver output strengths are weighted. Id. (citing
`Ex. 1003, 5:55–66). On the current record, we are unconvinced that
`Petitioners’ proposed modification would “change the core operation” or
`would be unnecessary, as argued (Prelim. Resp. 36–37).
`Although Petitioners conclude that the proposed modification would
`allow the combined output drive strength to be “more easily tunable”
`(Pet. 57 (citing Ex. 1005 ¶ 124)), Patent Owner argues that Petitioners have
`not established what it means to be more easily tunable. Prelim. Resp. 39.
`In Patent Owner’s view, Yen already has significant and customizable
`tuning capabilities. Id. Furthermore, Patent Owner contends that the Strader
`design-choice testimony is conclusory. Id. at 37.
`At this stage, however, Petitioners have shown sufficiently that Yen’s
`customizable tuning capabilities would be enhanced to some degree. Pet. 57
`(citing Ex. 1005 ¶ 124). Petitioners’ conclusion that this further
`enhancement would have been obvious is not undermined by Yen’s
`discussion of adding resolution in different ways. See Ex. 1003, 5:41–66,
`discussed in Prelim. Resp. 38–39. Rather, Yen teaches that the strengths can
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`be arranged in “any number of ways,” which is similar to Petitioner’s
`rationale of providing operational flexibility. Compare Ex. 1003, 5:41–66
`with Pet. 57 (discussing using a single buffer itself or in combination with
`others) (citing Ex. 1003, 5:55–66, Ex. 1005 ¶ 124).
`Patent Owner further contends that Jain does not teach or suggest
`removing an output driver from a buffer circuit. Prelim. Resp. 36. But “[a]
`suggestion, teaching, or motivation to combine the relevant prior art
`teachings does not have to be found explicitly in the prior art . . . .” In re
`Kahn, 441 F.3d 977, 987–88 (Fed. Cir. 2006). Here, Petitioners explain, in
`sufficient detail, what a person of ordinary skill would have understood from
`Jain’s teachings and why they would have applied that knowledge to the
`invention described by Yen, as we discussed above. See Pet. 54–57 (citing
`Ex. 1005 ¶¶ 118–124). Therefore, we are persuaded that Petitioners’
`rationale is sufficient for purposes of institution.
`We conclude that Petitioners have demonstrated a reasonable
`likelihood of prevailing on their challenges to independent claims 1, 11, and
`18 as obvious over Yen and Jain. See Pet. 54–57 (citing Ex. 1005 ¶¶ 118–
`124), 62–64 (citing Ex. 1005 ¶¶ 138–143), 67–68 (citing Ex. 1005 ¶¶ 149–
`154).
`
`We have also reviewed Petitioners’ analysis of dependent claims 2–7
`and 12–16 at pages 59–62 and 64–66 of their Petition. We conclude that
`Petitioners also have demonstrated a reasonable likelihood of prevailing on
`their challenges of those claims as well.
`
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`E. Unconstitutionality of Inter Partes Reviews
`Patent Owner argues that inter partes reviews
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