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` Entered: September 7, 2018
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`Trials@uspto.gov
`571-272-7822
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`VIZIO, INC.,
`Petitioner,
`v.
`BROADCOM CORPORATION,
`Patent Owner.
`____________
`
`Case IPR2018-00786
`Patent 7,590,059 B2
`____________
`
`
`
`
`
`
`Before JEAN R. HOMERE, RAMA S. ELLURU, and
`DANIEL J. GALLIGAN, Administrative Patent Judges.
`
`HOMERE, Administrative Patent Judge.
`
`
`
`
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
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`IPR2018-00786
`Patent 7,590,059 B2
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`
`INTRODUCTION
`I.
`Vizio Inc. (“Petitioner”) filed a Petition requesting inter partes review
`of claims 11–20 (“the challenged claims”) of U.S. Patent No. 7,590,059 B2
`(Ex. 1001, “the ’059 patent”). Paper 1 (“Pet.”). Broadcom Corporation
`(“Patent Owner”) filed a Preliminary Response. Paper 6 (“Prelim. Resp.”).
`Pursuant to 37 C.F.R. § 42.4(a), we have the authority to determine whether
`to institute review.
`Under 35 U.S.C. § 314(a), an inter partes review may not be instituted
`unless the information presented in the petition and the preliminary response
`“shows that there is a reasonable likelihood that the petitioner would prevail
`with respect to at least 1 of the claims challenged in the petition.” For the
`reasons that follow, we determine that, on this record, Petitioner has
`established a reasonable likelihood that it would prevail with respect to the
`challenged claims. Accordingly, we institute an inter partes review as to the
`challenged claims.
`
`A. Related Matters
`Petitioner indicates that the ’059 patent is involved in Broadcom Corp
`v. VIZIO, Inc., Civil Action No. 8:17-cv-00408 (C.D. Cal.) and In re Certain
`Semiconductor Devices and Consumer Audiovisual Products Containing the
`Same, Investigation No. 337-TA-1047 (USITC). Pet. 1. Petitioner further
`indicates that the ’059 patent is also involved in certain other matters. Id. at
`1–2.
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`B. The ’059 Patent
`The ’059 patent relates to multi-standard video decoder chip 300 for
`selecting a suitable decoding process based on an identified one of a
`plurality of encoding types associated with packets separated by delimiters
`within a received encoded video stream. Ex. 1001, 2:38–51, Fig. 3A.
`Specifically, as depicted in Figure 3A below, the ’059 patent discloses
`decoder chip 300 includes memory block 301 for storing elementary video
`stream 309 from which code-in-port (CIP- 305) acquires a start code,
`which stream parser 307 processes and forwards to processing block 303 to
`generate information necessary for subsequent decoding of the video stream.
`Id. at col. 6:9–52.
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`Figure 3A depicts a block diagram of the multi-standard video decoder.
`More particularly, as illustrated in Figure 1 below, the ’059 patent
`discloses that the encapsulated payload within each received packet 100
`includes elementary video stream data 105, and delimiter 104. Id. at 5:4–33.
`Delimiter 104 contains start code 101 indicating the beginning of the packet,
`and start code suffix 103, which may indicate the particular encoding
`standard (e.g., MPEG-1, MPEG-2, MPEG-4H.264, VC-1) associated with
`the packet. Id.
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`Figure 1 depicts the block diagram of encapsulated video payload 100 with a
`delimiter.
`According to an embodiment of the ’059 patent all the steps in the
`decoding process shown in Figure 9 below are performed by a processor on
`the chip. Id. at 3:13–25. In particular, upon receiving the packetized data on
`the chip, the processor examines delimiter 104 to identify start code 101 as
`well as identifier 103 so as to identify one or more encoding types associated
`with packets in the video stream. Id. at 18:29–44, Fig. 9. The processor
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`subsequently selects a suitable one of a plurality of decoding processes
`based on the identified encoding process to decode the packetized data. Id.
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`Figure 9 depicts a method for decoding an encoded video stream.
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`C. Illustrative Claim
`Of the challenged claims, claim 11 is independent. Claims 12–20
`depend indirectly from independent claim 11. Claim 11 is illustrative and is
`reproduced below with disputed limitations emphasized:
`11. A computer-readable storage having stored thereon, a
`computer program having at least one code section for
`processing an encoded video stream, the at least one code section
`being executable by a machine to perform steps comprising:
`
`receiving on a chip, packetized data within the encoded
`video stream;
`determining on said chip, an identifier within said received
`packetized data that defines one of a plurality of encoding types
`associated with packets in the encoded video stream;
`selecting on said chip, a decoding process from a plurality
`of decoding processes based on said determined identifier;
`and decoding on said chip, at least a portion of said
`received packetized data in the encoded video stream utilizing
`said selected decoding process.
`
`Ex. 1001, 20:15–31 (emphases added).
`
`D. Asserted Grounds of Unpatentability1
`Petitioner asserts that claims 11–20 are unpatentable based on the
`
`
`1 Because the claims at issue have a filing date prior to the effective dates of
`the amendments to 35 U.S.C. §§ 102, 103, and 112 made by the Leahy-
`Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284 (2011)
`(“AIA”), we apply the pre-AIA version of 35 U.S.C. §§ 102, 103, and 112 in
`this Decision.
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`following grounds (Pet. 5–6):
`Reference(s)
`Chu2 and POSITA3
`Chu, POSITA and Watkinson4
`Chu, POSITA and Richardson5
`Chu, POSITA and APA6
`Kovacevic7 and POSITA
`Kovacevic, POSITA and Watkinson
`Kovacevic, POSITA and Richardson
`Kovacevic and APA
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`Basis
`§ 103(a)
`§ 103(a)
`§ 103(a)
`§ 103(a)
`§ 103(a)
`§ 103(a)
`§ 103(a)
`§ 103(a)
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`Challenged Claim(s)
`11, 12, and 19
`13, 14, 17, and 18
`15, and 20
`16
`11, 12, and 19
`13, 14, 17, and 18
`15 and 20
`16
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`2 US 7,167,108 B2, filed Nov. 26, 2003, issued Jan. 23, 2007 (Ex. 1009)
`(“Chu”).
`3 Knowledge of POSITA.
`4 Watkinson, The MPEG Handbook, (“Watkinson”) (Ex. 1007), published
`by Focal Press in 2001.
`5 Richardson, H.264 and MPEG-4 Video Compression: Video Coding for
`Next-generation Multimedia, (“Richardson”) (Ex. 1029), published by John
`Wiley & Sons, Ltd. in 2003.
`6 Admitted Prior Art in the ’059 Paten,t including the MPEG-2, VC-1, and
`H.264 video encoding standards. Ex. 1001, 2:15–24.
`7 U.S. Patent Publication No. 2005/0060420 A1 to Branko Kovacevic
`(“Kovacevic”) (Ex. 1004), filed September 11, 2003 and published March
`17, 2005.
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`II. DISCUSSION
`A. Claim Construction
`In an inter partes review, a claim in an unexpired patent shall be given
`its broadest reasonable construction in light of the specification of the patent
`in which it appears. 37 C.F.R. § 42.100(b). Under the broadest reasonable
`construction standard, claim terms are given their ordinary and customary
`meaning, as would be understood by one of ordinary skill in the art in the
`context of the entire disclosure. In re Translogic Tech., Inc., 504 F.3d 1249,
`1257 (Fed. Cir. 2007). Cuozzo Speed Techs. LLC v. Lee, 136 S. Ct. 2131,
`2142–46 (2016). Only terms that are in controversy need to be construed,
`and then only to the extent necessary to resolve the controversy. Vivid
`Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
`Neither Petitioner nor Patent Owner proposes an explicit construction
`for any terms of the challenged claims. Pet. 11–12; Prelim Resp. 4–5.
`Accordingly, Petitioner and Patent Owner submit that all terms in the
`challenged claims be construed according to their broadest reasonable
`interpretation. Pet. 11–12; Prelim Resp. 4–5. Because neither party proffers
`a construction of, or otherwise disputes the meaning of, any of the claim
`terms, we determine, at this juncture of the proceeding, that it is not
`necessary to provide any express interpretation of the claim terms.
`
`B. Level of Ordinary Skill in the Art
`In determining the level of ordinary skill in the art, various factors
`may be considered, including the “type of problems encountered in the art;
`prior art solutions to those problems; rapidity with which innovations are
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`made; sophistication of the technology; and educational level of active
`workers in the field.” In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995)
`(internal quotation and citation omitted). In that regard, Petitioner’s
`Declarant, Robert Stevenson, Ph.D., testifies that a person of ordinary skill
`in the art (POSITA) at the time of the invention “would have Master’s
`degree in Computer Science, Computer Engineering, or Electrical
`Engineering, with at least two to three years of experience in development
`and programming related to video digital signal processing. More work
`experience could substitute for education, and vice versa. The POSITA
`would have been familiar with very-large-scale-integration (‘VLSI’)
`technologies and system-on-chip (‘SoC’) design.” Ex. 1002 ¶ 42. Patent
`Owner does not proffer a suggested level for the ordinarily skilled artisan.
`On this record, we observe that Petitioner’s proffered undisputed
`assessment of a person of ordinary skill in the art appears to be consistent
`with the level of ordinary skill in the art at the time of the invention as
`reflected in the prior art in the instant proceeding. See Okajima v. Bourdeau,
`261 F.3d 1350, 1355 (Fed. Cir. 2001). Therefore, for purposes of this
`Decision, we adopt Petitioner’s assessment.
`C. Principles of Law
`A patent claim is unpatentable under 35 U.S.C. § 103(a) if the
`differences between the claimed subject matter and the prior art are such that
`the subject matter, as a whole, would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said
`subject matter pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
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`(2007). The question of obviousness is resolved on the basis of underlying
`factual determinations including: (1) the scope and content of the prior art;
`(2) any differences between the claimed subject matter and the prior art; (3)
`the level of ordinary skill in the art; and (4) any secondary considerations, if
`in evidence. Graham v. John Deere Co., 383 U.S. 1, 17– 18 (1966).
`
`D. Obviousness over Chu and POSITA
`Petitioner asserts that claims 11, 12 and 19 are unpatentable under 35
`U.S.C. § 103(a) as obvious over Chu and POSITA. Pet. 17–27. Patent
`Owner opposes. Prelim. Resp. 6–9.
`Based on the evidence in this record, we determine that Petitioner has
`established that there is reasonable likelihood that Petitioner would prevail
`with respect to this ground of unpatentability. In our discussion below, we
`address the parties’ contentions in turn.
`
`Overview of Chu (Ex. 1009)
`
`Chu describes a method and system for switching between a plurality
`of decoders, each decoder adapted to a decode bit stream having a unique
`format so as to select a suitable decoder based on the detected format of a
`received data stream/bitstream. Ex. 1009, 1:47–56. In particular, as
`depicted in Figure 3 below of Chu, format detector 320 examines received
`data stream 310 including a start code, packet header, and content to
`determine the compression/encoding type of the video in the formatted data
`stream so as to select a decoder (340, 342, 344) suitable to decode the
`identified format. Id. at 2:36–67, 6:32–37.
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`Figure 3 shows apparatus 300 using a format indicator contained in received
`formatted data stream 310 to select a suitable detector to detect the data.
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`Analysis
`
`Petitioner provides explanations to account for all of the claim
`limitations required by claims 11, 12 and 19, citing Dr. Stevenson’s
`Declaration for support. Pet. 17–27; Ex. 1002.
`Claim 11 – Petitioner’s contentions
`The preamble of independent claim 11 recites “[a] computer-readable
`storage having stored thereon, a computer program having at least one code
`section for processing an encoded video stream, the at least one code section
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`being executable by a machine to perform” the steps recited in the claim.
`Ex. 1001, 20:15–18. Petitioner relies upon Chu’s disclosure of an
`“apparatus” for processing a formatted data stream as teaching “a computer
`program … for processing an encoded video stream.” Pet. 17–18 (citing Ex.
`1009, 1:17–33, 2:36–37, 4:29–31; Ex. 1002 ¶¶ 68–69). In particular,
`Petitioner relies upon Chu’s disclosure that “[f]ormat detectors 320 [of
`apparatus 300] include hardware and/or software to instantiate process
`steps” and that the process of apparatus 300 can be implemented in software
`for teaching the “one code section for processing” the encoded video stream.
`Id. (quoting Ex. 1009, 6:31–34; citing Ex. 1009, 4:29–39; Ex. 1002 ¶ 70).
`Further, Petitioner submits that “a POSITA would have understood that
`Apparatus 300 can comprise a processor (i.e., the claimed “machine”) to
`execute the disclosed Software (executable by a machine).” Id. at 18 (citing
`Ex. 1009, 6:28–34; Ex. 1002 ¶ 70). Additionally, Petitioner submits that,
`although Chu does not explicitly disclose a memory for storing the disclosed
`software, it would have been obvious to a POSITA to store the Software in
`the claimed computer readable storage for execution by the Apparatus
`because such a storage is a widely known practice, and a POSITA would
`thereby have had a reasonable expectation of implementing such storage in
`Chu. Id.
`Independent claim 11 further recites “receiving on a chip, packetized
`data within the encoded video stream.” Ex. 1001, 20:19–20. Petitioner
`relies upon Chu’s disclosure of apparatus 300 receiving packetized data as
`teaching the claimed “receiving on a chip” limitation. Pet. 19 (citing
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`Ex. 1002, ¶ 74). Petitioner then contends that “a POSITA would have
`understood that Apparatus 300 could be implanted (sic) as the claimed
`‘chip.’” Id. (citing Ex. 1002 ¶ 74). Petitioner also relies upon Chu’s
`disclosure that apparatus 300 receives formatted data stream 310 to teach the
`claimed “encoded video stream” of video data encoded according to one of
`several MPEG standards, which is “arranged in frames.” Id. (citing Ex.
`1002 ¶¶ 74–76; Ex. 1009, 1:17–33, 2:36–43, 4:29–31, 6:28–34, Fig. 3).
`Further, Petitioner contends that a POSITA would have understood the video
`data encapsulated in a frame to be the claimed “received packetized data.”
`Id. (citing Ex. 1002, ¶ 74, Ex. 1009 2:36–43).
`Independent claim 11 further recites “determining on said chip, an
`identifier within said received packetized data that defines one of a plurality
`of encoding types associated with packets in the encoded video stream.”
`Ex. 1001, 20:21–24. Petitioner contends Chu discloses format detectors 320
`detecting format indicators including start codes within the frames of
`formatted data stream 310 to teach the claimed “determining.” Pet. 20
`(citing Ex. 1009, 2:43–58, 4:29–33, 6:28–34, and Fig. 3; Ex. 1002 ¶¶ 79,
`81). Further, Petitioner relies upon Chu’s disclosure of headers and code
`words to teach the claimed “identifier within said received packetized data”
`including the claimed data that “defines one of a plurality of encoding types
`associated with packets in the encoded video stream.” Id. at 21 (citing Ex.
`1009, Abstract, 1:59–65, 1:49–51, 2:2–4, 2:36–43, 2:54–57, 6:34–38, 7:63–
`65, 10:12–15, 10:24–28; Ex. 1002 ¶¶ 69, 79–81). Additionally, Petitioner
`relies upon Chu’s disclosure of unique decoder 340, 342, or 344 being
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`selected based on the encoding format identified by the format indicators to
`teach the claimed “determining.” Id. at 21–22 (citing Ex. 1009, Abstract,
`1:17–22, 1:47–65; 2:39–50; 3:20–23; 3:29–33; 6:34–36; Ex. 1002 ¶ 81).
`
`Independent claim 11 further recites “selecting on said chip, a
`decoding process from a plurality of decoding processes based on said
`determined identifier.” Ex. 1001, 20:25–27. Petitioner reiterates its
`contention that Chu’s disclosure of the format indicator teaches the claimed
`“identifier” contained in formatted data stream 310 corresponding to a
`particular data compression format and a particular decoder (e.g., 340, 342,
`or 344). Pet. 22. Petitioner further asserts Chu discloses that “Logic 360
`identifies the compression format corresponding to the detected Format
`Indicator and selects the appropriate decoding process” and, therefore,
`teaches the claimed “selecting . . . a decoding process from a plurality of
`decoding processes based on said determined identifier.” Id. at 22–23
`(citing Ex. 1002 ¶¶ 85, 87; Ex. 1009, 6:29–41, Fig. 3). According to
`Petitioner, “[a]fter selecting the appropriate decoding process, Chu’s Switch
`330 transmits formatted data stream 310 to one of the decoders (e.g., 340,
`342, or 344) that is associated with the detected format indicator.” Id.
`(citing Ex. 1009, 2:60–66, 6:39–41, Fig. 3; Ex. 1002 ¶¶ 87–88).
`Additionally, independent claim 11 recites “decoding on said chip, at
`least a portion of said received packetized data in the encoded video stream
`utilizing said selected decoding process.” Ex. 1001, 20:28–31. Petitioner
`relies upon Chu’s disclosure of apparatus 300 selecting an appropriate one of
`decoders 340, 342, or 344 corresponding to the compression format
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`identified by the format indicator within the received data to teach the
`claimed “at least a portion of said received packetized data in the encoded
`video stream”). Pet. 24 (citing Ex. 1009, Abstract, 1:47–49, 6:43–45;
`Ex. 1002 ¶ 91. Petitioner further relies upon Chu’s disclosure of the selected
`decoder 340, 342, or 344 producing decoded data 350, 352, or 354 to teach
`the claimed “decoding . . . utilizing said selected decoding process.” Id. at
`24 (citing Ex. 1009, 6:43–45, Fig. 3).
`
`Performing a series of decoding steps on a chip
`
`Patent Owner argues that Chu does not teach performing on a chip
`any of the four steps recited in independent claim 11. Prelim. Resp. 6. In
`particular, Patent Owner asserts that, although Petitioner acknowledges that
`Chu does not disclose a chip, Petitioner relies upon conclusory testimony
`from Dr. Stevenson to contend that Chu’s apparatus 300 could be
`implemented on a chip. Id. at 7. Accordingly, Patent Owner asserts that
`Petitioner fails to establish a reasonable likelihood that Petitioner will
`prevail on at least one of the challenged claims. Id. In particular, Patent
`Owner argues that Chu discloses a “seamless agile decoder apparatus,”
`which is not a chip, and that Petitioner’s assertion that “a POSITA would
`have understood Apparatus 300 could be implemented as the claimed
`‘chip’” is not only flawed under the laws of obviousness, but it is also
`unsupported and should be given no weight. Id. at 8 (quoting Pet. 19; citing
`InTouch Techs Inc. v VGO Commc’ns, Inc., 751 F.3d 1327, 1352 (2014)).
`Likewise, Patent Owner qualifies as being conclusory, and without merit,
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`Dr. Stevenson’s statement that a POSITA would have understood the term
`chip to encompass a semiconductor material, and that Chu’s processor
`would have been made of semiconductor material. Id.
`We disagree with Patent Owner’s contentions. Rather, we find
`persuasive Petitioner’s contentions, as corroborated by Dr. Stevenson’s
`testimony, that a POSITA would have been able to implement on a chip
`apparatus 300 disclosed in Chu so as to perform on the chip the undisputed
`steps taught by Chu’s apparatus. Pet. 17–19 (citing Ex. 1102 ¶¶ 70–71). In
`particular, Chu expressly discloses implementing the apparatus in software,
`hardware or both. Ex. 1009, 4:29–31 (“The process 100, like the processes
`described below, may be implemented in hardware, software, firmware, or
`hybrids thereof.”). We agree with Petitioner that a POSITA would have
`appreciated that the disclosed apparatus embodied in software or hardware
`would have utilized a semiconductor processor to execute the disclosed
`steps. Id. at 19 (citing Ex. 1002 ¶ 76, Ex. 1009, 6:28–34). This is supported
`by Dr. Stevenson’s testimony, which states the following:
`A POSITA would have generally understood the plain and
`ordinary meaning of the term “chip” to include a semiconductor
`with an embedded integrated circuit. As discussed above, in
`Chu’s Software implemented embodiments, a POSITA would
`have also understood Apparatus 300 to include a processor to
`execute the Software. This processor would have been made of
`semiconductor material with
`integrated surrounding and
`embedded circuitry. Thus, a POSITA would have understood
`this to be a “chip” (i.e., a microchip).
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`Ex. 1002 ¶ 76 (citing Ex. 1009, 1:17–33, 2:36–43, 4:29–31, 6:28–34).
`Accordingly, the record before us supports Petitioner’s contention that a
`POSITA would have understood the disclosed apparatus to be implemented
`on a chip to perform the cited decoding steps.
`In light of the foregoing, we are persuaded that Petitioner has shown
`adequately for the purposes of this Decision that Chu’s teachings at least
`suggest performing the aforementioned series of steps on a chip as recited by
`claim 11.
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`Threshold determination as to claim 11
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`For purposes of this Decision, we find Petitioner’s arguments and
`evidence present a reasonable likelihood of prevailing on its assertion that
`the claim 11 would have been obvious over Chu and POSITA.
`
`Dependent claims 12 and 19
`
`We have reviewed Petitioner’s explanations and supporting evidence
`regarding claims 12 and 19, and find them persuasive. See Pet. 24–27.
`Patent Owner does not provide separate arguments for these claims. Based
`on the record before us, Petitioner has demonstrated a reasonable likelihood
`that it will prevail on its assertion that claims 12 and 19 would have been
`obvious over Chu and POSITA.
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`E. Obviousness over Chu, POSITA and Watkinson
`We have reviewed Petitioner’s explanations and evidence in support
`of its contentions that claims 13, 14, 17, and 18 would have been obvious
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`over the combined teachings of Chu and Watkinson, and we find them
`persuasive. See Pet. 27–33. Patent Owner does not provide separate
`arguments for these claims. Based on the record before us, Petitioner has
`demonstrated a reasonable likelihood that it will prevail on its assertion that
`claims 13, 14, 17, and 18 would have been obvious over the combination of
`Chu, POSITA, and Watkinson.
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`F. Obviousness over Chu, POSITA and Richardson
`We have reviewed Petitioner’s explanations and evidence in support
`of its contentions that claims 15 and 20 would have been obvious over the
`combined teachings of Chu, POSITA, and Richardson, and we find them
`persuasive. See Pet. 33–37. Patent Owner does not provide separate
`arguments for these claims. Based on the record before us, Petitioner has
`demonstrated a reasonable likelihood that it will prevail on its assertion that
`claims 15 and 20 would have been obvious over the combination of Chu,
`POSITA, and Richardson.
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`G. Obviousness over Chu, POSITA and Admitted Prior Art
`We have reviewed Petitioner’s explanations and evidence in support
`of its contention that claim 16 would have been obvious over the combined
`teachings of Chu, POSITA, and Admitted Prior Art, and we find them
`persuasive. See Pet. 37–39. Patent Owner does not provide separate
`arguments for claim 16. Based on the record before us, Petitioner has
`demonstrated a reasonable likelihood that it will prevail on its assertion that
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`claim 16 would have been obvious over the combination of Chu, POSITA,
`and Admitted Prior Art.
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`H. Obviousness over Kovacevic and POSITA
`Petitioner asserts that claims 11, 12 and 19 are unpatentable under 35
`U.S.C. § 103(a) as obvious over Kovacevic. Pet. 40–52. Patent Owner
`opposes. Prelim. Resp. 9–10.
`Based on the evidence in this record, we determine that Petitioner has
`established that there is reasonable likelihood that Petitioner would prevail
`with respect to this ground of unpatentability. In our discussion below, we
`address the parties’ contentions in turn.
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`Overview of Kovacevic (Ex. 1004)
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`Kovacevic describes a multi-standard decoder for decoding a multi-
`media stream having an unknown protocol, which is identified based on
`information contained in packets of the received bit stream. Ex. 1004 ¶ 24.
`As depicted in Figure 5 below, Kovacevic discloses multimedia system 100
`that compares the information stream of the unknown protocol with various
`known protocols, each corresponding to an identified one of a plurality of
`encoding types (e.g., MPEG-1, MPEG-2...) until a match is found. Id. ¶¶
`25–29. In particular, upon receiving the data stream from multimedia device
`110 or 117, microcode engine 131 within demultiplexor 130 processes
`microcode 136 associated with data packets received from the data stream
`until a proper protocol is identified. Id. ¶¶ 29, 65.
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`Figure 5 shows multimedia system (100) for processing multimedia data
`streams.
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`Analysis
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`Petitioner provides explanations to account for all of the claim
`limitations required by claims 11, 12 and 19, citing Dr. Stevenson’s
`Declaration for support. Pet. 40–54; Ex. 1002.
`Claim 11 – Petitioner’s contentions
`The preamble of independent claim 11 recites “[a] computer-readable
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`storage having stored thereon, a computer program having at least one code
`section for processing an encoded video stream, the at least one code section
`being executable by a machine to perform” the steps recited in the claim.
`Ex. 1001, 20:15–18. Petitioner relies upon Kovacevic’s disclosure of
`microprocessor 137 (i.e., the claimed “machine”) of transport stream
`demultiplexor 130 for executing microcode 136 (i.e., the claimed “one code
`section of the computer program”), which provides instructions for
`processing packets of received video data (the claimed “processing of
`encoded video stream”), to teach the preamble of claim 11. Pet. 40 (citing
`Ex. 1004 ¶ 29, Fig. 5; Ex. 1002 ¶¶ 156, 157). In particular, Petitioner asserts
`Kovacevic teaches that demultiplexor 130 identifies unknown protocols in
`multimedia streams and performs each of the claimed steps. Id. at 41 (citing
`Ex. 1004 ¶¶ 24, 29, 56, 60, Ex. 1002 ¶ 158). Further, Petitioner submits
`that, although Kovacevic does not explicitly disclose a memory for storing
`microcode 136, it would have been obvious to a POSITA to store microcode
`136 in the claimed computer readable storage for execution by
`microprocessor 137. Id. According to Petitioner, a POSITA would have
`had a reasonable expectation of implementing such a storage in Kovacevic
`because such a storage is a widely known practice for providing the
`microprocessor with fast and efficient access to execute the microcode. Id.
`at 42 (citing Ex. 1002 ¶¶ 159, 160).
`Independent claim 11 further recites “receiving on a chip, packetized
`data within the encoded video stream.” Ex. 1001, 20:19–20. Petitioner
`asserts Kovacevic discloses demultiplexor 130 receiving a program stream
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`including a packetized elementary stream (“PES”) and, therefore, teaches the
`claimed “receiving on a chip” limitation. Pet. 42–43 (citing Ex. 1002 ¶ 162;
`Ex. 1004 ¶¶ 2–6, 29, 60, 63). According to Petitioner, while Kovacevic does
`not explicitly state that the elements of multimedia system 100 are
`implemented as a chip, it would have been obvious to a POSITA that
`multimedia system 100, including its transport stream demultiplexor 130,
`could be implemented as a “chip” because it was well-known at the time of
`the ’059 Patent for a chip to include multiple processors such as
`microprocessor 137 and MIPS core processor 180. Id. at 43–44 (citing Ex.
`1002 ¶ 163). Petitioner further asserts that “a POSITA would have been
`motivated and [would have] had a reasonable likelihood of success
`implementing Multimedia System 100 as a chip, since increasing the number
`of processing elements on a chip was a long-standing goal of electronics
`manufacturers.” Id. at 44.
`Independent claim 11 further recites “determining on said chip, an
`identifier within said received packetized data that defines one of a plurality
`of encoding types associated with packets in the encoded video stream.”
`Ex. 1001, 20:21–24. Petitioner relies upon Kovacevic’s disclosure of
`examining a byte in the packet to see if it equal to a particular value
`(hexadecimal 0xFF), which indicates a particular encoding type, as teaching
`identifying a specific type of data compression from the plurality of
`encoding types in the received video stream. Pet. 45 (citing Ex. 1004 ¶ 60,
`63–66, and Fig. 11; Ex. 1002 ¶¶ 165, 166). Petitioner contends Kovacevic
`discloses that transport stream demultiplexor 130 uses the value of this
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`particular byte to determine whether a received PES packet is associated
`with MPEG-1 or MPEG-2 and, therefore, teaches the claimed determining
`whether an identifier within the received packet defines one of the encoding
`types. Id. at 45–46 (citing Ex. 1004 ¶¶ 61–64, and Fig. 11; Ex. 1002 ¶¶ 166,
`167).
`Independent claim 11 further recites “selecting on said chip, a
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`decoding process from a plurality of decoding processes based on said
`determined identifier.” Ex. 1001, 20:25–27. Petitioner relies upon
`Kovacevic’s disclosure of transport stream demultiplexor 130 using the
`determined value of the byte discussed above to identify one of a plurality of
`decoding processes to teach the claimed “selecting . . . a decoding process
`from a plurality of decoding processes based on said determined identifier”).
`Pet. 46–47 (citing Ex. 1002 ¶¶ 169–171; Ex. 1002 ¶¶ 62–65). Further,
`Petitioner asserts that a person of ordinary skill in the art “would have
`understood Kovacevic’s parsing of the header data of the Video PES
`packets, to be a claimed ‘decoding process’ because extracting information
`such as buffer size and scale data from the header data is vital to the
`presentation of the encoded video data.” Id. at 48 (citing Ex. 1002, ¶¶ 172–
`176).
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`Additionally, independent claim 11 recites “decoding on said chip, at
`least a portion of said received packetized data in the encoded video stream
`utilizing said selected decoding process.” Ex. 1001, 20:28–31. Petitioner
`relies upon Kovacevic’s disclosure of a downstream decoding device that
`decodes the video data portion of the encoded video stream to teach the
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`claimed “decoding . . . at least a portion of said received packetized data in
`the encoded video stream”). Pet. 49 (citing Ex. 1004 ¶¶ 4, 8, 24; Ex. 1002
`¶¶ 174–176). Further, Petitioner asserts that, “[w]hile Kovacevic does not
`explicitly disclose which element of Multimedia System 100 performs the
`functions of the Downstream Decoding Device, it would have been obvious
`to a POSITA to utilize MIPS Core Processor 180 . . . to perform the
`functions of the Downstream Decoding Device” because a person of
`ordinary skill in the art would have recognized that the MIPS core processor
`is a reduced instruction set computer (RISC) processor that is the most
`suitable component in multimedia system 100 to execute the decoding
`instructions. Id. at 49–50 (citing Ex. 1004 ¶¶ 62, 64, Ex. 1002 ¶¶ 177–179.
`Finally, Petitioner asserts that a person of ordinary skill in the art “would
`have found it obvious to store the code for implementing the Payload data
`decoding by the MIPS Processing Core 180 on the claimed ‘computer-
`readable storage’” so as to facilitate the fa
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