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`Portland, Oregon, USA
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`- August 27-29, 2007
`Computing Machinery
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` BOSTON spa
`ON LOW POWER EL oe? 7B
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`SRITISH LIBRARY
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`_ August 27-29, 2007
`Computing Machinery
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`Portland, Oregon, U
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`Association for
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`Advancing Computing as.a Science & Profession
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`Association for
`Computing Machinery
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`Advancing Computing as a Science & Profession
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`Copyright © 2007 by the Association for Computing Machinery, Inc. (ACM). Permission to make digital
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`R fo 10 My One
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`Table of Contents
`
`ISLPED 2007) Orcavibzetiin.cscsscecssssceseararcoremnennonnenermnevsinercenctnersieieaeneercenamnrevins xi
`Program Committee...seseeeecteensseecseussneseeetenseseceescusnnnpcstescesesransusucestssnnugenesserenaness xii
`Sponsors & SUPPOFterS...csccecssnesesenssensreietvneseininienstninietnnnsiiinvecenneseessneenenteeexv
`2006 Design Contest Winners....pinanessaceressancdessogenageneagenuseenecescecesenceeneeesrssnnunveecerecnnnuaseecencnvnaseseseaxvi
`
`Keynote
`e Nanotechnology for Low-Power and High-Speed Nanoelectronics Applications................... 1
`Robert Chau(Intel)
`
`Session 1: Emerging Device Technologies for Low Power
`Session Chair: Yehia Massoud (Rice University)
`Co-Chair: Chris Kim (University ofMinnesota)
`Compact.Modeling of Carbon Nanotube Transistor
`for Early Stage Process-Design Exploration...............6.,abebacsecoesssssensecscasstessescesssysqersesanseesssee
`Asha Balijepalli, Saurabh Sinha, Yu Cao (Arizona State University)
`
`A Fleating-Body Dynamic Supply Boosting Technique
`for Low-Voltage PD/SO] CMOS SRAM in Nanoscale ooo... cece ec esesecetenereeneseeseeeneaes
`Rajiv Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Williams, Ching-Te Chuang (28M)
`
`Low Power FPGA Design Using Hybrid CMOS-NEMS Approach...ceecceeenes
`Yu Zhou, Shijo Thekkel, Swarup Bhunia (Case Western Reserve University)
`
`suse 2
`
`avers.
`
`veopen 14
`
`Designand Analysis of Thin-BOX FD/SOI Devices
`for Low-Power and Stable SRAM in sub-50nm Technologies.:...0........ccccsccessecceecsereeccteceeseeeeees20
`Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang ([BM T.J. Watson Research Center}
`Clocking Structures and Power Analysis for Nanomagnet-Based Logic Devices.........
`M.T. Niemier,X. 8. Hu, M. Alam, G.-Bernstein, W. Porod, M. Putney, J.DeAngelis
`(University ofNotre Dame)
`
`auenies 26
`
`Session 2: Power-EfficientCMP Design
`Chair: Massimo Poricino(Politecnico di Torino)
`Co-chair: Qing Wu (State University ofNew York at Binghamton)
`
`Energy Efficient Near-threshold Ghip Multi-processingceceseeeeeeneettecee tren eens
`Bo Zhai, Ronald G. Dreslinski, DavidBlaauw, Trevor Mudge, Dennis Sylvester (University-of.Michigan)
`Analysis of Dynamic Voltage/Frequency Scaiing in Chip-Multiprocessors....
`Sebastian Herbert, Diana Marculescu (Carnegie Mellon University)
`Evaluating Design Tradeoffs in On-Chip Power Managementfor CMP...44
`Joseph Sharkey(Assured Information Security, Inc.),
`Alper Buyuktosunoglu, Pradip Bose (BM TJ. Watson Research Center)
`
`38
`
`re 32
`
`Impact. of Die-to-Die and Within-Die Parameter Variations
`on the ThroughputDistribution of Multi-Core. Processors... cess esssceeseedeeteseessecees
`Keith A. Bowman, Alaa R. Alameldeen, Srikanth T. Srinivasan, Chris B. Wilkerson(intel Chessialions
`A Reusability-Aware Cache Memory Sharing Technique
`for High-Performance Low-Power CMPs with Private L2 Caches................-.. GFT Bae
`Sungjune Youn (LG Electronics Ine.), Hyunhee Kim, Jihong Kim (SeoulNational University)
`
`nen g itt 50
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`2staaat 56
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`Session 3: Low-powerTechniquesfor Logic,
`Clock Distribution, and Interconnect
`Chair: Brian Otis (University of Washington)
`Co-chair: Saibal Mukhopadhay (/BM)
`e Dual Signal Frequencies and Voltage Levels for Low Power
`and Temperature-Gradient Tolerant Clock Distribution oes cecerestesteneeneeneeeneeneetey 62
`Sherif A. Tawfik, Volkan Kursun (University of Wisconsin-Madison)
`
`e ARobust Edge Encoding Technique for Energy-Efficient Multi-Cycle Interconnect........... 68
`Jae-sun Seo, Dennis Sylvester, David Blaauw (University ofMichigan),
`Himanshu Kaul, Ram Krishnamurthy (inte! Corperation)
`
`« Low-Power Process-Variation Tolerant Arithmetic
`Units Using Input-Based Elastic Choking «00.0...csssesneessnensessnsenseesseensecereerenceneetineevensenenes 74
`Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy (Purdue University)
`« Sleep Transistor Sizing and Control for Resonant Supply Noise Damping LSbcansanednanaeeesiTERRES 80
`Jie Gu, Hanyong Eom, Chris H. Kim (University ofMinnesota)
`*
`
`e Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSICircuits ............... 86
`Ja Chun Ku, Yehea Ismail (Northwestern University)
`
`Session 4: Power Considerations at the Physical Level
`
`Chair: Eli Chiprout (intel Corporation)
`Co-chair: Azadeh Davoodi (University of Wisconsin)
`
`e Post-Placement Leakage Optimization
`for Partially Dynamically Reconfigurable FPGAS...0..........ccccecccseeesseseteneceeceeneeetensaneenneenenereeney 92
`Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang (National Taiwan University)
`¢ Power Optimal MTCMOS RepeaterInsertion for Global Buses...............cceceeeeeneentneeee 98
`Hanif Fatemi, Behnam Amelifard, Massoud Pedram (University ofSouthern California)
`-
`
`« Timing-Driven Row-Based Power Gating....--cc ceceeeece eeteenserentenetenerenneneenentetee 104
`Ashoka Sathanur, Antonio Pullini (Politecnico di Torino), Luca Benini (Universita di Bologna),
`Alberto Macii, Enrico Macii, Massimo Poncino (Politecnico di Torino)
`
`e Detailed Placement for Leakage Reduction
`Using Systematic Through-Pitch Variation .........0...ccccecsecssescsneseeceeseesseeneesetanceeeneenseseneeneenienaes 110
`Andrew B. Kahng, Swamy Muddu, Puneet Sharma (University ofCalifornia at San Diego)
`essesseseesessssesessenesaey 116
`e Early PowerGrid Verification Under Circuit Current Uncertainties..
`Imad A. Ferzli, Farid N. Najm (University ofToronto), Lars Kruse (Magma Design Antomntian
`
`Special Session
`
`« Future of On-Chip Interconnection Architectures0.cece esseseesecneneenereenesnennaneaneenses 122
`Shekhar Borkar (Intel Corporation), Bill Dally (Stanford University)
`
`Session 5: Software and System PowerOptimization
`Chair: Joerg Henkel (University ofKarlsruhe)
`Co-Chair: Yiran Chen (Seagate LLC)
`
`« Towards a Software Approach to Mitigate Voltage Emergencies 00...eeeseereenteseees 123
`Meeta Sharma Gupta, Krishna K. Rangan, Michael D. Smith, Gu-Yeon Wei, David Brooks (Harvard University)
`
`«
`
`e
`
`Improving Disk Reuse for Reducing Power Consumption...occ eeetet eeeeneees 129
`Mahmut Kandemir, Seung Woo Son (The Pennsylvania State University), Mustafa Karakoy (Imperial College)
`
`PVS: Passive Voltage Scaling for Wireless Sensor Networks...seers 135
`Youngjin Cho, Younghyun Kim, Naehyuck Chang (Seoul National University) |
`
`e AProgramming Environment with Runtime Energy Characterization
`for ENGy=AWare APPliGAtlONs cx cccsscsscecusscevssssecesswsssongoncsworsoyyengrtanessesovserveasengungsantertonstoreserersyeyvtgsets 141
`Changjiu Xian, Yung-Hsiang Lu, Zhiyuan Li (Purdue University)
`
`vi
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`Session 6: Leakage-Aware Architectural Synthesis
`Chair: Ron Zhang (Qualcomm)
`Co-Chair! Yung-Hsiang Lu (Purdue University)
`A Process Variation Aware Low Power Synthesis Methodology
`for Fixed-point FIR filters..........:.....2sssnsainimadinsniasrmnnnsnnirnnmnnnnannnienssroereucernrennanernrs 147
`Nilanjan Banerjee, Jung Hwan Choi, Kaushik Roy. (Purdue. University)
`Voltage- and ABB-Island Optimization in High Level Synthesis......2.0..cessaml 53
`Domenik Helms, OlafMeyer, Marko Hoyer (OFFIS Research Institute),
`Wolfgang Nebel (University afOldenburg)
`Power-Optimail RTL Arithmetic Unit Soft-Macro Selection
`Strategyfor Leakage-Sensitive Technologies......eecscscecsesecsseeccensseceeservenessersee 159
`Simone Medardoni, Davide Bertozzi (ENDIF -University ofFerrara),
`Enrico. Masii (Politecnico di Torino)
`
`Power Signal Processing: A New Perspective:
`for Power Analysis and OpthmlZaonsecsiccccccssscnsesorsicevecascesisetesssevesernearsenreeveseneasceerrenra tonne.. 165
`Quming Zhou, Lin Zhong, Kartik Mohanram (Rice University)
`=
`‘
`
`Session 7: Low-Power Memory Design and NBTI Detection
`Chair: Gunjan Pandya (Intel Corporation)
`Co-chair: Volkan Kursun (University of Wisconsin)
`A 160 mV,Fully Differential, Robust Schmitt Trigger Based Sub-threshold SRAM........... 171
`Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy (Purdue University)
`ALow-Power SRAM UsingBit-Line Charge-Recycling Technique................FeclgegpuertaGersececvs 177
`Keejong Kim (Purdue University), Hamid Mahmoodi (San Francisco State University),
`Kaushik Roy (Purdue University)
`Minimizing PowerDissipation during Write Operation to Register Files... 183
`Kimish Patel, Wonbok Lee, Massoud Pedrain(University ofSouthern California)
`An On-Chip NBTI Sensor for Measuring PMOS Threshold Voltage Degradation................ 189
`John Keane, Tae-HyoungKim, Chris H. Kim (University ofMinnesota)
`
`Variable-latency Adder (VL-Adder):
`New Arithmetic Circuit Design Practice to Overcome NBTI.......eeetsesnentenescesegaieses 195
`Yiran Chen, Hai Li (Seagate Technology), Jing Li, Cheng-Kok Koh (Purdue University)
`
`Session 8: DVS and Thermal Management
`Chair; Zhijian Lu (Marvell Semiconductors)
`Co-chair; Jun Yang (University ofPittsburgh)
`
`Throughput of Multi-core Processors Under Thermal Constraints.........0:....ceeeereene 201
`Ravishankar Rao, Sarma Vrudhula, Chaitali Chakrabarti (Arizona State University)
`
`Dynamic Voltage Frequency Scaling
`for Multi-tasking Systems USing Online LEANING, ...... i...ccscccereesrenstrsedenersceteererseenenpeeceeoenseees 207
`Gaurav Dhiman, Tajana Simunic Rosing (University of California, San Diego)
`
`Thermal-Aware Task Scheduling at the System Software Level... eseetecrer eens 213
`Jeonghwan Choi, Chen-Yong Cher, Hubertus Franke; Hendrik. Hamann, Alari Weger; Pradip Bose
`(IBM T.J. Watson Research Center)
`
`Thermal Response to DVFS:Analysis with an Intel PentiumM...................saeeesvimteeeaisiboens 219
`Heather Hanson, Stephen W. Keckler (The University ofTexas, Austin),
`Soraya Ghiasi, Karthick Rajamani, Freeman Rawson, Juan Rubio ([BMAustin Research Laboratory)
`Approximation Algorithms for Power Minimization
`of Earliest Deadline First and Rate Monotonic Schedules.oo... ccccecsenscecntatesearesieeeiennent 220
`Sushu Zhang, Karam S.:Chatha, Goran Konjevod (Arizona State University)
`
`vii
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`Se i Ae 10 My POX
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`Plenary |!
`« The Parallel Computing Landscape: A Berkeley View...eesceesenseeeneennennnnceey 231
`David Patterson (University ofCalifornia, Berkeley)
`
`Session 9: Signal Processing, Wireless, and Communication
`Chair: Chaitali Chakrabarti (Arizona State University)
`Co-chair: Farzan Fallah (Fijuisu Laboratories)
`
`e Low PowerSoft-Output Signal Detector Design
`for Wireless MIMO Communication Systems 000...cecenescence neta nseeenteneneeneresneneerenes 232
`Sizhong Chen, Tong Zhang (Rensselaer Polytechnic Institute)
`
`e« ALow Power Multimedia SoC with Fully Programmable 3D Graphics
`and MPEG4/H.264/JPEG for Mobile Devices oo... ceceseecsssenessesneeesneeareenenneanesneenesseneresnense 238
`Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim (KAIST),
`Jongcheol Jeong, Euljoo Jeong, Suk-Joong Lee (Corelogic, Inc.), Hoi-Jun Yoo (KAIST)
`
`£
`¥
`« An Architecture For Energy Efficient Sphere Decoding...te eeeeeeetenessereoened 244
`Ravi Jenkal, RhettDavis (North Carolina State University)
`
`¢ On the Selection of Arithmetic Unit Structure
`in Voltage Overscaled Soft Digital Signal Processing ...............:ccesessnecseereeniteeeteeetis 250
`Yang Liu, Tong Zhang (Rensselaer Polytechnic Institute)
`* Low-power H.264/AVC Baseline Decoderfor Portable Applications...............ee 256
`Ke Xu, Chiu Sing Choy (The Chinese University ofHong Kong)
`
`Session 10: Architectural Power Optimization
`Chair: Geoffrey Yeap (Qualcomm)
`Co-chair : Yu Cao (Arizona State University)
`
`e A0.4-V UWB Baseband Processor un... cccceeesseeceeesesnaeeersnsnessecneesinsnesnessseensaneeenraenaenies 262
`Vivienne Sze, Anantha P. Chandrakasan (Massachusetts Institute ofTechnology)
`
`« Resource Area Dilation to Reduce Power Density in Throughput Servers..............0......+ 268
`Michael D. Powell (Intel Massachusetts, Inc. and Purdue University), T. N. Vijaykumar (Purdue University)
`» Locality-Driven Architectural Cache Sub-banking for Leakage Energy Reduction............274
`Olga Golubeva, Mirko Loghi, Enrico Macii, Massimo Poncino (Politecnico di Torino)
`e A Multi-Model Power Estimation Engine for Accuracy Optimization .......0.0.0 280
`Felipe Klein, Guido Araujo (Institute ofComputing, UNICAMP), Rodolfo Azevedo (UNICAMP),
`Roberto Leao, Luiz C. V. Santos (UFSC)
`
`Session 11: DC/DC Converters
`Chair: William Li (intel)
`Co-chair: Domine Leenaerts (NXP)
`
`e A Fast-Transient Over-Sampled Delta-Sigma Adaptive
`DC-DC Converter for Power-Efficient Noise-Sensitive Devices...eee eeneecees 286
`Minkyu Song, Dongsheng Ma (The University ofArizona)
`
`¢ High-Efficiency Synchronous Dual-Output Switched-Capacitor
`DC-DC Converter with Digital State Machine Controloo...eenteeenenecertesireneteneeneneees 292
`Shiming Han, Xiaobo Wu (Zhejiang University), Yang Liu (Analog Devices, Inc)
`
`« A Micro Power Management System and Maximum Output
`PowerControl for Solar Energy Harvesting Applications oo...eee tener eteeseneeneneeee 298
`Hui Shao, Chi-Ying Tsui, Wing-Hung Ki (The Hong Kong University ofScience and Technology)
`
`viii
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`e Advanced Thermal Sensing Circuit and Test Techniques Used
`in a High Performance 65nm Processot........._ccvocaksanpyevnglenveeresennonenesenrenVEXTTU¥TAMSSUS0S¥30USOIROCUTTEDUSEN304
`David E: Duarte, Greg Taylor, Keng L. Wong,Usman A. Mughal, George L.Geannopoulos
`(Intel Corporation)
`e SingleInductor, Multiple Input, Multiple Output (SIMIMO)
`Power Mixer-Charger-Stupply System ...........cscsessneenesnsesseeeeesenneenneearrennanssnesinonaneennentarengsesess 310
`Min Chen, Gabriel A. Rincén-Mora (Georgia Institute of Technology)
`
`Session 12: Energy and PowerDelivery
`Chair: Nemani Mahadev (Intel Corporation)
`Co-chair: Swarup Bhunia (Case Western University)
`e Vibration Energy Scavenging and Managementfor Ultra Low Power Applications..........316
`Lu Chao, Chi-Ying Tsui, Wing-Hung Ki (Hong Kong University ofScienceand Technology)
`« Energy Management of DVS-DPM Enabled Embedded Systems Powered
`by Fuel Cell-Battery Hybrid Source..............---sasaceusesinoecnatherdvsorsesnatesparathRernereedsorrerswwenmonesesdseesiene 22
`¥
`¢
`Jianli Zhuo, Chaitali Chakrabarti (ArizonaState University),
`Naehyuck Chang (Seoul National University)
`e Design of an Efficient Power Delivery Network
`in an SoCto Enable Dynamic Power Management.................----ecacuessieeneoacerneennitieTaSTaTTTAAI OLS
`Belmam Amélifatd, Massoud Pedram(University ofSouthern California)
`¢ Energy-Efficient and Performance-Enhanced Disks Using Flash-Memory Cache..............334
`Jen-Wei Hsieh (National Chiayi University), Tei-Wei Kuo, Po-Liang Wu (National Taiwan University),
`¥u-Chung Huang (Genesys Logic, Inc.)
`e SAPP: Scalable and Adaptable Peak Power Managementin NoCs...............00-+asesaasascenenD 340
`Pravéen S. Bhojwani, Jason D. Lee, Rabi N. Mahapatra (Texas A&MUniversity)
`
`Pienary Il
`0 All Watts Considered c.c..cccccecccccccssccsceceeeceesseteceeseenerenneeasaneesenennereatneneanencenanneneneneeaseanecsinne S40
`Luiz AndréBarroso (Googie)
`
`Posters
`« A65-nm Pulsed Latch with a Single Clocked Transistot................---ssesemeenenereeeteeeennnniines 347
`Martin Saint-Laurent; BakerMoharninad, Paul Bassett (QualcommInc.)
`
`« A Methodologyfor Analysis and Verification
`of Power Gated Circuitswith Correlated Results .........icececesnetetteenreneinesSeventies|
`Aveek Sarkar, Shen Lin, Kai Wang (Apache Design Solutions)
`e VT Balancing and Device Sizing Towards High Yield
`of Sub-threshold Static Logic Gates.............sedevsusuenensereecssssencarscsendbashecceseshonsssuceseasanruberegvaneenepetseasesa 355
`Yu Pu (Technische Universiteit Eindhoven, NXP.Research Eindhoven andNational University ofSingapore),
`José Pineda de Gyvez (Technische Universiteit Bindhoven and NXP Research),
`Henk Corporaal (Technische Universiteit Eindhoven), Yajun Ha (National University ofSingapore)
`« Power-Efficient LDPC Code DecoderArchitecture .......5. cieseeseeeneetteenirens rma 99
`Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi-Goto (Waseda University)
`e A Low-Power CSCD Asynchronous Viterbi Decoder for Wireless Applications.................363
`Mohamed Kawokgy, C. André T. Salama (University ofToronto)
`e Reducing Cache Energy Consumption by Tag Encoding
`in Embedded Processors -..........ceceeccseeeeeeeccereteneeteateredeenseenesspevbavnseeceseueescuvceounuvenanaenenlZaVERUSESTDOREEEi367
`Mingining Zhang, Xiaotao Chang, Ge Zhang
`(institute ofComputing Technology, Chinese Academy ofSciencés)
`
`ix
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`° On Reducing Energy-Consumption by Late-Inserting
`Instructions into the Issue QUEUE occcessesences eseseeesnsensstsetasaseenensencenseusescagentenesiesennentey 371
`Enric Morancho, Jose Maria Llaberia, Angel Olivé (Universitat Politécnica de Catalunya)
`e Power-Aware Operand Delivery .........ccccss esses sseessneeseensseesnecsnsessneesnreensnessssceenneseuesannsessecsnareanes 375
`Erika Gunadi, Mikko H. Lipasti (University of Wisconsin)
`
`e Onthe Latency, Energy and Area of Checkpointed,
`Superscalar Register Alias Tables .0.............c:sccccseeesseeesneteenesersnneenennenesenesnresterareerenseenavansennaseneety 379
`Eltham Safi, Patrick Akl, Andreas Moshovos, Andreas Veneris (University of Toronto),
`Aggeliki Arapoyianni (University ofAthens)
`e Adaptive Analog Biasing — A Robustness-Enhanced Low-Power Technique
`for Analog Baseband Design ..........ccecccesecnceeceeeeeeseneeessnsanceneesssrsensensnesnecersaeerserensancenaseesonansaness 383
`Zhenhua Wang (NXP Semiconductors)
`
`« Slope interconnect Effort: Gate-Interconnect Interdependent Delay Model
`for CMOS Logic Gates with Scaled Supply Voltage...............scesreseseeeceessnenennenenseceerentaneseeseneeseeses 387
`Myeong-Eun Hwang (Purdue University), Seong-Ook Jung (Yonsei University),
`=
`‘
`Kaushik Roy (Purdue University)
`e Electromigration and Voltage Drop Aware Power Grid Optimization
`for Power Gated ICS ooo... cccccccccececcscec nese cneesecene nesses csaesnsecssseuesesaseuneassnesseuecasaressnsneensinenesaceaterecaseaseecanees 391
`Aida Todri (University ofCalifornia, Santa Barbara), Shih-Chieh Chang (NTHU),
`Malgorzata Marek-Sadowska (University ofCalifornia, Santa Barbara)
`e Reducing Display Power in DVS-enabled Handheld Systems...............-.-.ene 395
`Jung-hi Min, Hojung Cha (Yonsei University)
`. Multicasting based Topology Generation and Core Mapping
`for a PowerEfficient Networks-on-Chipy 0... cess seeeeteseseecsten cree retsenereensennnenreesesnaseannencenaenans 399
`Balasubramanian Sethuraman, Ranga Vemuri (University ofCincinnati)
`
`e Phase-aware Adaptive Hardware Selection
`for Power-efficient Scientific Computations 0...cesses eencenerces tereteesereenessereseersnatenteanenigs 403
`Konrad Malkowski, Padma Raghavan, Mahmut Kandemir, Mary Jane Irwin (The Pennsylvania State University)
`« Signoff Power Methodology for Contactless Smartcards.00... teense 407
`Julien Mercier (STMicroelectronics), Christian Dufaza (L2MP), Mathieu Lisart (STMicroelectronics)
`e AnILP Based Approach to Reducing Energy Consumption in NoC Based CMPs............. 41]
`Ozcan Ozturk, Mahmut Kandemir, Seung Woo Son (Pennsylvania State University)
`
`PRGERNr MAXscssezssczcxccoecxveczzseresucepeneypqesnnesesnevsovensoveenconesonsensnenneclemencnndsB¥s HESS VISE9055 252572575 ETOREREEEEEON? 415
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