Paper 18
`Trials@uspto.gov
`571-272-7822 Entered: December 4, 2018
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
` v.
`VLSI TECHNOLOGY LLC,
`Patent Owner.
`____________
`
`Case IPR2018-01038
`Patent 8,566,836 B2
`____________
`
`
`
`
`
`
`
`
`
`Before BART A. GERSTENBLITH, MINN CHUNG, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`McGRAW, Administrative Patent Judge.
`
`
`
`DECISION
`Denying Institution of Inter Partes Review
`35 U.S.C. § 314(a)
`
`
`
`
`
`Trials@uspto.gov
`571-272-7822 Entered: December 4, 2018
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
` v.
`VLSI TECHNOLOGY LLC,
`Patent Owner.
`____________
`
`Case IPR2018-01038
`Patent 8,566,836 B2
`____________
`
`
`
`
`
`
`
`
`
`Before BART A. GERSTENBLITH, MINN CHUNG, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`McGRAW, Administrative Patent Judge.
`
`
`
`DECISION
`Denying Institution of Inter Partes Review
`35 U.S.C. § 314(a)
`
`
`
`
`
`
`IPR2018-01038
`Patent 8,566,836 B2
`
`
`I.
`INTRODUCTION
`Intel Corporation (“Petitioner”) filed a Petition requesting an inter
`partes review of claims 1–11, 13, 14, 18, 20, and 21 (“the challenged
`claims”) of U.S. Patent No. 8,566,836 B2 (Ex. 1001, “the ’836 patent”).
`Paper 2 (“Pet.”). On September 6, 2018, VLSI Technology LLC (“Patent
`Owner”) filed a Patent Owner Preliminary Response (Paper 9) and a
`Corrected Patent Owner Preliminary Response (Paper 10, “Prelim. Resp.”).
`Following authorization, Petitioner filed a Reply (Paper 14, “Reply”) and
`Patent Owner filed a Sur-Reply to Petitioner’s Reply (Paper 15, “Sur-
`Reply”). We have authority to determine whether to institute an inter partes
`review. 35 U.S.C. § 314(a); 37 C.F.R. § 42.4(a).
`The standard for instituting an inter partes review is set forth in
`35 U.S.C. § 314(a), which provides that an inter partes review may not be
`instituted unless the information presented in the Petition shows “there is a
`reasonable likelihood that the petitioner would prevail with respect to at least
`1 of the claims challenged in the petition.” Upon consideration of the
`Petition, the Preliminary Response, Reply, the Sur-Reply, and the evidence
`therein, we conclude the information presented does not show that there is a
`reasonable likelihood that Petitioner would prevail in establishing the
`unpatentability of at least one of the challenged claims of the ’836 patent.
`Accordingly, we do not institute inter partes review of the ’836 patent.
`
`A. Related Proceedings
`Petitioner states Patent Owner has asserted claims 1, 4, 7, 9–11, 13,
`14, 17, 20, and 21 of the ’836 patent in VLSI Technology LLC v. Intel
`Corporation, No. 5:17-cv-05671 (N.D. Cal. Oct. 2, 2017). Pet. 2.
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`B. The ’836 Patent
`The ’836 patent is directed to a “multi-core system on a chip” in
`which a speed information for each core, such as the maximum operation
`speed (Fmax), is extracted and stored in a storage device, such as a device
`control registry. Ex. 1001 [57]. The information may be “accessed and used
`by the operating system when allocating workload among the cores by
`selecting the fast[est] core . . . to run any applications or tasks that [cannot]
`be executed on a plurality of cores.” Id.
`
`C. Illustrative Claims
`Claims 1, 10, and 20, which are the only challenged independent
`claims in this proceeding, are illustrative and reproduced below.1
`
`1. A method for operating a multi-core processing device,
`comprising:
`[a] measuring a processing speed parameter for each of
`a plurality of cores;
`[b] storing each measured processing speed parameter
`for each of the plurality of cores in a storage device;
`[c] and upon identifying a processing task that can not
`be run across the plurality of cores, selecting a core
`from the plurality of cores having a fastest
`measured processing speed parameter at a given
`voltage to run the processing task.
`10. A multi-core system on chip (SOC), comprising:
`[a] a plurality of cores, each core comprising a
`performance measurement circuit for measuring a
`performance parameter value for said core; and
`
`
`1 Bracketed material and formatting added for clarity and for consistency
`with usage by the parties.
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`[b] at least a first storage device for storing the
`performance parameter values for the plurality of
`cores
`[c] for use in selecting a core having maximized or
`minimized performance parameter value at a
`specified voltage to run a processing task that can
`not be run across the plurality of cores.
`20. In a multi-core processor comprising multiple cores
`which are controlled by system logic, a method for
`executing single core applications and multi-core
`applications comprising:
`[a] measuring a maximum processing speed value for
`each of the multiple cores for at least a first
`operating voltage value;
`[b] storing each measured maximum processing speed
`value for each of the multiple cores;
`[c] running a multi-core application on a plurality of the
`multiple cores by controlling each of the plurality
`of the multiple cores to run at a speed which is
`identified from the stored maximum processing
`speed values to be the slowest maximum processing
`speed of the plurality of the multiple cores; and
`[d] running a single core application on a single core
`which is identified from the stored maximum
`processing speed values for the multiple cores as
`being the fastest core upon identifying a processing
`task that cannot be run across the plurality of the
`multiple cores.
`D. Asserted Grounds of Unpatentability
`Relying upon the declaration testimony of David August, Ph.D.,
`
`(Ex. 1002), Petitioner challenges claims 1–11, 13, 14, 17, 18, 20, and 21 of
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`the ’836 patent based on the asserted grounds of unpatentability (“grounds”)
`set forth in the table below.
`References
`Jacobowitz,2 Finkelstein,3 and
`Bowman 4
`Jacobowitz, Finkelstein, and
`Bowman, and Herbert 5
`
`Basis
`§ 103
`
`§ 103
`
`Challenged Claim(s)
`1–11, 13, 14, 18, 20, and 21
`
`17
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`II. DISCUSSION
`A. Principles of Law
`A claim is unpatentable under § 103(a) if the differences between the
`claimed subject matter and the prior art are such that the subject matter, as a
`whole, would have been obvious at the time the invention was made to a
`person having ordinary skill in the art to which said subject matter pertains.
`KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). The question of
`obviousness is resolved on the basis of underlying factual determinations,
`including (1) the scope and content of the prior art; (2) any differences
`between the claimed subject matter and the prior art; (3) the level of skill in
`
`
`2 U.S. Patent No. 7,917,758 B2, filed May 11, 2007, issued Mar. 29, 2011
`(Ex. 1003, “Jacobowitz”)
`3 U.S. Patent Application Publication No. 2010/0169609 A1, filed Dec. 30,
`2008, published July 1, 2010 (Ex. 1004, “Finkelstein”)
`4 Bowman et al., Impact of Die-to-Die and Within-Die Parameter
`Variations on the Throughput Distribution of Multi-Core Processors,
`ISLPED '07 Proceedings of the 2007 International Symposium on
`Low Power Electronics and Design, Aug. 27–29, 2007, pp. 50–55
`(Ex. 1005, “Bowman”).
`5 Herbert et al., Analysis of Dynamic Voltage/Frequency Scaling in
`Chip-Multiprocessors, ISLPED '07 Proceedings of the 2007
`International Symposium on Low Power Electronics and Design,
`Aug. 27–29, 2007, pp. 38–43 (Ex. 1007, “Herbert”).
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`the art; and (4) when in evidence, objective indicia of non-obviousness (i.e.,
`secondary considerations).6 Graham v. John Deere Co., 383 U.S. 1, 17–18
`(1966). “To satisfy its burden of proving obviousness, a petitioner cannot
`employ mere conclusory statements. The petitioner must instead articulate
`specific reasoning, based on evidence of record, to support the legal
`conclusion of obviousness.” In re Magnum Oil Tools Int’l, Ltd., 829 F.3d
`1364, 1380 (Fed. Cir. 2016).
`
`B. Level of Ordinary Skill in the Art
`Petitioner contends a person of ordinary skill in the art at the time of
`the alleged invention of the ’836 patent (a “POSITA”) would have had at
`least an Master of Science degree in electrical engineering or materials
`science (or equivalent experience) and would have had two to three years of
`academic or industry experience in multi-core processor system design and
`operation, or comparable industry experience with integrated current
`processing, manufacturing, and structures. Pet. 31 (citing Ex. 1002 ¶¶ 38–
`39).
`
`Patent Owner does not articulate a level of skill for a POSITA. See
`generally Prelim. Resp. For the purposes of this Decision, we adopt
`Petitioner’s proposed articulation of a person of ordinary skill in the art.
`
`C. Claim Construction
`In an inter partes review, we construe claim terms in an unexpired
`patent according to their broadest reasonable construction in light of the
`
`
`6 Patent Owner does not present arguments or evidence of such secondary
`considerations in its Preliminary Response. As such, secondary
`considerations do not constitute part of our analysis.
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`specification of the patent in which they appear. 37 C.F.R. § 42.100(b).7
`Therefore, we look to the specification to see if it provides a definition for
`claim terms, but otherwise apply the broadest reasonable interpretation. In
`re ICON Health and Fitness, Inc., 496 F.3d 1374, 1379 (Fed. Cir. 2007).
`Petitioner does not identify any claim terms as requiring construction.
`See Pet. 31. Neither does Patent Owner. See generally Prelim. Resp. For
`the purposes of this Decision, we determine that no claim term needs express
`construction. See Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795,
`803 (Fed. Cir. 1999) (“[O]nly those terms need be construed that are in
`controversy, and only to the extent necessary to resolve the controversy.”).
`
`D.
`
`Asserted Obviousness of Claims 1–11, 13, 14, 18, 20, and 21
`over Jacobowitz, Finkelstein, and Bowman
`Petitioner asserts that claims 1–11, 13, 14, 18, 20, and 21 are
`unpatentable over Jacobowitz, Finkelstein, and Bowman. Pet. 32–71.
`Patent Owner opposes. Prelim. Resp. 1–64.
`
`1. Jacobowitz
`Jacobowitz is directed to “techniques for optimizing performance of
`multicore chips.” Ex. 1003, 1:32–33. One method involves, inter alia,
`determining the Vdd-frequency SCHMOO8 characteristics of each core,
`saving data indicative of the Vdd-frequency SCHMOO characteristics, and
`
`
`7 Because the Petition was filed before the effective date of Changes to the
`Claim Construction Standard for Interpreting Claims in Trial Proceedings
`Before the Patent Trial and Appeal Board, 83 Fed. Reg. 51,340 (Nov. 13,
`2018), the previous version of § 42.100(b) governs claim construction in this
`proceeding.
`8 A “SCHMOO” is a “two-dimensional plot of the valid Vdd and frequency
`operating region of a circuit, such as a processor core.” Ex. 1003, 2:36–39.
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`configuring the cores to provide optimum power consumption and/or
`optimum performance, for a given workload. Id. at 1:33–43.
`Figure 1, reproduced below, shows multi-core chip 100 having several
`central processing unit (CPU) cores 102. Id. at 3:8–11, 3:15–16, Fig. 1.
`
`
`
`Figure 1, reproduced above, depicts multi-core chip 100.
`
`2. Finkelstein
`Finkelstein is directed to “a method for optimizing the voltage-
`frequency parameters in multi-core processor systems.” Ex. 1004 ¶ 2.
`Figure 1, reproduced below, illustrates data processing system 100 having
`multi-core processor 102 with several processor cores 104 coupled to a
`physical memory. Id. ¶¶ 14–15.
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`Figure 1, reproduced above, shows data processing system 100.
`Figure 2, reproduced below, is a flow diagram illustrating a flow
`sequence for optimizing the voltage-frequency setup of the multi-core
`processor of Figure 1. Id. ¶¶ 9, 20.
`
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`Figure 2, reproduced above, is a flow diagram illustrating a flow
`sequence for optimizing the voltage-frequency setup of a multi-core
`processor system. Id.
`Figure 4, shown below, illustrates possible ways of switching between
`power and performance optimization modes in a multi-core processor system.
`Id. ¶¶ 11, 29.
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`Figure 4, reproduced above, illustrates possible ways for multi-core
`processor 102 to switch between the various functional modes (i.e., power
`mode and performance mode) referred to in flow sequence 200 of Figure 2.
`See id. ¶¶ 11, 29. “During runtime, whenever a processor core enters or
`leaves the C6 state, the first plurality of processor cores changes and a
`processor core with the slowest processor speed is then ascertained or
`identified from among a re-ascertained first plurality of processor core.” Id.
`¶ 29. The voltage-frequency curve associated with the slowest processor
`core is then selected. Id. Depending on the functional mode required, at
`least one of the voltage and frequency is then adjusted accordingly. Id.
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`Based on the voltage-frequency characteristics curve of the slowest
`processor core, the operating voltage and frequency are adjusted according
`to certain rules. See id.
`
`3. Bowman
`Bowman describes a “statistical performance simulator . . . developed
`to explore the impact of die-to-die (D2D) and within-die (WID) parameter
`variations on the distributions of maximum clock frequency (FMAX) and
`throughput for multi-core processors in a future 22nm technology.”
`Ex. 1005, 50 (Abstract).9 Bowman explains that “[m]ulti-core processors
`are emerging as a power-efficient approach to designing high-performance
`microprocessors” and that multi-core processors “can achieve better
`performance [than large single-core processors] on highly parallel
`multithreaded applications by executing the threads across the cores while
`operating at a lower clock frequency and lower power.” Id. (§ 1).
`Bowman states that it “explores the impact of D2D and WID
`parameter variations on [maximum clock frequency (“FMAX”)] and
`throughput distributions of multi-core processors through a newly developed
`statistical performance simulator.” Id. The “statistical performance
`simulator performs 1000’s of Monte Carlo runs per multi-core design.” Id.
`at 51 (§ 2). For each run, a delay sample is generated for each critical path.
`Id. The slowest critical path for each core determines the FMAX for the
`core. Id. All cores in the multi-core processor are assumed to have the same
`
`9 Petitioner did not uniquely number each page of Exhibit 1005 in sequence
`as required by 37 C.F.R. § 42.63(d)(2)(i). Therefore, for consistency with
`Petitioner’s citations, this Decision refers to the page numbers of the
`underlying reference and section headings.
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`global clock frequency. Id. For highly parallel multi-threaded (MT)
`applications, where all cores execute instructions, the slowest core FMAX
`determines the FMAX of the microprocessor. Id. For single-threaded (ST)
`applications, the fastest core determines the FMAX. Id. The corresponding
`MT and ST FMAX values are inputs to a multicore throughput model to
`calculate the corresponding MT and ST throughput values. Id. After
`performing 1000’s of Monte Carlo runs, the simulator generates FMAX and
`throughput distributions for MT and ST applications. Id.
`
`4. Independent Claim 1
`Independent claim 1 is directed to, in general, a method for operating
`a multi-core processing device comprising [a]10 measuring a processing
`speed parameter for each of a plurality of cores, [b] storing the measured
`processing speed parameters, and [c] upon identifying a processing task that
`can not be run across the plurality of cores, selecting a core from the
`plurality of cores having a fastest measured processing speed at a given
`voltage to run the processing task. Ex. 1001, 10:44–54.
`
`a. Petitioner’s Contentions
`Petitioner contends that Jacobowitz teaches the limitations of claim 1,
`steps [a] and [b]. See Pet. 35–36. For example, Petitioner asserts that
`Jacobowitz’s disclosure of a maximum core frequency test phase of a
`“SCHMOO test,” which measures the maximum frequency for each of the
`plurality of the cores in a multi-core chip at a given voltage, teaches
`“measuring a processing speed parameter for each of a plurality of cores” as
`
`
`10 For clarity and consistency, the bracketed letters refer to claim elements
`identified by the parties as shown in Section I.C.
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`recited in claim 1, step [a]. See id. (citing Ex. 1003, [57], 1:35–37, 2:32–33,
`3:49, 3:64–4:10, 4:31–34, 8:66–9:1, 7:10–48, Figs. 1–2). Petitioner further
`asserts that Jacobowitz teaches the “storing” of measured processing speed
`parameter limitations of claim 1, step 1[b], because Jacobowitz discloses
`storing the results of the SCHMOO test. Id. at 36 (citing Ex. 1003, [57],
`1:37–38, 4:22–25, 4:56–5:4, 7:4–9).
`With respect to claim 1, step [c], Petitioner relies on the combined
`teachings of Jacobowitz, Finklestein, and Bowman. Id. at 36–45.
`Specifically, Petitioner asserts that “Jacobowitz (which teaches using the
`measured processing speed parameter to configure the core(s)), in
`combination with Finkelstein (which teaches running a processing task that
`can not be run across multiple cores on the fastest core) and Bowman (which
`teaches identifying that processing task and selecting the fastest core),
`teaches [the limitations of claim 1, step [c]].” Id. at 44; see also generally
`id. at 36–45.
`Petitioner contends that Jacobowitz teaches using the voltage-
`frequency SCHMOO data stored for each core to configure the cores to
`optimize power consumption or performance for a given workload. Id. at 37
`(citing Ex. 1003, [57], 1:39–41, 2:39–47, 5:15–40; Ex. 1002 ¶ 79).
`Petitioner states Finkelstein teaches a multicore processor system that
`can process parallel as well as legacy sequential programs. Id. at 37 (citing
`Ex. 1004 ¶¶ 4, 5, 14). Petitioner asserts that a POSITA would have
`understood that legacy sequential computer programs are designed to run on
`a single core and, therefore, cannot run across multiple cores of a multi-core
`processor. Id. (citing Ex. 1002 ¶ 80). Petitioner concludes that a POSITA
`would have understood that a legacy sequential computer program is “a
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`processing task that can not be run across the plurality of cores.” Id. at 37–
`38 (citing Ex. 1002 ¶ 80).
`Petitioner also asserts a POSITA would have understood that the
`legacy computer program in Finkelstein (i.e., a processing task that cannot
`be run across the plurality of cores) runs on the fastest core. To support this
`assertion, Petitioner points to the performance optimization mode shown in
`Figure 4. See id. at 41 (citing Ex. 1004 ¶ 29, Fig. 4). Petitioner asserts that,
`as shown in Figure 4, the multi-core processor initially starts at data point
`402 with all cores active and operating at the maximum frequency (Fmax) of
`the slowest core (Core 0) for a given voltage (V). Id. (citing Ex. 1004 ¶ 29,
`Fig. 4). As the slower cores become inactive (e.g., are operatively switched-
`off), the remaining active cores are adjusted to operate at the maximum
`frequency of the slowest core from among the remaining active cores for the
`given voltage. Id. (citing Ex. 1004 ¶ 29; see also Ex. 1002 ¶ 84). Petitioner
`contends that a POSITA would have understood that “when the multi-core
`processor has only one core active (i.e., all other cores are inactive) such as
`shown in data point 406 in Figure 4, that the processor can only run [the
`legacy sequential computer programs] on the one active core.” Id. at 42
`(citing Ex. 1002 ¶ 85) (emphasis added). Petitioner asserts that a POSITA
`would have understood that “when the multi-core processor has only one
`active core, the active core is the core with the largest maximum operating
`frequency at the given voltage (i.e., the fastest core (Core 3) in Figure 4).”
`Id. (citing Ex. 1002 ¶ 85) (emphases added). Petitioner concludes that,
`therefore, a POSITA “would have understood that Finkelstein discloses a
`legacy sequential computer program (i.e., ‘a processing task that can not be
`run across the plurality of cores’) that runs on the fastest core (Core 3) (i.e.,
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`‘a core from the plurality of cores having a fastest measured processing
`speed parameter at a given voltage to run the processing task’).” Id. at 42–
`43 (citing Ex. 1002 ¶ 86).
`Petitioner states that “[a]lthough Finkelstein does not expressly
`disclose ‘identifying’ the computer program as a legacy sequential computer
`program that can only run on a single core and can not run across multiple
`cores, as opposed to a parallel computer program that can run across
`multiple cores, and based on that identification, ‘selecting’ the fastest core to
`run the computer program, this is expressly taught by Bowman.” Id. at 43
`(citing Ex. 1002 ¶ 86).
`With respect to Bowman, Petitioner contends “Bowman describes a
`multi-core processor that distinguishes between, and separately handles,
`highly parallel multi-threaded (MT) applications and single-threaded (ST)
`applications.” Id. (citing Ex. 1005, 50 (Abstract, §1), 51 (§2)). Petitioner
`further asserts that Bowman discloses for “highly parallel multi-threaded
`(MT) applications, where all cores execute instructions, the slowest core
`FMAX [maximum clock frequency] determines the FMAX of the
`microprocessor,” while for “single-threaded(ST) applications, the fastest
`core determines the FMAX.” Id. (quoting Ex. 1005, 51 (§ 2)); see also id. at
`43 (quoting Ex. 1005, 53 (§4) as stating “.MT applications, where all cores
`execute instructions _ ST applications, where only one core executes
`instructions”).
`Petitioner contends that a POSITA would have understood from
`Bowman that the single-threaded (ST) applications are processing tasks that
`cannot be run across the plurality of cores. See id. at 43–44 (citing Ex. 1002
`¶ 88). Petitioner further asserts that a “POSITA would also have understood
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`that Bowman teaches determining whether an application is single-threaded
`as opposed to multi-threaded, and if the application is determined to be
`single-threaded, selecting the fastest core-the core with the maximum clock
`frequency (FMAX)-to run the application.” Id. at 44 (citing Ex. 1002 ¶ 89).
`Thus, Petitioner concludes, Bowman discloses “identifying” a processing
`task that cannot be run across the plurality of cores, and upon this
`identification, “‘selecting’ a core from the plurality of cores having a fastest
`measured processing speed parameter at a given voltage to run the
`processing task.” Id. (citing Ex. 1002 ¶ 89).
`
`b. Analysis
`Having considered the arguments and evidence, we are not persuaded
`that Petitioner shows a reasonable likelihood of prevailing in its assertion
`that the cited art teaches the limitations of claim 1, step [c], which recites
`“upon identifying a processing task that can not be run across the plurality of
`cores, selecting a core from the plurality of cores having a fastest measured
`processing speed parameter at a given voltage to run the processing task.”
`With respect to claim 1, step [c], Petitioner relies on the combined
`teachings of Jacobowitz, Finklestein, and Bowman. Pet. 36–45.
`Specifically, Petitioner asserts that “Jacobowitz (which teaches using the
`measured processing speed parameter to configure the core(s)), in
`combination with Finkelstein (which teaches running a processing task that
`can not be run across multiple cores on the fastest core) and Bowman (which
`teaches identifying that processing task and selecting the fastest core),
`teaches [the limitations of claim 1, step [c]].” Id. at 44; see also generally
`id. at 36–45. We determine that Petitioner does not show sufficiently on this
`record that the cited art, either alone or in combination, teaches identifying a
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`processing task that cannot be run across the plurality of cores or teaches
`selecting a core from a plurality of cores having the fastest measured
`processing speed parameter to run a processing task.
`First, we find Petitioner fails to show that Finkelstein teaches running
`any task on the fastest core of a plurality of cores. See Pet. 42–43 (stating a
`POSITA would have understood that Finkelstein’s legacy sequential
`program “runs on the fastest core (Core 3) (i.e., ‘a core from the plurality of
`cores having a fastest measured processing speed parameter at a given
`voltage to run the processing task’)”); Ex. 1002 ¶ 86. Contrary to
`Petitioner’s assertions, however, Finkelstein does not teach running any task
`on the fastest core of a plurality of cores. Rather, Finkelstein directs its
`cores to operate at the frequency of the slowest active core. See Ex. 1004
`¶ 21 (stating the “operating frequency of each processor core in the first
`plurality of processor cores may be ascertained to identify the processor core
`with lowest operating frequency (i.e., slowest processor speed)”) (emphasis
`added); id. ¶ 29 (“During runtime, whenever a processor core enters or
`leaves the C6 state, the first plurality of processor cores changes and a
`processor core with the slowest processor speed is then ascertained or
`identified from among a re-ascertained first plurality of processor core. The
`voltage-frequency curve associated with the slowest processor is then
`selected.” (emphases added)).
`Petitioner asserts that a POSITA would have understood that Core 3
`in Figure 4 is the fastest core when the multi-core processor has only one
`core active. See Pet. 42 (citing Ex. 1002 ¶ 85). We disagree. Finkelstein
`identifies Core 3 as the slowest of all cores shown in Figure 4. See
`Ex. 1004, Fig. 4. The slowest core, i.e., Core 3, does not become the fastest
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`core of a plurality of cores, when there are no other active cores remaining.
`Therefore, we disagree with Petitioner that Finkelstein teaches “a core from
`the plurality of cores having a fastest measure processing speed parameter at
`a given voltage to run the processing task.” Pet. 42–43 (citing Ex. 1002
`¶ 85).
`
`Second, we find that Petitioner fails to show that Bowman teaches
`“identifying” a task and “selecting” a core as required in claim 1, step [c].
`See Pet. 36–43 (not making any argument that either Jacobowitz or
`Finkelstein teaches or suggests “identifying” any processing tasks or
`“selecting” any core); see also id. at 43 (admitting “Finkelstein does not
`expressly disclose ‘identifying’ the computer program as a legacy sequential
`computer program that can only run on a single core and can not run across
`multiple cores . . . and based upon that identification ‘selecting’ the fast core
`to run the computer program,” but asserting that “this is expressly taught by
`Bowman”). Specifically we find that Petitioner does not provide sufficient
`evidence or argument to support its contentions that “Bowman discloses
`‘identifying’ a processing task that can not be run across the plurality of
`cores, and upon this identification, ‘selecting’ a core from the plurality of
`cores having a fastest measured processing speed parameter at a given
`voltage to run the processing task.” Id. at 44; see also generally id. at
`43–45.
`Petitioner does not point to any express disclosure that Bowman
`teaches “identifying” any processing task or “selecting” any core. See
`Pet. 43–45. Rather, Petitioner relies upon Dr. August’s testimony that a
`“POSITA would have understood that Bowman teaches determining
`whether an application is single-threaded as opposed to multi-threaded, and
`
`19
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`IPR2018-01038
`Patent 8,566,836 B2
`
`if the application is determined to be single-threaded, selecting the fastest
`core-the core with the maximum clock frequency (FMAX)-to run the
`application.” Id. at 44 (citing Ex. 1002 ¶ 89) (emphases added). Petitioner
`then concludes, “[a]ccordingly, Bowman discloses ‘identifying’ a processing
`task that can not be run across the plurality of cores, and upon this
`identification, ‘selecting’ a core from the plurality of cores having a fastest
`measured processing speed parameter at a given voltage to run the
`processing task.” Id. (citing Ex. 1002 ¶ 89) (emphases added). We are not
`persuaded by Petitioner’s arguments or evidence.
`
`First, we find Dr. August’s declaration testimony is entitled to little to
`no weight because all of his opinions are based on his contention that
`Bowman discloses a “multi-core processor.” See, e.g., Ex. 1002 ¶ 87
`(“Bowman describes a multi-core processor that distinguishes between”
`multi-threaded and single threaded applications), id. (“depending on the
`application, the multi-core processor processes the applications differently”),
`id. (“the highly parallel multi-threaded applications are run on multiple
`cores”), id. (“single threaded applications are run on only one core”), id.
`¶ 89 (stating a POSITA “would have understood that in order for Bowman’s
`multi-core processor to be able to handle the two types of applications
`differently . . . the multi-core processor first determines (or identifies) the
`type of application”), id. (the multi-core processor . . . selects which core(s)
`and frequency to execute the application”).
`Contrary to Dr. August’s assertions, however, Bowman, does not
`disclose a “multi-core processor.” Rather, Bowman is directed to a
`“statistical-performance simulator” “developed to explore the impact of
`D2D and WID parameter variations on FMAX and throughput distributions
`
`20
`
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`
`IPR2018-01038
`Patent 8,566,836 B2
`
`for multi-core processors.” Ex. 1005, 51; see also id. at 50, Abstract.
`Dr. August fails to provide any persuasive evidence or argument to explain
`why a POSITA would have understood either (1) that a statistical-
`performance simulator is a multi-core processor or (2) how teachings
`relating to a statistical-performance simulator would apply to an actual
`multi-core processor. All of Dr. August’s opinions relating to how Bowman
`teaches or suggests the limitations of claim 1 are based on his assertion that
`Bowman discloses a multi-core processor. See Ex. 1002 ¶¶ 87–90. Because
`Petitioner has not shown that Bowman discloses a multi-core processor as
`opined by Dr. August, Dr. August’s testimony is not persuasive and entitled
`to little to no weight.
`Second, Dr. August fails to provide persuasive evidence to support his
`opinions as to what a POSITA would have understood from Bowman’s
`disclosure or that Bowman “discloses ‘identifying’ a processing task that can
`not be run across the plurality of cores, and upon this identification,
`‘selecting’ a core from the plurality of cores having a fastest measure
`processing speed parameter at a given voltage to run the processing task.”
`Ex. 1002 ¶ 89 (emphases altered). Notably, paragraph 89 of Dr. August’s
`declaration testimony, where Dr. August opines as to what a POSITA
`“would have understood” from Bowman’s disclosure (as it relates to the
`“identifying” and “selecting” limitations of claim 1), does not contain any
`citations to Bowman. See Ex. 1002 ¶ 89; see also 37 C.F.R. §42.65(a)
`(“Expert testimony that does not disclose the underlying facts or data on
`which the opinion is based is entitled to little or no weight.”); Trial Practice
`Guide Update, page 5, Office Patent Trial Practice Guide, August 2018
`Update, 83 Fed. Reg. 39989 (Aug. 13, 2018) (available at
`
`21
`
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`IPR2018-01038
`Patent 8,566,836 B2
`
`https://go.usa.gov/xU7GP)(“[E]xpert testimony cannot take the place of
`disclosure from patents or printed publications. In other words, expert
`testimony . . . is not a substitute for disclosure in a prior art reference
`itself.”).
`We recognize that other portions of Dr. August’s testimony cite to
`Bowman. See Ex. 1002 ¶¶ 87–88 (citing Ex. 1005, 50 (Abstract, §1), 51
`(§2), 53 (§4)); see also id. ¶ 89 (stating “as described above, Bowman
`teaches that single-threaded applications should be executed on the fastest
`core, while highly parallel multi-threaded applications should be executed
`on multiple cores as the maximum clock frequency of the slowest core”).
`Dr. August, however, does not
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