Trials@uspto.gov
`571-272-7822
`
`Paper No. 21
`Entered: April 29, 2019
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`MEDIATEK INC. and MEDIATEK USA INC., and
`ARM LTD. and ARM, INC.,
`Petitioners,
`
`v.
`
`ADVANCED MICRO DEVICES, INC. and ATI TECHNOLOGIES ULC,
`Patent Owner.
`____________
`
`Case IPR2018-00102
`Case IPR2018-011491
`Patent 7,633,506 B1
` ____________
`
`Before JONI Y. CHANG, BRIAN J. McNAMARA, and
`PAUL J. KORNICZKY, Administrative Patent Judges.
`
`McNAMARA, Administrative Patent Judge.
`
`FINAL WRITTEN DECISION
`35 U.S.C. § 318(a) and
` 37 C.F.R. § 42.73
`
`1 IPR2018-00102 and IPR2018-01149 have been joined. All references in
`this Decision are to Papers and Exhibits in IPR2018-00102, unless otherwise
`noted.
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`IPR2018-00102, IPR2018-01149
`Patent 7,633,506 B1
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`BACKGROUND
`On December 12, 2018, IPR2018-01149 was joined to this IPR2018-
`00102 in which a trial already had been instituted. See ARM Ltd. and ARM
`Inc. v. Advanced Micro Devices, Inc. and ATI Techs., Inc., Case IPR2018-
`01140, slip op. (PTAB Dec. 12, 2018) (Paper 16, Decision to Institute and
`Grant of Motion For Joinder). “Petitioner” refers to MediaTek Inc.,
`MediaTek USA Inc., ARM Ltd., and ARM, Inc., collectively. “Patent
`Owner” refers to Advanced Micro Devices, Inc. and ATI Technologies ULC
`collectively.
`Inter Partes Review: On October 20, 2018, Petitioner filed a Petition
`(“Pet.”) for inter partes review of claims 1–9 of U. S. Patent No. 7,633,506
`B1 (“the ’506 patent”). On April 27, 2018, in IPR2018-00102, we instituted
`an inter partes review of claims 1–9 of the ’506 patent on all grounds
`asserted in the Petition. Paper 14 (“Dec. to Inst.”). Patent Owner filed a
`Patent Owner Response. Paper 17 (“PO Resp.”). Petitioner filed a
`Petitioner Reply. Paper 28 (“Pet. Reply”). Patent Owner filed a Sur-Reply.
`Paper 35 (“PO Sur-reply”).
`Motion to Amend: Patent Owner filed a Contingent Motion to
`Amend. Paper 18 (“Mot. To Amend”). Petitioner filed an Opposition to
`Patent Owner’s Motion to Amend. Paper 29 (“Opp. To Mot. To Amend”).
`Patent Owner filed a Reply to Petitioner’s Opposition to its Motion to
`Amend. Paper 34 (“Reply to Opp. To Mot. To Amend”). Petitioner filed a
`Sur-reply. Paper 41 (“Pet. Sur-Reply to Mot. To Amend”).
`Motion to Exclude Evidence: Patent Owner filed a Motion to Exclude
`Evidence. Paper 40 (“Mot. To Exclude”). Petitioner filed a Response.
`Paper 42 (“Resp. To Mot. To Exclude”).
`
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`We have jurisdiction under 35 U.S.C. § 6. This Final Written
`Decision is issued pursuant to 35 U.S.C. § 318(a). We base our decision on
`the preponderance of the evidence. 35 U.S.C. § 316(e); 37 C.F.R. § 42.1(d).
`A transcript of an oral hearing held on January 22, 2019, (Paper 47, “H’rg.
`Tr.”) has been entered into the record.
`Having reviewed the arguments of the parties and the supporting
`evidence, we conclude that Petitioner has demonstrated by a preponderance
`of the evidence that the challenged claims are unpatentable. We also deny
`Patent Owner’s Motion to Amend.
`
`THE ’506 PATENT (EXHIBIT 1001)
`According to the ’506 patent, a three dimensional (3D) image
`typically is displayed on a two dimensional array of pixels using a plurality
`of graphical objects, such as points, lines, and polygons, known as primitives
`that are the basis of most rendering instructions. Ex. 1001, 1:45–50. Visible
`primitives that are part of a scene are drawn individually by determining
`those pixels falling within the edges of the primitives and obtaining
`attributes that correspond to each of the pixels to determine the displayed
`color value of the applicable pixels. Id. at 1:52–60. The final displayed
`color of an individual pixel may be a blend of colors from multiple surfaces
`or layers. Id. at 1:65–67. A blending function based on an opacity value
`associated with each pixel of each primitive can be used to blend colors of
`overlapping surfaces or layers when the top surface is not completely
`opaque. Id. at 1:61–65. 3D image data represents attributes such as color,
`opacity, texture, depth, and perspective information. Id. at 2:5–6. Graphics
`processing is the execution of draw commands that may include X and Y
`coordinates for the vertices of the primitive, as well as attribute parameters
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`for the primitive (color and depth or “Z” data) to generate a display image.
`Id. at 2:6–11.
`According to the ’506 patent, a graphics chip designed to carry out
`instruction processing to render graphics on a screen typically has a front-
`end and a back-end. Ex. 1001, 2:19–20. The front-end receives graphics
`instructions and generates geometry defining primitives or combinations of
`primitives that are processed by the back-end, where they might be textured,
`shaded, colored, or otherwise prepared for final output. Id. at 2:20–26.
`When back-end processing of primitives is complete, each pixel in the
`screen has a specific number value that defines a unique color attribute the
`pixel will have when drawn. Id. at 2:26–29. That final value is kept in a
`frame buffer for use at an appropriate time. Id. at 2:29–31. Systems have
`become more complex to accommodate three-dimensional (3D) data,
`requiring a 256-bit system that processes 512 bits in a single logic cycle. Id.
`at 2:32–40. The use of data words with a 256-bit frame buffer is a challenge
`for the input/output (I/O) system used by the graphics processing back-end
`because granularity may be too coarse. Id. at 2:40–45.
`In the ’506 patent, geometry representative data presented to the
`back-end of the graphics chip is divided into data words and provided to one
`or more parallel pipelines. Id. at 2:55–60. The display screen is divided into
`tiles and a portion of the display screen defined by one or more tiles is
`serviced by a pipeline. Id. at 2:60–64, Fig. 3. Work is allocated to pipelines
`based on a repeating square pixel tile pattern. Id. 5:23–25. The tiling
`pattern is based on the number of active pipelines. Id. at 5:50–51. As
`shown in Figure 5, logic 520 in set-up unit 515 intersects graphics primitives
`with the repeating tile pattern, such that a primitive is sent to a pipeline only
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`if it is likely to result in generation of covered pixels. Id. at 5:25–28. Set-up
`unit 515 creates a bounding box based on X, Y coordinates for each vertex
`of a polygon and the bounding box is compared to the tile pattern and
`mapped to one or more pipelines. Id. at 5:51–67.
`Each parallel pipeline comprises a raster back-end having (i) a scan
`converter to step through the geometric patterns passed to the back end, (ii) a
`“hierarchical-Z” component to define the borders of the geometry more
`precisely, (iii) a “Z-buffer” for performing three dimensional operations of
`the data, (iv) a rasterizer for computing texture addresses and color
`components for a pixel, (v) a unified shader for combining multiple
`characteristics for a pixel and outputting a single value, and (vi) a color
`buffer logic unit for taking the incoming shader color and blending it into the
`frame buffer using the current frame buffer blend operations. Id. at 2:65–
`3:8, Fig. 5.
`
`ILLUSTRATIVE CLAIM
`Claim 1, with claim element designations used in the Petition shown
`in brackets, is reproduced below:
`1. [preamble] A graphics chip comprising:
`[a] a front-end in the graphics chip configured to receive one
`or more graphics instructions and to output a geometry;
`[b] a back-end in the graphics chip configured to receive said
`geometry and to process said geometry into one or more
`final pixels to be placed in a frame buffer;
`[c] wherein said back-end in the graphics chip comprises
`multiple parallel pipelines;
`[d] wherein said geometry is determined to locate in a portion
`of an output screen defined by a tile; and
`[e] wherein each of said parallel pipelines further comprises
`a unified shader that is programmable to perform both
`color shading and texture shading.
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`GROUNDS OF INSTITUTION
`In our Decision to Institute, we instituted trial on the following
`challenges to patentability (which were all of the grounds asserted):
`Claims 1–9 as unpatentable under 35 U.S.C. § 103 over Rubinstein2 in
`view of Collodi3, and
`Claims 8–9 as unpatentable under 35 U.S.C. § 103 over Rubinstein, in
`view of Collodi, and in further view of Zatz.4
`CLAIM CONSTRUCTION
`In our Decision to Institute, we applied the ordinary and customary
`meaning to the terms not construed. We applied the broadest reasonable
`interpretation to the following terms that required construction:
`Z-buffer logic unit
`In our Decision to Institute, we construed “Z-buffer logic unit” to
`mean “a logic unit that facilitates visibility testing by comparing depth
`values.” Dec. to Inst. 8. The parties do not dispute the substance of our
`construction of this term.
`Hiererchical Z-interface
`In our Decision to Institute, we construed “Hierarchical Z-interface”
`to mean “an interface with a z-buffer logic unit that provides for visibility
`testing at a coarse level, including, for example, for an entire tile or
`primitive.” Dec. to Inst. 8–9. The parties do not dispute the substance of
`our construction of this term.
`
`
`2 U.S. Patent No. 7,102,646 B1, issued September 5, 2006 (Ex. 1004).
`3 U.S. Patent Appl. Publ. No. 2003/0076320 A1, published April 24, 2003
`(Ex. 1007).
`4 U.S. Patent No. 6,809,732 B2, issued October 26, 2004.
`6
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`Early Z-interface and late Z-interface
`In our Decisions to Institute, we construed “early Z-interface” to mean
`“an interface with a z-buffer logic unit that provides for visibility prior to
`shading and texturing.” We construed the term “late Z-interface” to mean
`“an interface with a z-buffer logic unit that provides for visibility testing
`after shading and texturing. Dec. to Inst. 9–10. The parties do not dispute
`the substance of our construction of these terms.
`Graphics Chip
`Neither party proposed a construction of “graphics chip” prior to our
`Decision to Institute. The Petition states that the preamble of claim 1 is not
`limiting because the term “graphics chip” does not describe an essential
`structure or step. Pet. 34. Petitioner argues that “to the extent the Board
`finds the preamble is limiting,” the “graphics chip” requires only “a system
`with one or more chips for graphics processing.” Id. at 35. Patent Owner
`argues that whether or not the preamble is limiting, “the body of the claim
`requires that the claimed elements be on the same graphics chip.” PO Resp.
`24. Therefore, Patent Owner proposes that the broadest reasonable
`interpretation of “graphics chip” in the context of the front-end is the same
`graphics chip in the context of the back-end, necessitating that the invention
`in the challenged claims of the ’506 patent exists on a single graphics chip.
`Id. at 25. Petitioner responds that the ’506 patent refers to a “graphics
`system” or “graphics chips” in the plural, that the invention is never
`described in the Specification as consisting of a single graphics chip, and
`that Patent Owner cites only to specific embodiments of the purported
`invention. Pet. Reply 10 (citing Ex. 1001, Abstract, 1:16, 2:49–55, 2:65–
`3:6, 3:54, 3:62–63, 4:27–32).
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`The preamble of claim 1 provides antecedent basis for the claim
`limitations “a front-end in the graphics chip” and a “back-end in the graphics
`chip.” Noting that when complex graphics are desired in computers
`additional, components or chips are added to assist with complex
`instructions to render graphics on a screen, the Specification states
`“[g]raphics chips may be considered as having a front-end and a back-end,”
`and that “[t]he front-end typically receives graphics instructions and
`generates the primitives or combinations of primitives that define geometric
`patterns,” and “primitives are processed in the back-end where they might be
`textured, shaded, colored, or otherwise prepared for final output.” Ex. 1001,
`1:30–31, 2:19–26. The Specification further states that “[t]he present
`invention relates to a parallel array graphics system” that “includes a
`back-end configured to receive primitives and combinations of primitives
`(i.e., geometry) and process the geometry to produce values to pace in a
`frame buffer” (id. at 2:49–54) and relative to Figure 5 describes “An
`Embodiment of a Back-End Graphics Chip” (id. at 4:67–7:14).
`Although the antecedents in claim 1 appear to indicate the claim is
`drawn to a single graphics chip, the description in the ’506 patent of a
`back-end graphics chip as a separate entity indicates that the distinction
`between a single graphics chip and the implementation of a graphics system
`using multiple chips is not material for purposes of deciding obviousness in
`this Decision.
`Unified Shader
`(a) The ITC construction
`After the Petition was filed, in a parallel proceeding at the
`International Trade Commissions (ITC), the Administrative Law Judge
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`(“ALJ”) construed a “unified shader” to be one that performs both color
`shading and “texture coordinate shading.” PO Resp. 13–14. Patent Owner
`notes that the Commission’s Notice of Review proposed the following, even
`more limited, construction for “unified shader:”
`a single shader circuit capable of performing color shading and
`texture coordinate shading, wherein the single shader circuit
`may not include separate dedicated hardware blocks that perform
`separate color and texture operations, and wherein texture
`coordinate shading may include texture address operations,
`indirect texturing, and bump mapping performed by the unified
`shader to modify texture coordinates.
`Id. at 14 (citing Ex. 2008, 3) (emphasis in PO Resp.). According to Patent
`Owner, our Decision to Institute did not consider the ALJ’s construction
`adequately and Patent Owner urges that we now also consider the
`Commission’s construction. Id.
`Our Decision to Institute included an extensive discussion of the ITC
`ALJ’s construction. Dec. to Inst. 11–15. For example, we noted that in
`addition to “unified shader,” the ALJ construed the function actually recited
`in claim 1, i.e., “texture shading,” to have its plain and ordinary meaning,
`which the ALJ stated is “texture shading operations including coordinate
`texture mapping and texture address operations.” Id. at 12 (citing Ex. 1009,
`5–6 (17:12–18:3)). Noting that the ALJ’s construction of “texture shading”
`includes two terms that are not otherwise defined, i.e. “coordinate texture
`mapping” and “texture address operations,” we were not persuaded that we
`could apply the ALJ’s construction in this proceeding. We also noted that
`the ITC staff and Patent Owner proposed “unified shader” be construed
`differently in the context of other patents in the ITC proceeding (U.S. Patent
`No. 8,760,454 (“the ’454 patent”) and U.S. Patent No. 9,582,846 (“the ’846
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`patent”), i.e., to mean “a single shader circuit configured to perform both
`vertex and pixel operations.” Id. at 14 (citing Ex. 2003, 10). In view of the
`undefined terms and the ITC staff’s different constructions of unified shader
`in the context of different patents, we could not determine an ordinary and
`customary meaning of the terms “texture shading” or “unified shader.” Id.
`14–15.
`The construction in the Commission’s Notice of Review cited by
`Patent Owner also does not provide guidance necessary for this proceeding.
`The following terms in the construction articulated in the Commission’s
`Notice of Review are not used or defined anywhere in the text of the ’506
`patent: texture coordinate shading, texture address operations, indirect
`texturing, bump mapping, and modify texture coordinates. See Ex. 2008.
`These terms appear in the U.S. Patent No. 7,796,133 B1 (“the ’133 patent”),
`the application that purportedly was incorporated by reference into the ’506
`patent. As much of the construction applied by the ITC and proposed by
`Patent Owner comes from disclosure in the related ’133 patent, we analyze
`the incorporation by reference below.
`Furthermore, although we have considered the findings of fact and
`conclusions reached by the ITC, we are not bound by them. See Nobel
`Biocare Servs. AG v. Instradent USA, Inc., 903 F.3d 1365, 1375 (Fed. Cir.
`2018) (noting the Federal Circuit is not bound by its prior affirmance of an
`ITC decision when reviewing a final written decision of the Board because
`“[a]s the Board correctly observed, the evidentiary standard in its
`proceedings, preponderance of the evidence, is different from the higher
`standard applicable in ITC proceedings, clear and convincing evidence”).
`Here, in the instant Final Written Decision, we have made an independent
`
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`determination of claim construction and patentability of the challenged
`claims based on the parties’ contentions, the specific evidence presented in
`this proceeding, and the standards applicable to inter partes review
`proceedings.
` Incorporation by reference of the ’133 patent
`Patent Owner argues that the ’506 patent includes a definition of a
`unified shader, i.e., “the claimed unified shader must be capable of
`performing both color shading and texture coordinate/address shading,” as
`“already identified by the ALJ, OUII, and the ITC Commission in the
`corresponding ITC investigation.” PO Resp. 1. Patent Owner’s reliance on
`the ITC construction reflects an argument that incrementally incorporates
`into the construction of “unified shader” features that are not found in the
`literal text of the ’506 patent. Claim 1 recites that the unified shader
`performs “texture shading.” Patent Owner cites the ’506 patent
`Specification to assert that the ’506 patent specifically defines the unified
`shader to require a single shader circuit that can perform both color shading
`and texture address shading. PO Resp. 15 (citing Ex. 2010 (Pfister Dep.
`8:10–20)); see also, Ex. 1001, 6:45–54 (“A unified shader is so named
`because the functions of a traditional color shader and a traditional texture
`address shader are combined into a single unified shader. The unified shader
`performs both color shading and texture address shading.”). Although the
`’506 patent does not use the term “texture coordinate shading,” Patent
`Owner next relies on the disclosure of texture addresses and texture
`coordinates in the ’506 patent and a purported incorporation by reference of
`the application that led to issuance of the ’133 patent to argue that the ’506
`patent equates texture address shading with texture coordinate shading. Ex.
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`1001, 6:60–63, 11:15–16. Patent Owner then relies on the ’133 patent and
`the ITC’s construction to further limit the construction of “unified shader” in
`the ’506 patent to a shader that performs texture coordinate shading that may
`include texture address operations, indirect texturing, and bump mapping
`performed by the unified shader to modify texture coordinates. PO Resp.
`14. None of these functions are described in the ’506 patent. Even the
`Commission’s construction of a “texture coordinate shader” states that
`texture coordinate shading may include these functions, but it does not
`require them. See Ex. 2008, 3.
`The issue of whether the ’506 patent properly incorporated the ’133
`patent by reference came to the Board’s attention in the context of Patent
`Owner’s Motion to Amend. H’rg. Tr. 14:18–15:6. We address Patent
`Owner’s Motion to Amend later in this Decision. For purposes of this
`discussion, we note that although Patent Owner’s Motion to Amend
`proposes to amend claim 1 to recite “texture coordinate shading” explicitly
`(see Opp. To Mot. To Amend 29, 1), Patent Owner urges us to construe
`“texture shading” in the context of the unified shader in unamended claim 1
`to mean “texture coordinate shading.” PO Resp. 15–19.
`U.S. Patent Application 10/724,384 (“the ’384 application”) that
`matured into the ’506 patent was filed in November 26, 2003. Ex. 1001,
`cover page. As to the “unified shader,” the ’384 application stated:
`A unified shader is so named because the functions of a
`traditional color shader and a traditional texture address shader
`are combined into a single, unified shader. The unified shader
`performs both color shading and texture address shading. The
`conventional distinction between shading operations (i.e., color
`texture map and coordinate texture map or color shading
`operation and texture address operation) is not handled by the use
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`of separate shaders. In this way, any operation, be it for color
`shading or texture shading, may loop back into the shader and be
`combined with any other operation.
`The functionality of a unified shader is further described in
`commonly owned co-pending U.S. Patent Application entitled
`“Unified Shader”, with serial number 10/xxx,xxx, filed
`December XX, 2003, and is hereby fully incorporated by
`reference.
`Ex. 1017, 307. Thus, as originally filed, the application that matured into
`the ’506 patent did not describe the functionality of the unified shader (other
`than to state it performs color shading and texture address shading), but
`instead sought to incorporate that description by reference to an application
`that had not been filed and could not be identified.5 Patent Owner took no
`action to address this issue until filing an Office Action Response on July
`10, 2007, when Patent Owner amended the Specification’s description of the
`unified shader to identify U.S. Patent Application 10/730,965 filed
`December 8, 2003 (“the ’965 application”) as the referenced application.
`Ex. 1017, 252.
`The ’965 application, which matured into the ’133 patent, is identified
`as a continuation of abandoned U.S. Patent Application No. 10/716,946 filed
`
`
`5 Similarly, in its description of set-up unit 515, the scan converter and
`hierarchical Z interface, and the scan converter and Early Z interface, the
`originally filed ’384 application that matured into the ’506 patent stated that
`“the functionality” of each device “is further described in commonly owned
`co-pending U.S. Patent Application entitled ‘Scalable Rasterizer
`Interpolator’, with serial number 10/xxx,xxx, filed December XX, 2003, and
`is hereby fully incorporated by reference.” Ex. 1017, 305, 306. In an
`amendment filed on July 7, 2007, Patent Owner amended the Specification
`to change this incorporation by reference to identify Application No.
`10/730,864 (“the ’864 application”), filed December 8, 2003. Id. at 251–
`252.
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`on November 18, 2003 (“the ’946 application”), i.e., several days before the
`November 26, 2003 filing date of the ’384 application that matured into the
`’506 patent. See Ex. 2003. Although the ’946 application has not been
`made of record in this proceeding, as a continuation application, the ’965
`application that matured into the ’133 patent would have been the same as
`the abandoned ’946 application. A review of Patent Office records indicates
`that before the Office took any action concerning it, the ’946 application was
`abandoned on February 4, 2004, several weeks after the ’965 application
`was filed. We are not aware of any explanation in the record concerning
`why the ’946 application was abandoned and the ’965 application was filed
`in its place.
`Figures 9–15 and the corresponding subject matter that appears in the
`’506 patent beginning at column 9, line 27 through column 14, line 20 were
`not included in the ’384 application as filed on November 26, 2003. See Ex.
`1017, 312. Thus, the ’384 application as originally filed did not include the
`’506 patent text under the headings “Unified Shader,” “Unified (Pixel)
`Shader Architecture,” “Shader Code Partitioning,” “Control Logic,”
`“Register Subsystem,” “Multiple Shaders,” and “ALU I/O Description.” See
`Ex. 1001, 9:27–14:20.
`On March 31, 2008, Patent Owner filed “a Substitute Specification
`that includes subject matter of a co-pending application (serial no.
`10/730,965) that was incorporated by reference in its entirety in the
`originally filed application.” Ex. 1017, 126. As discussed above, the subject
`matter was not incorporated by reference in the originally-filed application
`because Patent Owner did not identify a specific application to be
`incorporated by reference. See 37 C.F.R. § 1.57(c). Indeed, the ’384
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`application that matured into the ’506 patent included three separate
`incorporation by reference assertions in the form of application “10/xxx,xxx,
`filed on Dec. XX, 2003” and Patent Owner’s July 10, 2007 amendment
`incorporated two different applications by reference, i.e., the ’965
`application concerning the unified shader and the ’864 application
`concerning the set-up unit, scan converter, and the Early and Hierarchical Z
`interfaces. The existence of the subject matter to be incorporated by
`reference is irrelevant until Patent Owner actually identifies the subject
`matter to be incorporated. See id., Pet. Reply to Opp. to Mot. to Amend 4.
`Identification of the application to be incorporated by reference occurred
`years after the original filing date, i.e., on July 10, 2007 at the earliest.
`The Substitute Specification filed on March 31, 2008, added Figures
`9–15 and the corresponding description, but did not import into the ’384
`application (now the ’506 patent) the literal text using the term “texture
`coordinate shading” or include other material from the ’965 application
`(now the ’133 patent), e.g., discussions of “indirect texturing,” and “bump
`mapping.” There is no evidence that this issue was brought to the attention
`of the ITC.
`(b) The description of “unified shader” in the ’506 patent
`In our Decision to Institute, we declined to construe the term “unified
`shader” by itself. Dec. to Inst. 10–25. Rather than construe this term out of
`the context of the claims, we preliminarily construed the entire phrase
`“unified shader that is programmable to perform both color shading and
`texture shading” to mean “a processing mechanism that through an interface
`receives packets from a rasterizer and has at least one ALU/memory pair
`that can be programmed to adjust the color of a pixel, and issue a texture
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`request to a texture unit or write received texture values to a memory, and
`outputs resultant values to a frame buffer.” Id. at 25 (emphasis omitted).
`Our construction recognized that the recited limitation includes several
`elements: (i) unified shader; (ii) color shading, and (iii) texture shading.
`We turn first to the “unified shader” portion of the limitation. Our
`construction of the “unified shader” portion of this term is based, in part, on
`the following description of a “unified shader” in the ’506 patent
`Specification as amended on March 31, 2008:
`One embodiment of a unified shader is shown in the block
`diagram of FIG. 9. Unified shader 1100 performs per-pixel
`shading calculations on rasterized values that are passed from a
`rasterizer unit 1110. The results of the calculations are sent to
`frame buffer 1120. As part of the calculation performed by
`unified shader 1100, a texture unit 1130 may receive texture
`lookup requests from the shader 1100. The actual shading
`algorithm used may vary and may be defined by a set of
`instructions, such as microcode instructions.
`Ex. 1001, 9:36–44.
`Patent Owner proposes that we construe “unified shader” to “include
`‘a single shader circuit capable of performing color shading and texture
`coordinate shading.’” PO Resp. 18. Patent Owner’s proposed construction
`is highly functional and introduces at least the following uncertainties: (i) it
`leaves open to question what makes up the shader circuit, rendering the term
`“shader circuit” a nonce term; (ii) it changes the claim term “texture
`shading” to “texture coordinate shading”—thus, on its face, Patent Owner
`proposes further limiting the claim to a particular type of texture shading,
`i.e., texture coordinate shading; and (iii) it does not define either “texture
`shading” or “texture coordinate shading,” thereby providing no insight into
`the functional being performed. In view of these uncertainties, Patent
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`IPR2018-00102, IPR2018-01149
`Patent 7,633,506 B1
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`Owner’s proposed construction provides no basis upon which we can
`interpret the metes and bounds of the claim.
` Petitioner agrees with Patent Owner that we should not import into
`the definition of unified shader the structural requirements that the
`processing mechanism “through an interface receives packets from a
`rasterizer and has at least one ALU/memory pair,” and “outputs resultant
`values to a frame buffer.” Pet. Reply 2, 7–10. The only structural
`limitation on the unified shader itself in this preliminary construction is that
`it includes at least one ALU/memory pair. See Ex. 1001, 9:45–10:40; Fig.
`10. The remaining portions of this preliminary construction concern inputs
`(i.e., packets from a rasterizer) to and outputs (resultant values to a frame
`buffer) from the unified shader. Petitioner also proposes that we simplify
`the “texture shading” element of claim 1 to mean “issue a texture request or
`receive texture information in response to that request.” Pet. Reply 9. Thus,
`Petitioner proposes we construe “unified shader” as a “processing
`mechanism that can be programmed to adjust the color of a pixel and issue a
`texture request or receive texture information in response to that request.”
`Id. at 10 (emphasis omitted).
`Like Patent Owner’s proposed construction, Petitioner’s proposed
`construction is highly functional and proposes no structure for the unified
`shader, other than it is a “processing mechanism” programmed to perform
`certain functions, i.e. issue a texture request and receive texture information
`in response to that request. As compared to the ’506 patent’s description of
`operations 5 and 6 performed by the unified shader architecture shown in
`Figure 10 discussed below, Petitioner’s proposed construction substitutes
`“texture request” for the term “texture address” and “texture information”
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`IPR2018-00102, IPR2018-01149
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`for “texture value.” See Ex. 1001, 10:15–19. Petitioner’s proposal is
`consistent with the ’506 patent’s description of operations issuing a texture
`address as “texture requests” and receiving in the SRAMs returned “texture
`data.” Id. at 10:15–20.
`Petitioner notes that defining a particular claim term by its function is
`not improper. Pet. Reply. 8 (citing Hill-Rom Svcs., Inc. v. Stryker Corp.,
`755 F.3d 1367, 1374-75 (Fed. Cir. 2014)). In this case, however, the claim
`itself recites the particular function, i.e., “unified shader that is
`programmable to perform both color shading and texture shading.” Further
`construing “unified shader” by the function it performs is either redundant or
`contradictory to the recited function. That the unified shader is
`programmable to perform both color shading and texture shading begs the
`question as to what constitutes the unified shader, other than a “circuit” as
`Patent Owner proposes, or a “processing mechanism” as Petitioner proposes.
`The term “unified shader” is not used consistently in the
`Specification. The Specification describes Figure 9 as “a block diagram of a
`unified shader according to an embodiment of the present invention.” Ex.
`1001, 3:37–38, 9:36–37. The implication from this description of Figure 9
`is that the elements of Figure 9 taken together make up at least one
`embodiment of the claimed unified shader. Figure 9 includes four elements:
`(i) rasterizer block 1110, shown