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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`SAMSUNG ELECTRONICS CO., LTD. AND SAMSUNG ELECTRONICS
`AMERICA, INC.
`Petitioner
`
`v.
`
`INVENSAS CORPORATION
`Patent Owner
`
`____________________
`
`U.S. Patent No. 6,054,336
`____________________
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 6,054,336
`
`
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,054,336
`
`TABLE OF CONTENTS
`Contents
`INTRODUCTION ........................................................................................... 1
`I.
`II. MANDATORY NOTICES UNDER 37 C.F.R ............................................... 2
`III. PAYMENT OF FEES UNDER 37 C.F.R ....................................................... 4
`IV. GROUNDS FOR STANDING ........................................................................ 4
`V.
`PRECISE RELIEF REQUESTED .................................................................. 4
`VI. OVERVIEW OF THE RELEVANT TECHNOLOGY .................................. 5
`VII. THE ’336 PATENT ....................................................................................... 10
`A.
`The Patent Specification ...................................................................... 10
`B.
`Prosecution History ............................................................................. 14
`VIII. LEGAL STANDARDS ................................................................................. 15
`A.
`Claim Construction ............................................................................. 15
`B.
`Level Of Ordinary Skill In The Art ..................................................... 16
`IX. OVERVIEW OF PRIOR ART ...................................................................... 16
`A. U.S. Patent No. 5,428,231 (“Tanaka”) (Ex-1006) .............................. 16
`B. U.S. Patent No. 5,847,460 (“Liou”) (Ex-1005) .................................. 23
`EXPLANATION OF GROUNDS FOR INVALIDITY ............................... 28
`A. Ground 1: Tanaka Anticipates Challenged Claims 1-3 ...................... 28
`1.
`Claim 1 ...................................................................................... 30
`2.
`Claim 2 ...................................................................................... 53
`3.
`Claim 3 ...................................................................................... 54
`B. Ground 2: Tanaka In View Of Knowledge Of A POSA Renders
`Obvious Challenged Claims 1-3 ......................................................... 55
`
`X.
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`i
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`

`

`Petition for Inter Partes Review
`Patent No. 6,512,298
`C. Ground 3: Tanaka In View Of Liou Renders Obvious
`Challenged Claims 1-3 ........................................................................ 59
`1. Motivation To Combine Tanaka And Liou .............................. 59
`2.
`Claim 1 ...................................................................................... 67
`3.
`Claims 2-3 ................................................................................. 73
`XI. SECONDARY CONSIDERATIONS OF NON-OBVIOUSNESS .............. 73
`XII. CONCLUSION .............................................................................................. 74
`
`ii
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`Petition for Inter Partes Review
`Patent No. 6,054,336
`
`LIST OF EXHIBITS
`U.S. Patent No. 6,054,336 (“the ’336 Patent”)
`Declaration of Dr. Miltiadis Hatalis
`Curriculum Vitae for Dr. Miltiadis Hatalis
`Prosecution File History of U.S. Patent No. 6,054,336
`U.S. Patent No. 5,847,460 (“Liou”)
`U.S. Patent No. 5,428,231 (“Tanaka”)
`Nakamura et al., “A Single-Layer Metal-Electrode CCD Image
`Sensor,” Digest of technical papers of the 1995 IEEE
`International Solid-State Circuits Conference, pp. 222-223.
`Ben G. Streetman, Solid State Electronic Devices (Prentice Hall
`1995)
`Ted Kamins, Polycrystalline Silicon for Integrated Circuit
`Applications (Springer 1988)
`W. Maly, Atlas of IC technologies: An Introduction to VLSI
`Processes (Benjamin/Cummings 1987)
`Sorab K. Ghandhi, VLSI Fabrication Principles (Wiley 1983)
`
`1001
`1002
`1003
`1004
`1005
`1006
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`iii
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`

`

`Petition for Inter Partes Review
`Patent No. 6,054,336
`
`I.
`
`INTRODUCTION
`Samsung Electronics Co., Ltd. and Samsung Electronics America, Inc.
`
`(collectively “Samsung”) request inter partes review (“IPR”) of Claims 1-3 of U.S.
`
`Patent No. 6,054,336 (“the ’336 Patent”; Ex-1001), assigned to Invensas
`
`Corporation (“Patent Owner”).
`
`The ’336 Patent claims a semiconductor fabrication process that uses
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`“spacers” to form conductor patterns having dimensions smaller than those that can
`
`be formed using lithography and masks. Ex-1001, Claim 1. During prosecution,
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`the applicant argued that Claim 1’s combination of steps — including forming
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`spacers by etching “auxiliary windows” in a “first dielectric layer,” adding a
`
`“second layer,” “anisotropic etching of this second layer” to form spacers, and then
`
`using the spacers to form “very narrow conductor tracks” — taught over the prior
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`art cited by the Examiner. Ex-1004, 65-72.1 The Examiner accepted these
`
`arguments and allowed the claims. Id., 73-76.
`
`However, the ’336 Patent’s combination of steps for using spacers to create
`
`conductive patterns with small dimensions was known before the ’336 Patent’s
`
`priority date of May 29, 1997. For example, these steps were disclosed in prior art
`
`
` 1
`
` All citations to Ex-1004 are to the repaginated page numbers applied to the File
`
`History by Samsung.
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`1
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`Petition for Inter Partes Review
`Patent No. 6,054,336
`references, U.S. Patent No. 5,428,231 (“Tanaka”) and U.S. Patent No. 5,847,460
`
`(“Liou”), that the PTO did not consider during prosecution. This Petition
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`accordingly presents grounds of invalidity based on Tanaka and Liou. These
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`grounds are each likely to prevail, and this Petition, accordingly, should be granted
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`on all grounds ultimately resulting in cancellation of the challenged claims. The
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`petition is further supported by the Declaration of Dr. Miltiadis Hatalis, an expert
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`in the semiconductor manufacturing processes claimed by the ’336 Patent.
`
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8
`Real Parties-in-Interest: Samsung identifies the following real parties-in-
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`interest: Samsung Electronics Co., Ltd. and Samsung Electronics America, Inc.
`
`Related Matters: Patent Owner has asserted that Samsung infringes the
`
`’336 Patent in a district court action, Invensas Corp. v. Samsung Electronics
`
`America, Inc., and Samsung Electronics Co., Ltd., Civ. No. 2:17-cv-00670-RWS-
`
`RSP (E.D. Tex.).
`
`Lead and Back-Up Counsel:
`
`Pursuant to 37 C.F.R. § 42.8(b)(3), Samsung identifies the following lead
`
`and back-up counsel:
`
`Lead Counsel
`
`SAMSUNG’S LEAD AND BACK-UP COUNSEL
`Brian M. Berliner (Reg. No. 34,549)
`Email: bberliner@omm.com
`O’Melveny & Myers LLP
`
`2
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,054,336
`
`Back-Up Counsel
`
`SAMSUNG’S LEAD AND BACK-UP COUNSEL
`400 South Hope Street, 18th Floor
`Los Angeles, CA 90071
`Telephone: (213) 430-6000
`Fax: (213) 430-6407
`
`Ryan Yagura (Reg. No. 47,191)
`Email: ryagura@omm.com
`Nicholas Whilt (Reg. No. 72,081)
`Email: nwhilt@omm.com
`
`
`O’Melveny & Myers LLP
`400 South Hope Street, 18th Floor
`Los Angeles, CA 90071
`Telephone: (213) 430-6000
`Fax: (213) 430-6407
`
`John Kappos (Reg. No. 37,861)
`O’Melveny & Myers LLP
`610 Newport Center Drive, 17th Floor
`Newport Beach, California 92660
`Telephone: 949-823-6900
`Fax: 949-823-6994
`Email: jkappos@omm.com
`
`Mark Liang (Reg. No. L1031)
`O’Melveny & Myers LLP
`2 Embarcadero Ctr., 28th Floor
`San Francisco, California 94111
`Telephone: 415-984-8700
`Fax: 415-984-8701
`Email: mliang@omm.com
`
`
`
`
`Service Information: Samsung may be served at the addresses provided
`
`above for lead and back-up counsel. Samsung consents to electronic service at the
`
`3
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`

`

`Petition for Inter Partes Review
`Patent No. 6,054,336
`address: INVENSASSAMSUNGTX17670OMM@omm.com.
`
`III. PAYMENT OF FEES UNDER 37 C.F.R. § 42.15(a)
`In accordance with 37 C.F.R. § 42.103(a), the Office is authorized to charge
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`an amount in the sum of $30,500 to Deposit Account No. 50-2862 for the fee set
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`forth in 37 C.F.R. § 42.15(a), and any additional fees that may be due.
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`IV. GROUNDS FOR STANDING
`Pursuant to 37 C.F.R. § 42.104(a), Samsung certifies that the ’336 Patent is
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`available for inter partes review and that Samsung is not barred or otherwise
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`estopped from requesting inter partes review on the grounds identified herein.
`
`V.
`
`PRECISE RELIEF REQUESTED
`Samsung respectfully requests review of Claims 1-3 (the “Challenged
`
`Claims”) of the ’336 Patent, and cancellation of these claims, based on the grounds
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`listed below.
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`• Ground 1: Claims 1-3 are anticipated under 35 U.S.C. § 102 by Tanaka;
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`• Ground 2: Claims 1-3 are obvious under 35 U.S.C. § 103 over Tanaka;
`
`• Ground 3: Claims 1-3 are obvious under 35 U.S.C. § 103 over Tanaka
`
`and Liou.
`
`4
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`Petition for Inter Partes Review
`Patent No. 6,054,336
`VI. OVERVIEW OF THE RELEVANT TECHNOLOGY2
`The ’336 Patent is directed to forming conductive gates or electrodes in
`
`charge coupled devices (CCDs) and similar semiconductor devices. Ex-1001, 3:4-
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`18. In these devices, it is desirable to minimize the distance or gap between
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`adjacent conductive gates or electrodes because this improves the efficiency of
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`transferring electrical charges from a region under one gate to the region under a
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`neighboring gate. Ex-1008, p. 359. Accordingly, the ’336 Patent states that its
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`object is to “provide conductors at very small distances from one another when
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`electronic circuits, for example integrated circuits, are manufactured.” Ex-1001,
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`Abstract.
`
`Ordinarily, features such as electrodes and gaps between them in a
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`semiconductor device are defined by lithography, which uses light to first transfer
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`a pattern to a resist layer formed on a conductive material. The resist then acts as a
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`protective mask during etching, so only portions of the conductive material not
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`covered by the resist are removed. The conductive material protected by the resist
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`is not removed and forms an electrode pattern that resembles the pattern formed
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`earlier on the resist layer. However, the minimum size of a feature, such as a gap
`
`between electrodes, formed by lithography depends upon the available lithography
`
`
` 2
`
` This section is supported by Ex-1002, ¶¶24-32.
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`5
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`Petition for Inter Partes Review
`Patent No. 6,054,336
`technology. It is desirable in certain devices such as CCDs to form features
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`smaller than those defined by the available lithography.
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`The specification identifies an article by Nakamura et al., published in the
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`Digest of technical papers of the 1995 IEEE International Solid-State Circuits
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`Conference, as describing one known prior art method for manufacturing patterns
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`of electrodes having gaps that are smaller than the minimum gaps defined by
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`lithography. Id., 1:26-30. According to the ’336 Patent, Nakamura’s method
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`discloses forming conductor gates of a CCD having narrow gaps by using a “side-
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`wall” technology. Id., 1:26-34; Ex-1007, 222. As depicted in Figure 5a of
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`Nakamura below, the relevant aspects of Nakamura’s method begins with a
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`“conductor layer . . . formed by a WSi [tungsten silicide] layer” (orange) that is
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`“covered with a silicon oxide layer” (blue), where both layers are formed on an
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`insulating substrate comprising a silicon substrate (green) and a gate insulator (not
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`colored). Ex-1001, 1:30-34; see also Ex-1007, 222.
`
`
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`Petition for Inter Partes Review
`Patent No. 6,054,336
`In addition, in Figure 5a, “[a]uxiliary windows” (labeled in pink) “are
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`provided in the oxide layer at the areas of the gaps between the gates to be formed
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`for this purpose” and the “oxide layer is etched throughout its entire thickness, so
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`that the WSi layer lies exposed in the auxiliary windows.” Ex-1001, 1:33-39; see
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`also Ex-1007, 222. Further, “mask windows of reduced dimensions” (labeled in
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`dark red) are “obtained through the application of spacers on the side walls of the
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`auxiliary windows” (yellow). Ex-1001, 1:39-41; see also Ex-1007, 222. In other
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`words, as depicted in Figure 5a above, a “mask window” is formed between the
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`spacers (yellow) having a width less than the width of the “auxiliary window,”
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`which is the wider area between the sidewalls of the silicon oxide regions (blue).
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`Nakamura discloses as a next step, etching through the oxide layer (blue)
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`using a mask (labeled “Resist (2nd mask)”) in Figure 5b below, to form an oxide
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`mask above the WSi conductive layer (orange). After removal of the Resist (2nd
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`mask), the WSi conductive layer is etched, resulting in two conductive gates
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`separated by a narrow inter-electrode gap as shown in Figure 5c below. Ex-1001,
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`1:43-44; see also Ex-1007, 222.
`
`7
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`Petition for Inter Partes Review
`Patent No. 6,054,336
`
`
`
`Because spacers (yellow) are used, the inter-electrode gap or distance
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`between the two WSi electrodes corresponds to the width of the “mask window,”
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`marked by the dark red lines. Without the spacers, the gap or distance between the
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`WSi electrodes would be wider and correspond to the width of the wider “auxiliary
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`window,” marked by pink lines. Nakamura thus discloses a method for forming a
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`narrow gap (with a width equal to size of the “mask window” in dark red) between
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`two adjacent electrodes so that it is smaller than the minimum gap that can be
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`defined by lithography (which would have a width equal to the size of the
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`“auxiliary window” in pink).
`
`Nakamura’s “side-wall” technology was well known by the mid-1990s. For
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`example, it was well known that to form “sidewall spacers,” a dielectric material
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`(e.g., Low Temperature Oxide (LTO) oxide) is first deposited on the substrate.
`
`The 1987 textbook, Atlas of IC Technologies: An Introduction to VLSI Processes,
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`includes a figure (annotated below) depicting the formation of spacers on sidewalls
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`8
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`Petition for Inter Partes Review
`Patent No. 6,054,336
`of a gate electrode from a deposited LTO material. Ex-1010, p. 228-29. Steps (c)-
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`(d) deposit an LTO material in a conformal manner, meaning that equal amounts of
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`LTO material are deposited on both a horizontal surface as well as on the vertical
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`sidewalls of the gate electrode. As a result, if the gate electrode has a height of a
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`measured from the substrate surface and the deposited LTO material has a
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`thickness b, then as the annotations on the figure show, the thickness of the LTO
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`oxide h adjacent to the gate sidewalls is larger than b and equal to the sum of a
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`plus b.
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`In steps (e) and (f) of the figure, the LTO material is etched anisotropically,
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`typically using the Reactive Ion Etching (RIE) process. The RIE etches
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`
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`9
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`Petition for Inter Partes Review
`Patent No. 6,054,336
`anisotropically and only removes material in the vertical direction. Id. When the
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`entire thickness b of the LTO material is removed by RIE, a portion of the LTO
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`material on the sidewalls of the gate remains. The remaining LTO material on
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`each of the two sidewalls of the gate electrode are referred as “sidewall spacers.”
`
`Although Nakamura uses the side-wall technology described above to
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`reduce the gap between electrodes, the ’336 Patent contends that Nakamura’s
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`method presents two problems. First, “if the etching selectivity between silicon
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`oxide and the conductor material is not sufficiently great . . . the gate material will
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`also be attacked.” Ex-1001, 1:43-53. Second, “short-circuits of more or less high-
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`ohmic values occur between the gates after etching of the poly, probably as a result
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`of material remaining behind in the gaps after etching.” Id., 1:59-64.
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`VII. THE ’336 PATENT3
`A. The Patent Specification
`The ’336 Patent, entitled “Method of manufacturing an electronic device,”
`
`purports to improve on the deficiencies in Nakamura’s method of forming narrow
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`gaps between conductive electrodes. Ex-1001, Cover, 1:54-58, 1:64-67.
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`The patent’s method for fabricating a conductor pattern with narrow gaps
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`between conductor tracks is depicted in the embodiment of Figures 1a-1h. Id.,
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`
` 3
`
` This section is supported by Ex-1002, ¶¶33-43.
`
`10
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`Petition for Inter Partes Review
`Patent No. 6,054,336
`2:62-64. The embodiment is “explained with reference to a charge coupled device
`
`[CCD], in particular an imaging device, in which it is of major importance that the
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`electrodes should be at very small distances from one another.” Id., 3:13-18.
`
`The embodiment’s method begins with the multilayer structure depicted in
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`Figure 1a that includes: (1) an insulating “substrate” that includes a “gate
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`dielectric layer 1” and a “silicon body 2;” (2) a conductive layer 3 made of
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`polycrystalline silicon “in which the gates or electrodes of the charge coupled
`
`device are to be defined;” (3) a first dielectric layer composed of a “silicon nitride
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`layer 4” and a “silicon oxide layer 5;” and (4) a “photoresist layer” 6 that includes
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`“openings 7 at the areas of the gaps to be formed between the gates.” Id., 3:17-43.
`
`
`
`
`
`The ’336 Patent’s method proceeds to etch first dielectric layer 4, 5 through
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`the openings 7 as depicted in Figure 1b below. Id., 3:45-47. As Figure 1b shows,
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`“layer 5 is not etched throughout its entire thickness, but only through part of its
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`thickness.” Id., 3:49-52. After this partial etching is complete, “the photoresist
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`layer 6 has been removed subsequent to the etching of the oxide 5.” Id., 3:52-54.
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`11
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`Petition for Inter Partes Review
`Patent No. 6,054,336
`The etching results in “auxiliary windows” 8 (circled in pink) in the “oxide layer 5
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`[that] have dimensions which correspond to those of the openings 7 in the mask 6
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`and are considerably greater, as will become apparent below, than those of the gaps
`
`to be formed in the conductive layer 3.” Id., 3:54-58.
`
`
`
`
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`After forming the auxiliary windows in the first dielectric layer, “in a next
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`stage shown in FIG. 1c” shown below, “an additional oxide layer 9 is formed with
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`. . . the pattern of windows 8 being present also in this additional layer.” Id., 3:59-
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`62. This additional oxide layer 9 is labeled in yellow as the “additional dielectric
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`layer.”
`
`12
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`

`Petition for Inter Partes Review
`Patent No. 6,054,336
`
`
`
`In Figure 1d below, the next step is to remove “portions of the layer 9” “by
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`means of anisotropic etching-back.” Id., 3:62-4:1. After this removal, “portions
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`10 of the additional layer, referred to as spacers for short, remain on the side walls
`
`of the auxiliary windows 8 (FIG. 1d), strongly reducing the dimensions of the
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`auxiliary windows 8.” Id. These spacers (elements 10), labeled in yellow, are
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`formed on the sidewalls of the auxiliary windows (circled in pink) and thereby
`
`reduce the width of the auxiliary windows.
`
`
`
`
`
`
`
`After forming the spacers, etching continues through the first dielectric layer
`
`13
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`

`Petition for Inter Partes Review
`Patent No. 6,054,336
`in the gaps formed by the spacers until the conductive polysilicon layer 3 is
`
`reached as depicted in Figure 1f below. Id., 4:1-11. The continued etching forms
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`windows 11 at the conductive layer (labeled and circled in brown). The width of
`
`the windows 11 at the conductive layer is smaller than the width of the auxiliary
`
`windows 8 previously formed and depicted in Figure 1b above. Id., 3:54-58
`
`(explaining that auxiliary windows 8 “have dimensions which . . . are considerably
`
`greater . . . than those of the gaps to be formed in the conductive layer 3”).
`
`
`
`After forming windows at the conductive layer, the patent describes
`
`additional and final steps for forming conductor gates from the polysilicon
`
`conductive layer 3 (colored in orange in Figure 1f above). Id., Figs. 1f, 1g, 2a, 2b,
`
`4:10-64. But these additional steps are not recited in the challenged Claims 1-3.
`
`B.
`Prosecution History
`The ’336 Patent was filed on May 26, 1998 as Application Serial No.
`
`09/085,085. Ex-1004, 1, 5-7; Ex-1001, Cover. The applicant claimed priority to a
`
`14
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`Petition for Inter Partes Review
`Patent No. 6,054,336
`foreign patent application, EP 97201585, filed on May 29, 1997. Id. On June 28,
`
`1999, the Examiner issued an Office Action that, among other things, rejected the
`
`pending claims as obvious under 35 U.S.C. § 103, over U.S. Patent No. 5,818,085
`
`(“Hsu”), in view of U.S. Patent No. 5,589,407 (“Meyyappan”). Ex-1004, 53-63.
`
`On October 8, 1998, the applicant responded by canceling the only
`
`independent claim in the originally-filed claims and added a new independent
`
`claim (corresponding to issued Claim 1 in the ’336 Patent). Id., 65-72. Applicant
`
`argued that certain steps in the newly added independent claim — including
`
`forming “auxiliary windows . . . ,” “providing an additional dielectric layer on the
`
`first dielectric layer . . .,” “etching the additional dielectric layer back
`
`anisotropically without a mask to form spacers . . .,” and “continuing etching
`
`anisotropically through the auxiliary window and the spacers . . .” — were not
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`taught by either Hsu or Meyyappan. Id.
`
`On December 21, 1999, the Examiner accepted the applicant’s arguments
`
`and allowed the amended claims. Id., 73-76.
`
`VIII. LEGAL STANDARDS
`A. Claim Construction
`Because the ’336 Patent is set to expire on May 26, 2018, before a final
`
`
`
`written decision, its claims should be construed consistent with the standard for
`
`claim construction set forth in Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir.
`
`15
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`Petition for Inter Partes Review
`Patent No. 6,054,336
`2005) (en banc). E.g., In re CSB-System Int’l, Inc., 832 F.3d 1335, 1341-42 (Fed.
`
`Cir. 2016). For the purposes of this proceeding, Samsung does not believe any
`
`terms need construction.
`
`B.
`Level Of Ordinary Skill In The Art
`A person of ordinary skill in the art at the time of the purported invention of
`
`the ’336 Patent (“POSA”) would have had a bachelor-level degree in mechanical
`
`engineering, materials science, electrical engineering, or a related field and 3–5
`
`years of experience or post-graduate education in the design/development of
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`semiconductor manufacturing. Ex-1002, ¶21.
`
`IX. OVERVIEW OF PRIOR ART4
`A. U.S. Patent No. 5,428,231 (“Tanaka”) (Ex-1006)
`Tanaka was filed on June 30, 1994, as U.S. Patent Application No. 269,349,
`
`and issued as U.S. Patent No. 5,428,231, on June 27, 1995. Ex-1006. Tanaka is
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`effective as prior art under at least §§ 102(a), (b) and (e), as it issued more than a
`
`year before the ’336 Patent was filed in the United States on May 26, 1998.
`
`Tanaka was not considered during the prosecution of the ’336 Patent.
`
`Like the ’336 Patent’s claims and embodiments, Tanaka relates “to a solid-
`
`state imaging device having CCDs with an improved electrode structure.” Id., 1:8-
`
`
` 4
`
` This section is supported by Ex-1002, ¶¶46-66.
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`16
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`Petition for Inter Partes Review
`Patent No. 6,054,336
`12. In fact, just like the ’336 Patent, Tanaka states that one of its objects is to
`
`improve the “transfer efficiency of a horizontal CCD” while curbing “short-circuit
`
`between transfer electrodes.” Id., 3:3-6. As stated in Section VI, the transfer
`
`efficiency in a CCD improves as the gap or distance between transfer electrodes
`
`decreases. Accordingly, Tanaka improves transfer efficiency by narrowing the
`
`“gap between the transfer electrodes of the horizontal CCD” so that the gap “is
`
`made less than a minimum dimension of lithography by [using] a side-wall-leaving
`
`technique.” Id., 3:32-36.
`
`Tanaka discloses several embodiments for narrowing the gap between
`
`transfer electrodes of a CCD using “a side-wall leaving technique,” with one
`
`embodiment of Figures 17A-F using Al (aluminum) to form the transfer electrodes
`
`and another embodiment of Figures 18-F using polysilicon to form the transfer
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`electrodes. Id., 12:58-14:48. Tanaka concludes that by using both embodiments,
`
`“an inter-electrode distance less than a minimum pattern dimension determined by
`
`lithography can be obtained.” Id., 15:14-17.
`
`Tanaka’s “side-wall leaving technique” in Figures 18A-F begins with the
`
`structure depicted in Figure 18A, which includes: (1) a silicon oxide film 62
`
`covering silicon substrate 61; (2) a conductive polysilicon film 63; (3) a dual layer
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`dielectric comprising of a silicon nitride film 64 and silicon oxide film 65; and (4)
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`a patterned resist film 66. Id., 13:66-14:11.
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`Then, “with the resist film 66 used as a mask, the silicon oxide film 65 is
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`selectively etched by RIE, and grooves 68 are formed in the silicon oxide film 65.”
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`Id., 14:12-15. “After the resist film 66 is removed, a silicon oxide film 67 is
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`deposited” on the resulting surface. Id. 14:15-17.
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`The resulting structure after forming grooves 68 and adding silicon oxide
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`film 67 is depicted in Figure 18B below. Grooves 68 (circled in pink) in the dual
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`layer dielectric are formed in the openings in the resist film 66 depicted in Figure
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`18A after the aforementioned RIE (Reactive Ion Etching) step. Then the silicon
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`oxide film 67 is added over the resulting surface including the sidewalls of the
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`grooves 68.
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`Tanaka discloses that the silicon oxide film 67 is deposited by “a vapor
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`phase growth method.” Id., 14:15-17. This method results in a conformal coating
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`of silicon oxide film 67 over the silicon nitride 64 and silicon oxide 65 layers.
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`Tanaka also states that the deposited “silicon oxide film is thinner at the central
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`portions of the grooves 68.” Id., 14:18-23. This means that, as depicted in Figure
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`18B above, the thickness of the silicon oxide film 67 deposited in the central
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`portions of the grooves 68 (green arrows) is thinner than the thickness of the
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`silicon oxide film 67 deposited near the sidewalls of grooves 68 (red arrows). Id.
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`After the silicon oxide film 67 is deposited, Tanaka discloses that “the entire
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`surface of the silicon oxide film 67 is etched by, e.g. RIE.” Id., 14:18-19. RIE
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`etching results in the formation of spacers on the sidewalls of the grooves, as
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`shown in Figure 18C below. Id., 14:18-23. Because of these spacers, as the
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`annotated Figure 18C below shows, the “grooves 69” (labeled below) are
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`“narrower than the grooves 68” shown in Figure 18B above. Id.
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`From Figure 18C, “[w]ith the silicon oxide film 67 used as a mask, the entire
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`surface of the silicon nitride film 64 is etched . . . and grooves 70 having almost the
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`same width as the grooves 69 are formed in the silicon nitride film 64.” Id., 14:24-
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`28. This further etching step leaves new grooves 70 (circled in red) immediately
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`above polysilicon film 63 in Figure 18D below. The grooves 70 have nearly the
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`same width as grooves 69, which are narrower than the grooves 68 formed earlier
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`in Figure 18B above.
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`Petition for Inter Partes Review
`Patent No. 6,054,336
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`After forming grooves 70, Tanaka describes removing the “silicon oxide
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`film 65 and silicon oxide film 67.” Id., 14:29-35. This step results in the structure
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`shown in Figure 18E below, where the grooves 70 are maintained immediately
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`above polysilicon film 63.
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`In the last step, Tanaka discloses etching the polysilicon film 63 through
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`grooves 70, forming a “polysilicon electrode pattern,” shown in Figure 18F below.
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`Id., 14:32-35.
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`Tanaka explains the benefits of the method of Figures 18A-F, including
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`reducing the gap between electrodes formed of the polysilicon film:
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`According to this embodiment, an electrode gap can be
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`reduced without varying a pitch of polysilicon electrodes
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`formed of the polysilicon film 63.
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` Thereby, the
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`integration density of the polysilicon electrode pattern
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`can be increased.
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`Id., 14:36-48.
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`B. U.S. Patent No. 5,847,460 (“Liou”) (Ex-1005)
`Liou was filed on December 19, 1995, as U.S. Patent Application No.
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`574,659, and issued as U.S. Patent No. 5,847,460 on December 8, 1998. Ex-1005,
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`Cover. Liou is effective as prior art under at least § 102(e). Liou was not
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`considered during the prosecution of the ’336 Patent.
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`Similar to the ’336 Patent, Liou discloses an improved method for forming
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`features in a semiconductor device that are smaller than what could be formed by
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`lithography. Liou explains that the “geometries and sizes” of semiconductor
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`components on a chip such as “gate electrodes” “are often dependent upon the
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`current photolithographic equipment and materials available in the industry”
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`because this photolithographic equipment is used to “project an image of patterns
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`onto a wafer surface.” Id., 1:20-29. But “[a]s line widths shrink smaller and
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`smaller in submicron photolithography, the process to print lines and contact holes
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`in photoresist becomes increasingly more difficult” because of limits in
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`“photolithography equipment’s capability.” Id., 1:37-39, 1:58-62. “Thus, it would
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`be desirable to achieve device sizes below the current photolithography
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`capability.” Id., 1:66-67. An object of Liou is therefore “to provide such a method
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`of forming contacts and vias having contact dimensions smaller than the contact
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`dimensions which can be printed with modern photolithography equipment.” Id.,
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`2:8-11.
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`An embodiment of Liou’s method for forming smaller feature sizes is
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`depicted in its Figures 1-5. In Figure 1 below, Liou’s method begins with a
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`multilayer structure that includes: (1) an insulating substrate that includes an
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`insulating layer 12 that covers a substrate surface 10; (2) a conductive layer 14
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`over the insulating layer 12; (3) an insulating layer 16 over the conductive layer
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`14; and (4) a photoresist layer 18 “formed over insulating layer 16” with an
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`opening 20. Id., 3:36-4:31.
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`Then, “insulating layer 16 is etched in opening 20 to form a contact opening
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`partially through the insulating layer” as depicted in Figure 2 below, where the
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`opening 20 (circled in pink) extends partway through the insulating layer 16. Id.,
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`4:32-34.
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`Then “photoresist layer 18 is removed” and a “sidewall spacer film 22 is
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`formed over insulating layer 16 and in opening 20.” Id., 4:45-49. In Figure 3
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`below, the sidewall spacer film 22 is colored in yellow and as Liou describes, it is
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`formed over insulating layer 16, including in the opening 20.
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`The next step, depicted in Figure 4 below, is “anisotropic etchback of the
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`sidewall spacer film,” which “leav[es] sidewall spacers 24” (yellow) on the sides
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`on the opening 20. Id., 4:57-59.
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`After forming sidewall spacers 24, Figure 5a shows that “the insulating layer
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`16 in the bottom of opening 20 is etched to expose the underlying conducting layer
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`14,” which results in a new opening 32 (labeled and circled in red) immediately
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`above the conductive layer 14. Id., 5:10-12.
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`Liou also discloses that the spacers (yellow) in Figure 5a may then be etched
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`away as depicted in Figure 5b. Id., 5:44-47.
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`Liou explains that “it is preferable to use an anisotropic etch” because
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`anisotropic etching “achieve[s] substantially vertical sidewalls at the bottom of
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`contact opening 32.” Id., 5:12-17. Liou also explains that because of its use of
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`sidewall spacers and anisotropic etching:
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`The contact dimension of the newly formed contact
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`opening 32 with sidewall spacers 24 is now smaller
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`than the original contact dimension of contact
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`opening 20 prior to the formation of the sidewall
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`spacers. The new contact dimension is smalle