`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`SAMSUNG ELECTRONICS CO., LTD. AND SAMSUNG ELECTRONICS
`AMERICA, INC.
`Petitioner
`
`v.
`
`INVENSAS CORPORATION
`Patent Owner
`
`____________________
`
`U.S. Patent No. 6,825,554
`____________________
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 6,825,554
`
`
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`
`TABLE OF CONTENTS
`INTRODUCTION ........................................................................................... 1
`I.
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8 ................................... 1
`III. PAYMENT OF FEES UNDER 37 C.F.R. § 42.15(a) .................................... 3
`IV. GROUNDS FOR STANDING ........................................................................ 3
`V.
`PRECISE RELIEF REQUESTED .................................................................. 4
`VI. OVERVIEW OF THE RELEVANT TECHNOLOGY .................................. 4
`VII. THE ’554 PATENT ......................................................................................... 7
`A.
`The Patent Specification ........................................................................ 7
`B.
`Prosecution History ............................................................................. 10
`VIII. LEGAL STANDARDS ................................................................................. 11
`A.
`Claim Construction ............................................................................. 11
`B.
`Level Of Ordinary Skill In The Art ..................................................... 12
`IX. OVERVIEW OF PRIOR ART ...................................................................... 13
`A.
`Schaper (Ex-1005) ............................................................................... 13
`B.
`Su (Ex-1006) ....................................................................................... 16
`C. Verdi (Ex-1007) .................................................................................. 18
`D. Huang (Ex-1008) ................................................................................. 21
`E.
`Schaper II (Ex-1009) ........................................................................... 23
`Explanation Of Grounds For Invalidity ......................................................... 25
`A. Ground 1: Schaper In View Of Verdi Renders Obvious Renders
`Obvious Challenged Claims 1-5 ......................................................... 25
`1.
`Reasons To Combine Schaper With Verdi ............................... 26
`
`X.
`
`i
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,512,298
`Claim 1 ...................................................................................... 29
`2.
`Claim 2 ...................................................................................... 38
`3.
`Claim 3 ...................................................................................... 38
`4.
`Claim 4 ...................................................................................... 40
`5.
`Claim 5 ...................................................................................... 41
`6.
`B. Ground 2: Schaper In View Of Schaper II Renders Obvious
`Challenged Claims 1-5 ........................................................................ 42
`1.
`Reasons To Combine Schaper With Schaper II ....................... 43
`2.
`Claim 1 ...................................................................................... 45
`C. Ground 3: Su In View of Verdi Renders Obvious Challenged
`Claims 1-5 ........................................................................................... 51
`1.
`Reasons To Combine Su And Verdi ......................................... 53
`2.
`Claim 1 ...................................................................................... 56
`3.
`Claim 2 ...................................................................................... 62
`4.
`Claim 3 ...................................................................................... 63
`5.
`Claim 4 ...................................................................................... 65
`6.
`Claim 5 ...................................................................................... 66
`D. Ground 4: Su In View of Huang Renders Obvious Challenged
`Claims 1-5 ........................................................................................... 67
`1.
`Reasons To Combine Su And Huang ....................................... 68
`2.
`Claim 1 ...................................................................................... 72
`3.
`Claim 4 ...................................................................................... 75
`XI. CONCLUSION .............................................................................................. 77
`
`
`
`
`
`
`ii
`
`
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`
`1001
`1002
`1003
`1004
`1005
`
`1006
`1007
`1008
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`1014
`1015
`1016
`1017
`1018
`1019
`
`1020
`
`1021
`
`1022
`
`1023
`
`LIST OF EXHIBITS
`U.S. Patent No. 6,825,554 (“the ’554 Patent”)
`Declaration of Peter Elenius
`Curriculum Vitae for Peter Elenius
`Prosecution File History of U.S. Patent No. 6,825,554
`Schaper et al., “Electrical Characterization of the Interconnected
`Mesh Power System IMPS MCM Topology,” IEEE
`Transactions on Components, Packaging, and Manufacturing
`Technology, Vol. 18, No. 1, February 1995 at pp. 99-105
`(“Schaper”)
`U.S. Patent Application Publication No. 2002/0118528 (“Su”)
`U.S. Patent No. 6,125,042 (“Verdi”)
`U.S. Patent No. 6,359,341 (“Huang”)
`Simon S. Ang et al., “A low-cost, flexible ball-grid-array
`multichip module technology,” Proc. SPIE 3184, August 1997
`at pp. 13-21 (“Schaper II”)
`Davidson and Katopis, Microelectronics Packaging Handbook,
`Chapter 3, 1989.
`Microelectronics Packaging Handbook, 696 (Rao Tummala and
`Eugene Rymaszewski eds., 1989)
`Semiconductor Packaging A Multidisciplinary Approach, 29-30
`(Robert Hannemann, et al., eds., 1994)
`Ball Grid Array Technology, 370-377 (John Lau, ed., 1995)
`Declaration of Sylvia D. Hall-Ellis
`Curriculum Vitae for Sylvia D. Hall-Ellis
`IEEE Xplore Bibliographic Record For Schaper
`SPIE Bibliographic Record For Schaper II
`Ball Grid Array Technology, 279-280 (John Lau, ed., 1995)
`Huang, et al., “CBGA Package Design for C4 PowerPC
`Microprocessor Chips: Trade-off between Substrate Routability
`and Performance” (IEEE 1994)
`Electronic Packaging and Interconnection Handbook, 7.52
`(Charles Harper, ed., 2000)
`Tsai, “Inductance and SSN Performance Comparison of a 225
`Plastic BGA and a 208 Plastic QFP” (1996)
`T. Chang, et al., “Parasitic characteristics of BGA packages,”
`124-129 (IEEE 1998)
`Citation to T. Chang, et al., “Parasitic characteristics of BGA
`
`iii
`
`

`

`packages,” 124-129 (IEEE 1998)
`
`Petition for Inter Partes Review
`Patent No. 6,825,554
`
`iv
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`
`I.
`
`INTRODUCTION
`Samsung Electronics Co., Ltd and Samsung Electronics America, Inc.
`
`(collectively “Samsung”) request inter partes review (“IPR”) of Claims 1-5 of U.S.
`
`Patent No. 6,825,554 (the “’554 Patent”; Ex-1001), assigned to Invensas
`
`Corporation (“Patent Owner”).
`
`The ’554 Patent claims a semiconductor package substrate that is “at most
`
`two layers” and provides “at least one isolating ground trace” on the first layer to
`
`“provide noise shielding” between “two signal traces” and on “a second layer such
`
`that at least one row of solder balls” that are “connected together and to ground to
`
`create a second-layer isolating ground trace.” Ex-1001, Claim 1. As detailed in
`
`this Petition, the ’554 Patent’s two-layer package substrate with noise shielding
`
`was known before July 31, 2001, the patent’s priority date.
`
`This Petition presents four grounds of invalidity that the PTO did not
`
`consider during prosecution. These grounds are each likely to prevail, and this
`
`Petition, accordingly, should be granted on all grounds ultimately resulting in
`
`cancellation of the challenged claims. The petition is further supported by the
`
`Declaration of Mr. Peter Elenius, an expert in the semiconductor packaging
`
`technologies claimed by the ’554 Patent. See Ex-1002.
`
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8
`Real Parties-in-Interest: Samsung identifies the following real parties-in-
`
`1
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`interest: Samsung Electronics Co., Ltd and Samsung Electronics America, Inc.
`
`Related Matters: Patent Owner has asserted that Samsung infringes the
`
`’554 Patent in a district court action, Invensas Corp. v. Samsung Electronics
`
`America, Inc., and Samsung Electronics Co., Ltd., Civ. No. 2:17-cv-00670-RWS-
`
`RSP (E.D. Tex.). Samsung has challenged U.S. Patent No. 6,566,167 (“’167
`
`Patent”), which is related to the ’554 Patent, in another, simultaneously-filed
`
`petition
`
`Lead and Back-Up Counsel:
`
`Pursuant to 37 C.F.R. § 42.8(b)(3), Samsung identifies the following lead
`
`and back-up counsel:
`
`Lead Counsel
`
`Back-Up Counsel
`
`SAMSUNG’S LEAD AND BACK-UP COUNSEL
`Brian M. Berliner (Reg. No. 34,549)
`Email: bberliner@omm.com
`O’Melveny & Myers LLP
`400 South Hope Street, 18th Floor
`Los Angeles, CA 90071
`Telephone: (213) 430-6000
`Fax: (213) 430-6407
`
`Ryan Yagura (Reg. No. 47,191)
`Email: ryagura@omm.com
`Nicholas Whilt (Reg. No. 72,081)
`Email: nwhilt@omm.com
`O’Melveny & Myers LLP
`400 South Hope Street, 18th Floor
`Los Angeles, CA 90071
`Telephone: (213) 430-6000
`
`2
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`
`SAMSUNG’S LEAD AND BACK-UP COUNSEL
`Fax: (213) 430-6407
`
`John Kappos (Reg. No. 37,861)
`O’Melveny & Myers LLP
`610 Newport Center Drive, 17th Floor
`Newport Beach, California 92660
`Telephone: 949-823-6900
`Fax: 949-823-6994
`Email: jkappos@omm.com
`
`Mark Liang (Reg. No. L1031)
`O’Melveny & Myers LLP
`2 Embarcadero Ctr., 28th Floor
`San Francisco, California 94111
`Telephone: 415-984-8700
`Fax: 415-984-8701
`Email: mliang@omm.com
`
`
`
`Service Information: Samsung may be served at the addresses provided
`
`above for lead and back-up counsel. Samsung consents to electronic service at the
`
`address: INVENSASSAMSUNGTX17670OMM@omm.com.
`
`III. PAYMENT OF FEES UNDER 37 C.F.R. § 42.15(a)
`In accordance with 37 C.F.R. § 42.103(a), the Office is authorized to charge
`
`an amount in the sum of $23,000 to Deposit Account No. 50-2862 for the fee set
`
`forth in 37 C.F.R. § 42.15(a) and any additional fees that may be due.
`
`IV. GROUNDS FOR STANDING
`Pursuant to 37 C.F.R. § 42.104(a), Samsung certifies that the ’554 Patent is
`
`available for inter partes review and that Samsung is not barred or otherwise
`
`3
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`estopped from requesting inter partes review on the grounds identified herein.
`
`V.
`
`PRECISE RELIEF REQUESTED
`Samsung respectfully requests review of Claims 1-5 (the “Challenged
`
`Claims”) of the ’554 Patent, and cancellation of these claims, based on the grounds
`
`listed below.
`
`• Ground 1: Claims 1-5 are obvious under 35 U.S.C. § 103 over Schaper in
`
`view of Verdi;
`
`• Ground 2: Claims 1-5 are obvious under 35 U.S.C. § 103 over Schaper in
`
`view of Schaper II;
`
`• Ground 3: Claims 1-5 are obvious under 35 U.S.C. § 103 over Su in view
`
`of Verdi; and
`
`• Ground 4: Claims 1-5 are obvious under 35 U.S.C. § 103 over Su in view
`
`of Huang.
`
`VI. OVERVIEW OF THE RELEVANT TECHNOLOGY1
`Ball Grid Array (“BGA”) is a packaging technology that uses solder ball
`
`terminals arranged in an array format on the bottom surface of the package. These
`
`solder ball terminals are normally placed into solder paste that has been printed on
`
`corresponding pads on the printed circuit board (PCB) and then reflowed to
`
`
` 1
`
` This section is supported by Ex-1002, ¶¶20-25.
`
`4
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`connect the BGA to the PCB. BGA packages were introduced to the market in the
`
`late 1980s.
`
`As illustrated below, the BGA package is composed of four basic parts: the
`
`semiconductor chip, a BGA substrate, an electrical connection between the chip
`
`and the BGA substrate, and the solder ball terminals. The substrate shown in the
`
`figure below is called a two-layer substrate as it has one metal layer on the top and
`
`another metal layer on the bottom. Beginning in 1990, BGAs began using a
`
`laminate or organic substrate material, which is referred to as a plastic or polymer
`
`BGA (“PBGA”).
`
`
`
`
`
`The electrical interconnection between the chip and the BGA substrate can
`
`be made using wire bonds or flip chip bumps. In the above figure, the chip is in a
`
`face-down configuration and is joined using flip chip solder bumps to the two-
`
`layer laminate BGA substrate. The majority of laminate substrates are two-layer
`
`substrates.
`
`5
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`The electrical design of IC packages involves a complex set of trade-offs to
`
`achieve the required electrical performance. The principals of high-performance
`
`IC package design were known in the 1980s and were extensively described by
`
`Davidson and Katopis in 1989. Ex-1010. There are two primary sources of noise
`
`in an IC package—coupled noise and switching noise. Id., Figure 3-1. Coupled
`
`noise is synonymous with “crosstalk” (also written, “cross talk” and “cross-talk”).
`
`“Cross talk is caused by electromagnetic interactions between signal lines in close
`
`proximity.” Id., 147. The ’554 Patent is directed toward reducing this crosstalk
`
`between adjacent sets of signals in a 2-layer PBGA substrate. Ex-1001, 1:6-10.
`
`There are many known methods to reduce the crosstalk between signal lines.
`
`These include: 1) increasing the separation between the lines, 2) minimizing the
`
`length of the adjacent lines, and 3) placing a ground or power line between the
`
`signal lines. The placement of a ground or power line between signal lines was
`
`well known in the art in the 1980s and 1990s. See, e.g., Ex-1011, 696 (“Coupled
`
`noise is controlled in such simple packages in two ways….One is to reduce mutual
`
`inductance by wider spacing of conductors, whereas the other is to intersperse
`
`signal and power lines.”); Ex-1012, 30 (showing that one design approach to
`
`address cross-talk is to “[a]dd reference trace between signal lines.”); Ex-1013,
`
`372 (“Alternatively, inclusion of a ground trace between adjacent signal lines
`
`reduces the crosstalk by approximately 50 percent.”).
`
`6
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`
`VII. THE ’554 PATENT2
`A. The Patent Specification
`The ’554 Patent, entitled “PBGA Electrical Noise Isolation Of Signal
`
`Traces,” is directed to a semiconductor package that addresses the problem of
`
`crosstalk and noise between adjacent signal traces in BGA packages. Ex-1001,
`
`1:9-12. In particular, it describes a semiconductor package in which “a plurality of
`
`traces” are patterned on “one or both sides of a 2-layer PBGA organic substrate 12,
`
`which includes solder balls 20 on the bottom layer.” Id., 2:48-51. These features
`
`are shown in Figure 1A, below.3
`
`
`
` 2
`
` This section is supported by Ex-1002, ¶¶26-32.
`
`3 Many of the figures throughout this petition have been annotated to illustrate
`
`relevant features. The figures for the ’554 Patent are taken from the related ’167
`
`Patent as the figures are identical, but the versions in the ’167 Patent are more
`
`readable with computer generated, rather than handwritten text.
`
`7
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`
`
`
`With respect to Figure 3 below, the ’554 Patent purports to reduce crosstalk
`
`by patterning an isolating ground trace “adjacent and substantially parallel to at
`
`least one group of signals” in order to isolate that group of signals from another
`
`group of signals. Id., 2:54-57. According to the patent, the isolating ground trace
`
`“acts as a local shield between the signals, thereby protecting the signals from
`
`crosstalk and achieving noise reduction without adding additional planes to the
`
`substrate.” Id., 3:6-10.
`
`8
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`
`
`
`The ’554 Patent also describes connecting the isolating ground trace to
`
`ground through multiple vias, for example, by using a via on both ends of the
`
`isolation trace or a plurality of vias along the length of the trace. Id., 3:1-5. Figure
`
`3 illustrates an isolating ground trace formed on the top layer of a PBGA substrate
`
`and the vias connecting the ground trace to ground.
`
`The ’554 Patent also describes an isolating ground trace formed on the
`
`bottom layer of the substrate. Since the bottom layer of a 2-layer PBGA substrate
`
`includes an array of solder balls, the patent explains that “[a]n isolating ground
`
`trace 204 is formed on the bottom layer by connecting a row of the solder balls
`
`20.” Id., 3:19-22. The isolating ground trace on the bottom layer is shown in
`
`Figure 4, below.
`
`9
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`
`The ’554 Patent also explains that the top and bottom isolating ground traces
`
`
`
`may be connected using vias. Id., 3:26-32.
`
`B.
`Prosecution History4
`The ’554 Patent was filed on March 11, 2003 as Application
`
`No. 10/387,261. Ex-1004, 5; Ex-1001, Cover. The ’554 Patent was filed as a
`
`division of Application No. 09/919,284, which issued as U.S. 6,566,167 (the “’167
`
`Patent”) and was filed on July 31, 2001. Ex-1004, 5; Ex-1001, Cover.
`
`During prosecution of the ’554 Patent, on February 19, 2004, the Examiner
`
`issued an Office Action rejecting all pending claims as anticipated by U.S.
`
`
` 4
`
` All citations to Ex-1004 are to the repaginated page numbers applied to the File
`
`History by Samsung.
`
`10
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`5,686,764 (“Fulcher”). Ex-1004, 43-47. On May 24, 2004, the applicant
`
`responded by amending the claims to add the limitation of “an array of solder balls
`
`on a second layer such that at least one row of solder balls is connected together
`
`and to ground to create a second-layer isolating ground trace” and argued that this
`
`limitation requiring a “row of solder balls” that “create a second-layer isolating
`
`ground trace” taught over Fulcher. Id., 58-67. On August 3, 2004, the Examiner
`
`accepted the applicant’s amendments and arguments and issued a Notice of
`
`Allowance for all pending claims. Id., 74-79.
`
`VIII. LEGAL STANDARDS
`A. Claim Construction
`In the context of an inter partes review, claim terms in an unexpired patent
`
`are given their broadest reasonable interpretation (“BRI”) in light of the
`
`specification in which they appear. 37 C.F.R. § 42.100(b); see also Cuozzo Speed
`
`Techs., LLC v. Lee, 136 S. Ct. 2131, 2134-35 (2016). Should institution be
`
`granted, the ’554 Patent would not expire before a final written decision, and its
`
`claims should therefore be given their broadest reasonable interpretation.5 For
`
`
`
` 5
`
` The Petitioner recognizes that the Board has proposed a rule change to apply the
`
`Phillips standard in all IPR proceedings. 83 FR 21221.
`
`11
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`purposes of this proceeding, Samsung does not believe any term needs
`
`construction.6
`
`In a prior district court litigation, a court construed the challenged claims
`
`under the Philips standard. Invensas Corp. v. Renesas Elecs. Corp., C.A. No. 11-
`
`448-GMS, 2013 WL 3753621 (D. Del. July 15, 2013).
`
`B.
`Level Of Ordinary Skill In The Art
`A person of ordinary skill in the art at the time of the purported invention of
`
`the ’554 Patent (“POSA”) would have had a bachelor’s degree in mechanical
`
`engineering, materials science, electrical engineering, or a related field and 2-3
`
`years of experience or post-graduate education and research in the
`
`design/development of semiconductor packages. Ex-1002, ¶17.
`
`
`
` 6
`
` Because the claim construction standard in this proceeding differs from the
`
`standard applicable in district court litigation, see In re Am. Acad. of Sci. Tech Ctr.,
`
`367 F.3d 1359, 1364, 1369 (Fed. Cir. 2004), and because there are no claim
`
`construction issues that are believed to be dispositive as to the particular grounds
`
`presented in the instant petition, Samsung expressly reserves the right to assert in
`
`litigation constructions for claim terms in the ’554 Patent that are not also asserted
`
`in this petition.
`
`12
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`
`IX. OVERVIEW OF PRIOR ART7
`A.
`Schaper (Ex-1005)
`The article entitled “Electrical Characterization of the Interconnected Mesh
`
`Power System (IMPS) MCM Topology,” was published in IEEE Transactions on
`
`Components, Packaging, and Manufacturing Technology in February 1995
`
`(“Schaper”). Declaration of Sylvia D. Hall-Ellis, Ex-1014. Schaper was publicly
`
`available by at least March 1, 1995, as shown by its copyright date and its
`
`bibliographic record. Id., ¶¶31a-i, 33; Ex-1016. Schaper is therefore effective as
`
`prior art to the ’554 Patent under pre-AIA §§ 102(a) and (b). Schaper was not of
`
`record and was not considered during prosecution of the ’554 Patent.
`
`Schaper describes the efforts of researchers at the University of Arkansas to
`
`develop a 2-layer substrate wherein crosstalk between signal traces is reduced by
`
`utilizing a ground trace between the signals. Ex-1005. In particular, Schaper
`
`describes the “Interconnected Mesh Power System” (IMPS), which was a
`
`“systematic topology” with only two physical wiring layers and low crosstalk
`
`signal transmission. Id., 99. In IMPS, two-metal layers are fabricated orthogonal
`
`to each other. Schaper illustrates the top layer as lines of conductors running
`
`
`
` 7
`
` This section is supported by Ex-1002, ¶¶35-56.
`
`13
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`vertically and the bottom layer as lines of conductors running horizontally as
`
`shown in Figure 4(a). Id., 99-101.
`
`
`
`
`
`Because adjacent signal tracks would result in high crosstalk, Schaper
`
`teaches “always keeping at least one power or ground conductor between adjacent
`
`signal conductors.” Id., 100. Specifically, Schaper teaches that “[t]he IMPS
`
`topology offers far greater crosstalk reduction by interposing an ac ground
`
`conductor between every pair of signal conductors.” Id., 101. An exemplary
`
`arrangement of the top layer showing vertical signal traces divided by a vertical
`
`14
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`ground trace is shown in Figure 4(a). The bottom layer similarly includes
`
`horizontal signal traces divided with horizontal ground and power traces to provide
`
`noise reduction. The red dots represent vias connecting the first and second layer
`
`ground traces.
`
`
`
`The two-metal layers are fabricated on a silicon wafer with a polyimide
`
`dielectric formed in between. Schaper refers to this implementation as an MCM-
`
`D, which was a common term at the time of the publication. Id., 99-101. Schaper
`
`
`
`15
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`also discloses an MCM-L IMPS implementation, which a POSA would have
`
`understood referred to a MCM laminate or MCM organic substrate-based
`
`technology. Id., 101.
`
`B.
`Su (Ex-1006)
`U.S. Patent Application Publication No. 2002/0118528 (“Su”) was filed on
`
`March 19, 2001 and was published on August 29, 2002. Su is therefore effective
`
`as prior art to the ’554 Patent under pre-AIA § 102(e). Su was not of record and
`
`was not considered during prosecution of the ’554 Patent.
`
`Su describes “a substrate layout method and structure of a ball grid array to
`
`reduce cross talk of adjacent signals.” Ex-1006, [0003]-[0005]. Su discloses a
`
`device, illustrated in Figure 4a, that includes normal signal pads 120, clock pad
`
`121, power pad 122, and ground pad 123 on the die 10 of a BGA substrate 16. Id.,
`
`[0027]. Su further discloses that there is a power ring 201 and a ground ring 202
`
`around the die. Id.
`
`16
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`
`
`
`
`
`Figure 4a also illustrates normal signal fingers 180 and a clock signal finger
`
`181 (collectively, signal fingers, green) and guard fingers 182, 183 (red). Each
`
`finger is connected to a corresponding solder ball through a trace on the top layer
`
`of the substrate. Id., [0027]. Su teaches that the first guard finger 182 is connected
`
`to a power trace and the second guard finger 183 is connected to a ground trace.
`
`Id.
`
`According to Su, by interposing the guard fingers and traces between the
`
`signal fingers and traces, crosstalk between the signal traces is reduced. Id.,
`
`[0026]. In particular, Su discloses that “when both side[s] of guard trace is
`
`shorte[d] to ground, the maximum and average voltage variation of the
`
`17
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`rectangular wave signal are minimal. Thus, it can provide the best screening
`
`performance against cross talk.” Id.
`
`Su employs a two-layer package, as illustrated in Figure 4c, in which the
`
`guard traces pass through vias from the top layer to the bottom layer where they
`
`connect to solder balls. Id., [0005], [0027].
`
`
`
`The two-layer embodiment of Figure 4c is described in [0027] and [0029],
`
`and also provides a guard trace formed to screen against crosstalk, “with both
`
`side[s] shorted to ground between the clock trace 28 and the normal signal trace
`
`32.” Id., [0029].
`
`C. Verdi (Ex-1007)
`U.S. Patent No. 6,125,042, titled “Ball Grid Array Semiconductor Package
`
`Having Improved EMI Characteristics” (“Verdi”), was filed on April 10, 1998 and
`
`issued on September 26, 2000. Verdi is therefore effective as prior art to the ’554
`
`18
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`Patent under at least pre-AIA §§ 102(a) and (e). Verdi was not of record and was
`
`not considered during prosecution of the ’554 Patent.
`
`Verdi describes a BGA package in which “hemisphericaly-shaped solder
`
`leads” (i.e., solder balls) are deployed in a matrix on the bottom layer of the
`
`semiconductor package, as illustrated in Figure 3. Ex-1007, 4:25-27.
`
`
`
`Verdi teaches that “[i]n the preferred embodiment of the invention, [] each
`
`lead 16 of the perimeter of the matrix 18 defined by rows 20a, 20b, 20c, and 20d
`
`are electrically connected to each other and further connected to ground.” Id.,
`
`4:32-35. This creates a Faraday cage, shielding the interior leads of the matrix
`
`from noise. Id., 4:37-40.
`
`19
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`Verdi teaches another embodiment where “the row(s) of the package that are
`
`grounded in accordance with the invention need not be the outermost row(s).”
`
`Id., 6:13-15. Although not illustrated by Verdi, the modified Figure 3 below shows
`
`an exemplary depiction of this embodiment.
`
`(Figure 3, modified based on Verdi’s alternative embodiment
`described at Ex-1007, 6:13-18)
`
`
`
`As shown, the outer solder balls are signal solder balls, with an interior
`
`
`
`
`
`perimeter of ground solder balls surrounding additional signal solder balls. The
`
`groups of signal balls are split to either side of the ground solder balls, as taught by
`
`Verdi: “certain signals may be ‘partitioned’ by grounding one or more interior
`
`rows of the leads 16. Thus, signal leads disposed within the grounded partition
`
`20
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`will be shielded, while those outside the partition will not.” Id., 6:15-18. In this
`
`arrangement, the inner and outer signal balls are isolated from each other by the
`
`ground solder balls.
`
`D. Huang (Ex-1008)
`U.S. Patent No. 6,359,341, titled “Ball Grid Array Integrated Circuit
`
`Package Structure” (“Huang”), was filed on January 21, 2000 and issued on
`
`September 19, 2002. Huang is therefore effective as prior art to the ’554 Patent
`
`under at least pre-AIA § 102(e). Huang was not of record and was not considered
`
`during prosecution of the ’554 Patent.
`
`Huang discloses “a BGA integrated circuit package, which can be
`
`manufactured utilizing the existent two-layer BGA substrate,” and which “can help
`
`reduce electromagnetic interference,” as shown in Figure 2, below. Ex-1008, 2:35-
`
`42.
`
`21
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`
`
`
`Huang describes the semiconductor package of Figure 2 as having a core
`
`layer (i.e., substrate, brown) with conductive traces formed on the top and bottom
`
`surfaces thereof. Id., 4:26-30. The top-layer conductive traces, among other
`
`traces, include signal traces 301h (green) and ground traces 301c (red). Id., 4:46-
`
`47. Corresponding ground and signal traces are also formed on the second-layer.
`
`Id., 4:48-50. “[S]ignal vias 304b are used to interconnect the first and second
`
`signal traces 301b, 303b, the ground vias 304c are used to interconnect the first and
`
`second ground traces 301c, 303c.” Id., 4:58-61. The bottom layer of the substrate
`
`is also “provided with a plurality of solder balls, including…a plurality of signal
`
`22
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`solder balls 37b, a plurality of ground solder balls 37c,…which are respectively
`
`attached to…the second [signal] traces 303b, [and] the second ground traces 303c.”
`
`Id., 4:62-5:3. A ground path is also created on the periphery of the device using
`
`ground solder balls 37c’ and ground traces 301c’ and 303c’. Id., 5:48-54.
`
`
`
`Huang further teaches that an objective of its disclosure is to provide noise
`
`isolation in “a BGA integrated circuit package, which can be manufactured
`
`utilizing the existent two-layer BGA substrate.” Id., 2:38-41, 5:61-64, 7:49-54,
`
`Fig. 2. Although Huang also discloses a “pre-preg layer 31” with a “ground
`
`metallic layer 32,” a POSA would recognize that these layers are not used for
`
`routing signals, power, or ground in the two-layer substrate. Id., 4:30-33. Huang
`
`teaches that they are used for shielding against electromagnetic radiation and to
`
`make the “combined structure of the substrate 30 and ground metallic layer 32
`
`rigid enough so that it would not be deformed when mounting the substrate 30 onto
`
`the printed circuit board 4.” Id., 5:40-45, 6:27-30.
`
`E.
`Schaper II (Ex-1009)
`The paper entitled “A low-cost, flexible ball-grid-array multichip module
`
`
`
`technology” was published in SPIE Vol. 3184 in August 1997 (“Schaper II”).
`
`Declaration of Sylvia D. Hall-Ellis, Ex-1014. Schaper II was publicly available by
`
`at least September 29, 1997, as shown by its copyright date and its bibliographic
`
`record. Id., ¶¶32a-f; Ex-1017. Schaper II is therefore effective as prior art to the
`
`23
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`’554 Patent under pre-AIA §§ 102(a) and (b). Schaper was not of record and was
`
`not considered during prosecution of the ’554 Patent.
`
`
`
`Schaper II shares two authors, L.W. Schaper and Simon S. Ang, with
`
`Schaper and describes an improvement to the same IMPS system described above
`
`in Schaper. In particular, Schaper II details the implementation of the IMPS
`
`technology using flexible polyimide films for a BGA package. Ex-1009, Abstract.
`
`
`
`This IMPS BGA package structure also includes solder balls, as shown in
`
`Figure 4, below. This structure would have been considered by a POSA to be a
`
`Tape BGA (TBGA), which is a type of PBGA package.
`
`
`
`24
`
`

`

`Petition for Inter Partes Review
`Patent No. 6,825,554
`
`X. Explanation Of Grounds For Invalidity
`A. Ground 1: Schaper In View Of Verdi Renders Obvious Renders
`Obvious Challenged Claims 1-5
`As discussed below, the combination of Schaper and Verdi discloses a
`
`semiconductor package that discloses all limitations of Claims 1-5 of the ’554
`
`Patent. Ex-1002, ¶57. To the extent that any limitation is not expressly disclosed
`
`by this combination, a POSA would have recognized that there were only a finite
`
`number of ways to accomplish the stated goals of the references, and among these,
`
`the structure claimed by the ’554 Patent would have been obvious to try and would
`
`yield predictable results. Id. Accordingly, for the reasons below, Schaper in view
`
`of Verdi re