Trials@uspto.gov
`571-272-7822
`
`
`
` Paper 15
`
`
` Entered: April 11, 2019
`
`
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`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`VLSI TECHNOLOGY LLC,
`Patent Owner.
`____________
`
`Case IPR2018-01296
`Patent 7,675,806 B2
`____________
`
`
`
`Before ROBERT J. WEINSCHENK, MINN CHUNG, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`CHUNG, Administrative Patent Judge.
`
`
`DECISION
`Denying Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`571-272-7822
`
`
`
` Paper 15
`
`
` Entered: April 11, 2019
`
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`VLSI TECHNOLOGY LLC,
`Patent Owner.
`____________
`
`Case IPR2018-01296
`Patent 7,675,806 B2
`____________
`
`
`
`Before ROBERT J. WEINSCHENK, MINN CHUNG, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`
`CHUNG, Administrative Patent Judge.
`
`
`DECISION
`Denying Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`
`IPR2018-01296
`Patent 7,675,806 B2
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`
`I. INTRODUCTION
`Intel Corporation (“Petitioner”) filed a Petition (Paper 2, “Pet.”)
`requesting an inter partes review of claims 11, 12, 13, 15, and 17 (the
`“challenged claims”) of U.S. Patent No. 7,675,806 B2 (Ex. 1101, “the ’806
`patent”). VLSI Technology LLC (“Patent Owner”) filed a Preliminary
`Response (Paper 14, “Prelim. Resp.”).
`By statute, institution of an inter partes review may not be authorized
`unless “the information presented in the petition . . . and any response . . .
`shows that there is a reasonable likelihood that the petitioner would prevail
`with respect to at least 1 of the claims challenged in the petition.” 35 U.S.C.
`§ 314(a). Upon consideration of the Petition and the Preliminary Response,
`we conclude that the information presented does not show there is a
`reasonable likelihood that Petitioner would prevail in establishing the
`unpatentability of any challenged claim of the ’806 patent. Accordingly, we
`do not institute an inter partes review.
`
`II. BACKGROUND
`A. Related Matters
`The parties indicate that the ’806 patent is the subject of the following
`district court litigation: VLSI Technology LLC v. Intel Corporation,
`No. 5:17-cv-05671 (N.D. Cal. Oct. 2, 2017). Pet. 2; Paper 6, 2.
`The ’806 patent is also the subject of petitions for inter partes review
`filed by Petitioner in IPR2018-01034 and IPR2019-00034.1
`
`
`1 The petition in IPR2018-01034 has been dismissed at the request of
`Petitioner. IPR2018-01034, Paper 11 (Decision Granting Petitioner’s
`Unopposed Motion to Dismiss).
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`B. The ’806 Patent
`The ’806 patent describes a low-voltage memory device in an
`integrated circuit. Ex. 1101, [57]. Figure 1 of the ’806 patent is reproduced
`below.
`
`
`Figure 1 is a block diagram of an exemplary system including a memory
`device. Id. at 1:40–41. As shown in Figure 1, integrated circuit 102
`comprises microprocessor core 112, first memory 108, and
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`second memory 110. Id. at 3:9–10. Integrated circuit 102 also includes bus
`interface unit and sleep control unit 114. Id. at 3:10–11.
`As illustrated in Figure 1, integrated circuit 102 is connected to
`external bus 106. Id. at 2:7–8. During operation, integrated circuit 102 can
`communicate with external devices via external bus 106. Id. at 2:15–16. In
`an embodiment, integrated circuit 102 may be incorporated in a multi-core
`device or system such that integrated circuit 102 is accessible to external
`microprocessor cores (not shown) via external bus 106. Id. at 2:16–20.
`As also depicted in Figure 1, bus interface unit and sleep control
`unit 114 of integrated circuit 102 is connected to voltage regulator 104 to
`provide a voltage control signal. Id. at 3:14–17. Voltage regulator 104
`regulates the voltages supplied to integrated circuit 102, which can operate
`in an active mode or low-voltage mode of operation. Id. at 2:21–23.
`According to the ’806 patent, integrated circuit 102 operates with less power
`in the low-voltage mode than in the active mode of operation, albeit with
`reduced functionality. Id. at 2:30–32.
`To enter the low-voltage mode of operation, integrated circuit 102
`instructs voltage regulator 104 to reduce the voltage supplied to integrated
`circuit 102 below the minimum operating voltage for certain portions of
`integrated circuit 102. Id. at 2:56–60. In an embodiment, first memory 108
`has a minimum operating voltage, which is the lowest voltage at which first
`memory 108 can reliably respond to read and write operations. Id. at 3:44–
`47. If the voltage supplied to first memory 108 is below its minimum
`operating voltage, first memory 108 is effectively inaccessible to
`microprocessor core 112 and other devices. Id. at 3:47–50. According to
`the ’806 patent, first memory 108 also has a retention voltage, which is a
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`voltage at which the memory can still retain stored data when the voltage is
`lowered below the minimum operating voltage. Id. at 3:50–56. In other
`words, first memory 108 can retain data stored in the memory when the
`voltage supplied to first memory 108 is below the minimum operating
`voltage but above or at the retention voltage. Id.
`The ’806 patent describes that second memory 110 is a low-voltage
`memory that operates at a lower voltage than first memory 108. Id. at 3:57–
`58. In an embodiment, the minimum operating voltage for second
`memory 110 is lower than the minimum operating voltage for first
`memory 108, but higher than the retention voltage for first memory 108. Id.
`at 3:61–64.
`According to the ’806 patent, in the active mode of operation, the
`voltage supplied to first memory 108 and second memory 110 is sufficiently
`high to allow read and write operations on both memories. Id. at 4:28–31.
`In the low-voltage mode of operation, the voltage supplied to
`first memory 108 is reduced below the first memory’s minimum operating
`voltage, but the voltage supplied to second memory 110 is maintained above
`the minimum operating voltage for the second memory, such that second
`memory 110 remains accessible, although first memory 108 is inaccessible.
`Id. at 4:32–40. Thus, devices connected to external bus 106 can continue to
`access second memory 110 during the low-voltage mode of operation, which
`can reduce the number of times integrated circuit 102 needs to exit the low-
`voltage mode of operation, resulting in reduced power consumption. Id. at
`4:40–45.
`The ’806 patent describes that first memory 108 has a relatively
`high-density memory topology compared to second memory 110 and that
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`microprocessor core 112 can use first memory 108 to store large blocks of
`data. Id. at 3:32–33, 3:41–43. In an embodiment, second memory 110
`mirrors a subset of the data stored in first memory 108. Id. at 5:9–11.
`In another embodiment, second memory 110 stores status data
`associated with first memory 108 (such as status flags or other information)
`to indicate whether data stored in a particular memory location of first
`memory 108 has been changed. Id. at 4:60–64. During the low-voltage
`mode of operation, the data requesting devices can access the status
`information in second memory 110 to determine the status of data stored in
`first memory 108 and perform tasks based on the status information. Id. at
`4:64–5:1. For example, if the status information indicates that the data
`stored at a memory location of first memory 108 has changed, the data
`requesting device can instruct bus interface unit and sleep control unit 114 to
`cause microprocessor core 112 to exit the low-voltage mode of operation.
`Id. at 5:1–6. The requesting device can then access first memory 108 and
`take appropriate action on the changed memory location. Id. at 5:6–8. In an
`alternative embodiment, the requesting device can write data in second
`memory 110 that will replace the data it mirrors in first memory 108 upon
`exiting the low-voltage mode of operation. Id. at 5:9–15.
`
`C. Illustrative Claim
`Of the challenged claims, only claim 11 is independent. Claim 11 is
`illustrative of the challenged claims and is reproduced below.
`11. A device, comprising:
`a first memory located within an integrated circuit, the first
`memory having a first memory cell topology with a first
`minimum operating voltage, the first memory cell
`topology comprising a first arrangement of transistors;
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`a second memory located within the integrated circuit, the
`second memory having a second memory cell topology
`with a second minimum operating voltage, wherein the
`second minimum operating voltage is less than the first
`minimum operating voltage and wherein the second
`memory cell topology comprises a second arrangement of
`transistors, the second arrangement of transistors different
`from the first arrangement of transistors, the second
`memory configured to store status information indicative
`of a status of data stored at the first memory;
`a processing core located at the integrated circuit, the
`processing core operable to:
`access the first memory and the second memory when in a
`first mode of operation, and to access the second
`memory but not the first memory when in a second
`mode of operation;
`access the status information in the second mode of
`operation; and
`enter the first mode of operation in response to the status
`information indicating data corresponding to the data
`stored at the first memory has changed.
`Ex. 1101, 10:31–57.
`
`D. Asserted Prior Art and Grounds of Unpatentability
`Petitioner cites the following references in its challenges to
`patentability.
`
`Reference and Date(s)
`Norman P. Jouppi & Steven J. E. Wilton,
`Tradeoffs in Two-Level On-Chip Caching,
`PROCEEDINGS OF THE 21ST ANNUAL
`INTERNATIONAL SYMPOSIUM ON COMPUTER
`ARCHITECTURE 34, April 27, 1994
`
`Designation Exhibit No.
`
`Jouppi
`
`Ex. 1103
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`Reference and Date(s)
`Li et al., Leakage Energy Management in
`Cache Hierarchies, PROCEEDINGS OF THE 2002
`INTERNATIONAL CONFERENCE ON PARALLEL
`ARCHITECTURES AND COMPILATION
`TECHNIQUES, August 11, 2003
`U.S. Patent No. 5,687,382 (issued Nov. 11,
`1997)
`Krisztián Flautner, et al., Drowsy Caches:
`Simple Techniques for Reducing Leakage
`Power, ISCA ’02 PROCEEDINGS OF THE 29TH
`ANNUAL INTERNATIONAL SYMPOSIUM ON
`COMPUTER ARCHITECTURE 148, June 12, 2002
`
`Designation Exhibit No.
`
`Li
`
`Ex. 1104
`
`Kojima
`
`Ex. 1105
`
`Flautner
`
`Ex. 1106
`
`Petitioner also relies on the Declaration of Bruce Jacob (Ex. 1102,
`“Jacob Declaration” or “Jacob Decl.”).2
`Petitioner asserts the following grounds of unpatentability (Pet. 6).
`
`Claims Challenged
`
`Statutory Basis
`
`References
`
`11, 12, 13, 15, and 17
`
`§ 103(a)3
`
`11, 12, 13, 15, and 17
`
`§ 103(a)
`
`Jouppi, Li, Kojima, and
`Flautner
`Jouppi, Li, and Kojima
`
`
`2 Additionally, Petitioner has submitted a Declaration from Dr. Sylvia Hall-
`Ellis (Ex. 1117) in support of Petitioner’s contention that Jouppi, Li, and
`Flautner qualify as prior art printed publications in this case. Patent Owner
`does not dispute these references qualify as prior art at this time.
`3 The Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284
`(2011) (“AIA”), amended 35 U.S.C. § 103. Because the ’806 patent has an
`effective filing date prior to the effective date of the applicable AIA
`amendments, we refer to the pre-AIA version of § 103.
`
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`
`III. ANALYSIS
`A. Level of Ordinary Skill in the Art
`The parties appear to dispute the level of skill in the art at the time of
`the invention of the ’806 patent. The main point of dispute appears to be the
`level of education and work experience a person of ordinary skill in the art
`would have had at the time of the invention—i.e., at least an undergraduate
`degree in electrical engineering (or an equivalent subject), with at least two
`years of post-graduate experience designing cache systems, according to
`Petitioner (Pet. 31–32 (citing Ex. 1102 ¶¶ 38–39)), as opposed to at least a
`B.S. degree in electrical engineering, computer engineering, or a related
`field, with three years of relevant industry experience, as proposed by Patent
`Owner (Prelim. Resp. 9). Petitioner also asserts that a person of ordinary
`skill in the art with a master’s degree would have had at least one year of
`post-graduate experience. Pet. 32.
`Although the parties’ proposals for the level of skill in the art have
`differences in wording, we do not find the proposals to be materially
`different. For purposes of this Decision, we find no meaningful differences
`between the parties’ respective definitions that would materially alter the
`outcome of this Decision.
`Further, the level of ordinary skill in the art may be reflected by the
`prior art of record. See Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed.
`Cir. 2001) (prior art itself can reflect appropriate level of ordinary skill in the
`art). We find the parties’ definitions to be comparable to the level of skill
`reflected in the asserted prior art. Hence, for purposes of this Decision, the
`prior art itself is sufficient to demonstrate the level of ordinary skill in the
`art.
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`B. Claim Construction
`In this proceeding, claim terms in the unexpired ’806 patent are given
`their broadest reasonable construction in light of the specification of the
`patent. See 37 C.F.R. § 42.100(b) (2017).4 Under the broadest reasonable
`interpretation standard, and absent any special definitions, claim terms
`generally are given their ordinary and customary meaning, as would be
`understood by one of ordinary skill in the art, in view of the specification. In
`re Translogic Tech. Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007).
`Petitioner and Patent Owner propose constructions for only one term,
`namely “second mode of operation” recited in claim 11. Pet. 28–31; Prelim.
`Resp. 10–21. Petitioner asserts that the term “second mode of operation”
`should be construed to mean “when a lower voltage is provided to the first
`and second memory.” Pet. 28. Patent Owner disagrees and argues that the
`term “second mode of operation” should be given its plain and ordinary
`meaning, which is provided in claim 11 itself. Prelim. Resp. 10–12.
`As discussed below, our Decision in this case does not rest on the
`distinctions between these proposed constructions. For purposes of this
`Decision, we determine that no claim term requires express construction.
`See, e.g., Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868
`F.3d 1013, 1017 (Fed. Cir. 2017) (“[W]e need only construe terms ‘that are
`in controversy, and only to the extent necessary to resolve the controversy.’”
`
`
`4 A recent amendment to this rule does not apply here because the Petition
`was filed before November 13, 2018. See “Changes to the Claim
`Construction Standard for Interpreting Claims in Trial Proceedings Before
`the Patent Trial and Appeal Board,” 83 Fed. Reg. 51,340 (Oct. 11, 2018) (to
`be codified at 37 C.F.R. pt. 42).
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`(quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803
`(Fed. Cir. 1999))).
`
`C. Obviousness over Jouppi, Li, Kojima, and Flautner
`Petitioner contends that claims 11, 12, 13, 15, and 17 are unpatentable
`under 35 U.S.C. § 103(a) as obvious over the combination of Jouppi, Li,
`Kojima, and Flautner. Pet. 32–74. In support of its contentions, Petitioner
`submits the Declaration of Bruce Jacob (Ex. 1102). Id. We have reviewed
`the parties’ contentions and supporting evidence. Based on the record
`presented, we are not persuaded that Petitioner has established a reasonable
`likelihood of prevailing on this asserted ground as to any of these challenged
`claims, for the reasons explained below.
`
`1. Relevant Principles of Law
`A claim is unpatentable under 35 U.S.C. § 103(a) if the differences
`between the claimed subject matter and the prior art are such that the subject
`matter, as a whole, would have been obvious at the time the invention was
`made to a person having ordinary skill in the art to which the subject matter
`pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). The
`question of obviousness is resolved on the basis of underlying factual
`determinations, including: (1) the scope and content of the prior art; (2) any
`differences between the claimed subject matter and the prior art; (3) the level
`of skill in the art; and (4) where in evidence, so-called secondary
`considerations.5 Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966). We
`
`
`5 Patent Owner does not present arguments or evidence of such secondary
`considerations in its Preliminary Response. Therefore, secondary
`considerations do not constitute part of our analysis in this Decision.
`
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`analyze this asserted ground based on obviousness with the principles
`identified above in mind.
`
`2. Overview of Jouppi (Ex. 1103)
`Jouppi describes a two-level “on-chip” cache memory system using a
`primary cache and a second level cache. Ex. 1103, Abstract, 34.6
`According to Jouppi, the primary cache (also called the L1 cache) usually is
`divided into separate instruction cache and data cache. Id. at 34. The
`second level cache (called the L2 cache) is a “mixed” cache containing both
`processor instructions and data. Id.
`Jouppi describes that the L2 cache is larger than the L1 cache,
`providing the majority of the cache capacity of the on-chip cache memory.
`Id. According to Jouppi, an important advantage of two-level on-chip
`caching is improved cache access time. Id.
`
`3. Overview of Li (Ex. 1104)
`Li describes an “on-chip L1-L2 cache hierarchy,” consisting of an L1
`instruction cache, an L1 data cache, and a unified L2 cache. Ex. 1104, 2.7
`Table 2 of Li (not reproduced herein) describes that the L2 cache is 4 times
`larger in size than the L1 data cache. Id. at 5. Table 2 also describes that the
`L1 data cache has 32 byte blocks, whereas the L2 cache has 128 byte blocks.
`Id.
`
`
`6 The page numbers for Exhibit 1103 refer to the page numbers of the
`reference as originally published.
`7 The page numbers for Exhibit 1104 refer to the page numbers of the
`reference as originally published.
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`Li describes that a block of L1 cache is the unit of transfer between
`the L1 cache and the L2 cache. Id. at 4. A block of the L1 cache has the
`same size as a sub-block of the L2 cache. Id. According to Li, the sub-
`blocks of the L2 cache moved to the L1 cache are the blocks most recently
`used by the processor on the chip. Id. at 2.
`
`4. Discussion
`In what follows below, we first discuss claim 11, which is the only
`independent claim among the claims challenged in this asserted ground of
`obviousness. We then discuss the rest of the challenged claims, i.e.,
`dependent claims 12, 13, 15, and 17.
`
`a. Claim 11
`In its proposed combination of Jouppi, Li, Kojima, and Flautner,
`Petitioner relies on Jouppi to teach “a first memory located within an
`integrated circuit” and “a second memory located within the integrated
`circuit” recited in claim 11, mapping the L2 cache of Jouppi’s “on-chip”
`cache memory to the claimed “first memory located within an integrated
`circuit” and mapping the L1 cache of Jouppi to the claimed “second memory
`located within the integrated circuit.” Pet. 33–34, 37–38.
`Petitioner contends that the combination of Jouppi and Li teaches “the
`second memory configured to store status information indicative of a status
`of data stored at the first memory,” as recited in claim 11. Id. at 44. In the
`proposed combination, Petitioner relies on Li alone to teach the claimed
`“status information” stored in the second memory. Id. at 48–49.
`Petitioner asserts that Li discloses that the L1 block contains a “dirty”
`bit, which indicates the status of data in the corresponding L2 sub-block. Id.
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`at 48 (quoting Ex. 1104, 4 (“[i]f the block in L1 is evicted, no action is
`performed if the L1 block is not dirty . . . . However, as in other strategies, if
`the evicted L1 block is dirty, the corresponding L2 subblock is reactivated
`. . . .”)).
`The passage of Li quoted by Petitioner, however, does not mention
`the word “dirty bit,” let alone a “dirty bit” stored in a L1 block. Rather, the
`quoted passage merely describes that if a block of the L1 cache is
`determined to be “dirty,” then the corresponding sub-block in the L2 cache
`is reactivated. Ex. 1104, 4. Indeed, Petitioner does not identify, nor do we
`discern, any disclosure in Li of a “dirty bit” or a “dirty bit” stored in a L1
`block.
`Thus, Petitioner does not appear to contend that Li discloses explicitly
`a “dirty bit” stored in a L1 block. Instead, Petitioner asserts that a person of
`ordinary skill in the art would have understood that to determine “if the
`evicted L1 block is dirty,” status information in the form of a dirty bit “must
`necessarily be present” in the L1 block to provide that indication. Pet. 48
`(emphasis added) (citing Ex. 1102 ¶ 170 (“Thus, the L1 cache block
`contains a dirty bit that indicates whether it has been written or not, since
`being brought into the cache.”)). In other words, Petitioner appears to rely
`on inherency to teach a “dirty bit” stored in a L1 block in this asserted
`ground of obviousness.
`As explained by the Federal Circuit, “the use of inherency, a doctrine
`originally rooted in anticipation, must be carefully circumscribed in the
`context of obviousness.” PAR Pharm., Inc. v. TWI Pharm., Inc., 773 F.3d
`1186, 1195 (Fed. Cir. 2014). “A party must . . . meet a high standard in
`order to rely on inherency to establish the existence of a claim limitation in
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`the prior art in an obviousness analysis.” Id. at 1195–1196. “[T]he
`limitation at issue necessarily must be present, or the natural result of the
`combination of elements explicitly disclosed by the prior art.” Id. at 1196
`(emphasis added).
`Under this standard, “[i]nherency . . . may not be established by
`probabilities or possibilities.” Id. at 1195 (quoting In re Oelrich, 666 F.2d
`578, 581 (CCPA 1981)). “‘The mere fact that a certain thing may result from
`a given set of circumstances is not sufficient’ to render the result inherent.”
`Millennium Pharms., Inc. v. Sandoz Inc., 862 F.3d 1356, 1367 (Fed. Cir.
`2017) (emphasis added) (quoting Oelrich, 666 F.2d at 581). Rather,
`Petitioner must “show that the natural result flowing from the operation as
`taught would result in the performance of the questioned function.”
`Personal Web Techs., LLC v. Apple, Inc., 917 F.3d 1376, 1382 (Fed. Cir.
`2019) (citation omitted).
`Applying that standard for inherency, Petitioner does not demonstrate
`sufficiently that Li inherently discloses a dirty bit stored in a L1 cache block.
`Although Petitioner cites a passage of Li that states “if the evicted L1 block
`is dirty, the corresponding L2 subblock is reactivated and written into” (Pet.
`48–49 (quoting Ex. 1104, 4)), Petitioner does not explain how Li determines
`whether a L1 block is dirty (see id.). Dr. Jacob similarly opines that when a
`L1 block is dirty, its corresponding sub-block in the L2 cache is overwritten
`with the dirty data from the L1 cache, but does not explain adequately how
`Li determines whether a L1 block is dirty, or how a person of ordinary skill
`in the art would have understood Li to determine whether a L1 block is dirty.
`Ex. 1102 ¶ 169. Although it may be possible to use a dirty bit stored in a L1
`block when determining whether the L1 block is dirty, mere possibility is
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`not enough. See Personal Web Techs., 917 F.3d at 1382; PAR Pharm., 773
`F.3d at 1195. Thus, neither Petitioner nor Dr. Jacob explains adequately
`why using a dirty bit stored in a L1 cache block is “the natural result flowing
`from” Li’s dirty block determination. See Personal Web Techs., 917 F.3d at
`1382.
`
`Petitioner also presents a figure that purportedly illustrates that each
`32 byte L1 block of Li includes a “dirty bit.” Pet. 49. Petitioner, however,
`does not identify where the figure is found or described in Li. Nor does
`Petitioner identify any other prior art as the source of the figure or cite any
`evidence in support of the figure. See id. Patent Owner asserts that the
`figure on page 49 of the Petition is “Petitioner’s own manufactured figure,”
`which is mere attorney argument, not evidence. Prelim. Resp. 48. We agree
`with Patent Owner that Petitioner’s figure on page 49 amounts to no more
`than a conclusory assertion unsupported by evidence.
`Thus, based on the record presented, Petitioner’s argument and
`evidence does not demonstrate sufficiently that a teaching of a dirty bit
`stored in a L1 cache block is inherent in Li.
`As discussed above, inherency appears to be the only theory of
`unpatentability presented in the Petition to teach the claimed “status
`information” stored in the second memory. “In an IPR, the petitioner has the
`burden from the onset to show with particularity why the patent it challenges
`is unpatentable.” Harmonic Inc. v. Avid Tech., Inc., 815 F.3d 1356, 1363
`(Fed. Cir. 2016)) (citing 35 U.S.C. § 312(a)(3)). Based on the record
`presented, we conclude that stating that status information in the form of a
`dirty bit must necessarily be present in the L1 block without adequate
`explanation does not satisfy Petitioner’s burden required for institution of a
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`review under the particular facts and circumstances of this case. See
`35 U.S.C. § 312(a)(3). See also Intelligent Bio-Sys., Inc. v. Illumina
`Cambridge Ltd., 821 F.3d 1359, 1369 (Fed. Cir. 2016) (“[T]he expedited
`nature of IPRs bring with it an obligation for petitioners to make their case
`in their petition to institute.” (emphasis added)); Colas Sols., Inc. v.
`Blacklidge Emulsions, Inc., No. 2018-1358, 2019 WL 1380044, at *3–*5
`(Fed. Cir. Mar. 27, 2019) (nonprecedential) (when inherency was the only
`theory presented in the Petition for a disputed claim element, a broader
`obviousness theory unrelated to inherency raised by Petitioner in a reply was
`improper); Cf. Sirona Dental Sys. GmbH v. Institut Straumann AG, 892 F.3d
`1349, 1356 (Fed. Cir. 2018) (“It would . . . not be proper for the Board to
`deviate from the grounds in the petition and raise its own [unpatentability]
`theory.”) (citing SAS Inst., Inc. v. Iancu, 138 S. Ct. 1348, 1356–57 (2018)).
`Accordingly, based on the record presented, we conclude that the
`information presented in the Petition does not demonstrate a reasonable
`likelihood of Petitioner prevailing in its challenge to claim 11 under
`35 U.S.C. § 103(a) as obvious over the combination of Jouppi, Li, Kojima,
`and Flautner.
`
`b. Dependent Claims 12, 13, 15, and 17
`Claims 12, 13, 15, and 17 each depend directly from claim 11.
`Petitioner’s arguments and evidence presented with respect to these
`dependent claims only address the additionally recited limitations of the
`dependent claims and, therefore, do not remedy the deficiencies in
`Petitioner’s analysis of claim 11 discussed above. See Pet. 68–74.
`Accordingly, based on the record presented, the information presented
`in the Petition does not demonstrate a reasonable likelihood of Petitioner
`
`17
`
`
`
`IPR2018-01296
`Patent 7,675,806 B2
`
`prevailing in its challenge to claims 12, 13, 15, and 17 under 35 U.S.C.
`§ 103(a) as obvious over the combination of Jouppi, Li, Kojima, and
`Flautner.
`
`D. Obviousness over Jouppi, Li, and Kojima
`In the alternative, Petitioner asserts that the challenged claims are
`unpatentable over the combination of Jouppi, Li, and Kojima. Pet. 74–77.
`The two alternative grounds of obviousness presented in the Petition are
`nearly identical, the only difference being which of the two alternative
`interpretations of the term “second mode of operation” (i.e., Petitioner’s
`proposed construction or the plain language meaning) is used to map the
`limitation Petitioner identifies as limitation 11[j] (reciting “access the second
`memory but not the first memory when in a second mode of operation”) to
`the cited prior art. See id. at 55–59, 74–77. Under Petitioner’s proposed
`construction of the term “second mode of operation,” Petitioner relies on the
`combination of Li, Kojima, and Flautner to teach limitation 11[j]. Id. at 55–
`59. In this asserted ground of obviousness, Petitioner relies on Li alone to
`teach limitation 11[j] under the plain meaning interpretation of “second
`mode of operation.” Id. at 74–77. The two asserted grounds of obviousness
`are identical in all other aspects. See id. at 74.
`Petitioner identifies as limitation 11[g] the limitation reciting “the
`second memory configured to store status information indicative of a status
`of data stored at the first memory.” Id. at 44. In this asserted ground of
`obviousness, Petitioner merely refers to its previous analysis of limitation
`11[g] discussed above in Section III.C., and relies on the same argument and
`evidence to teach limitation 11[g]. Id. at 74. Therefore, for the same
`reasons discussed above in Section III.C., the information presented in the
`
`18
`
`
`
`IPR2018-01296
`Patent 7,675,806 B2
`
`Petition does not demonstrate a reasonable likelihood of Petitioner
`prevailing in its challenge to claims 11, 12, 13, 15, and 17 under 35 U.S.C.
`§ 103(a) as obvious over the combination of Jouppi, Li, and Kojima.
`
`E. Remaining Issues
`Patent Owner asserts that we should exercise our discretion to deny
`institution under 35 U.S.C. § 325(d). Prelim. Resp. 21–25. Patent Owner
`also argues that institution of an inter partes review in this case would
`violate the U.S. Constitution. Id. at 50–52.
`Because we conclude Petitioner does not demonstrate a reasonable
`likelihood of prevailing on any asserted ground of unpatentability, we need
`not reach either of these issues.
`
`IV. CONCLUSION
`Based on the arguments and evidence presented in the Petition, we
`conclude Petitioner has not demonstrated a reasonable likelihood that
`Petitioner would prevail in showing at least one of the challenged claims of
`the ’806 patent is unpatentable based on any asserted ground of
`unpatentability. Therefore, we do not institute an inter partes review with
`respect to any of the challenged claims of the ’806 patent.
`
`
`V. ORDER
`In consideration of the foregoing, it is hereby:
`ORDERED that Petitioner’s request for an inter partes review is
`denied as to all challenged claims of the ’806 patent, and no trial is
`instituted.
`
`
`
`
`19
`
`
`
`IPR2018-01296
`Patent 7,675,806 B2
`
`PETITIONER:
`John Hobgood
`john.hobgood@wilmerhale.com
`
`Donald Steinberg
`don.steinberg@wilmerhale.com
`
`PATENT OWNER:
`
`Michael Fleming
`mfleming@irell.com
`
`Benjamin Hattenbach
`bhattenbach@irell.com
`
`Amy Proctor
`aproctor@irell.com
`
`20
`
`
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