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`IPR2018-01334
`U.S. Patent No. 8,838,949
`Petitioner’s Opening Brief on Remand
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`QUALCOMM INCORPORATED,
`Patent Owner.
`____________________________________________
`
`
`IPR2018-01334
`U.S. Patent No. 8,838,949
`____________________________________________
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`PETITIONER’S OPENING BRIEF ON REMAND1
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`1 IPR2018-01335 and IPR2018-01336 have been consolidated with IPR2018-
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`01334, and Petitioner will file this brief only in IPR2018-01334. All citations are
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`to IPR2018-01334 unless otherwise noted.
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`

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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`TABLE OF CONTENTS
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`
`I.
`
`INTRODUCTION ........................................................................................... 1
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`II.
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`STATEMENT OF FACTS AND PROCEDURAL HISTORY ....................... 2
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`A.
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`“Hardware Buffer” Limitation .............................................................. 2
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`B. Means-Plus-Function Limitations ......................................................... 3
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`C.
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`Issues On Remand ................................................................................. 4
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`III. ARGUMENT ................................................................................................... 5
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`A.
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`“Hardware Buffer” Should Be Given The Broadest Reasonable
`Interpretation Supported By The Intrinsic Record. ............................... 5
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`1.
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`2.
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`3.
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`Petitioner’s proposed claim construction is consistent
`with the Federal Circuit’s opinion and the claim
`language. ..................................................................................... 5
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`The specification supports Petitioner’s proposed claim
`construction. ................................................................................ 7
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`The prosecution history supports Petitioner’s proposed
`claim construction. .................................................................... 11
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`The Intermediate Storage Area Of Bauer And Svensson Is A
`“Hardware Buffer.” ............................................................................. 13
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`Claims 16 And 17 Are Obvious In Light Of The Proposed Prior
`Art Or, At The Very Least, Indefinite. ................................................ 17
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`1.
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`2.
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`The Board should find claims 16-17 unpatentable. .................. 18
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`If the Board finds it is logically impossible to render a
`decision on patentability of claims 16-17, it should find
`that it is impossible to reach a decision on the merits. ............. 20
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`B.
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`C.
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`IV. CONCLUSION .............................................................................................. 20
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`i
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`TABLE OF AUTHORITIES
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`Page(s)
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`CASES
`Intel Corp. v. Qualcomm Inc., 21 F.4th 801 (Fed. Cir. 2021)
` ........................................................................................ 4, 5, 6, 12, 18, 19, 20
`Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d
`1013 (Fed. Cir. 2017)..................................................................................... 19
`STATUTES, RULES, AND REGULATIONS
`83 Fed. Reg. 51,340 (Oct. 11, 2018) .......................................................................... 5
`35 U.S.C. § 103 .......................................................................................................... 2
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`ii
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`INTRODUCTION
`This consolidated Inter Partes Review proceeding is before the Board on
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`I.
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`remand from the Federal Circuit. In its Final Written Decision, the Board found
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`claims 10, 11, 13-15, and 18-23 of U.S. Patent No. 8,838,949 (“the ’949 patent”)
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`obvious but held that Petitioner had not proven by a preponderance of the evidence
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`that claims 1-9, 12, 16, and 17 were unpatentable. The Board found that “hardware
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`buffer” “‘should not be read so broadly as to encompass’ the use of a temporary
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`buffer” (FWD (Paper 30) at 17) and claims 1-9 and 12 were not obvious under that
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`negative construction. The Board also declined to determine whether there was
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`structure corresponding to the mean-plus-function terms of claims 16 and 17.
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`Instead, it found that Petitioner failed to carry its burden of providing adequate
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`evidence of the corresponding structure.
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`On appeal, the Federal Circuit remanded, instructing the Board to properly
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`construe “hardware buffer,” determine whether claims 1-9 and 12 are obvious under
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`that construction, and determine whether the Board can resolve the prior art
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`challenge to the patentability of claims 16 and 17 despite the potential indefiniteness
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`of the means-plus-function terms or whether the terms are indefinite and it is
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`impossible to adjudicate the prior art challenge on its merits. Petitioner asks the
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`Board to (1) adopt its proposed claim construction for “hardware buffer”; (2) hold
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`claims 1-9 and 12 unpatentable under this construction; and (3) find claims 16 and 17
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` 1
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`obvious and/or indefinite.
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`II.
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`STATEMENT OF FACTS AND PROCEDURAL HISTORY
`In July 2018, Petitioner filed these Petitions challenging all claims of the ’949
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`patent as unpatentable under 35 U.S.C. § 103 based on four references, two of which
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`are discussed here: Bauer (Ex. 1009) and Svensson (Ex. 1010).
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`The ’949 patent claims to solve certain inefficiencies in prior art multi-processor
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`systems by allowing data to be loaded to a secondary processor’s system memory
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`without copying the entire software image from a buffer. Ex. 1001 (’949 patent) at
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`9:42-56. However, the system and methods of the ’949 patent were routine and well-
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`known in the prior art. Multi-processor systems and the direct transfer of data between
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`processors were disclosed in multiple prior art references, some of which were not
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`before the Patent Office during the original prosecution.
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`A.
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`“Hardware Buffer” Limitation
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`Petitioner did not originally propose a claim construction for the term “hardware
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`buffer,” but argued that the “intermediate storage area” (“ISA”) in Bauer and Svensson
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`is a “hardware buffer” under the term’s plain meaning and the broadest reasonable
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`interpretation standard that applies here. See Petition (Paper 3) at 26-27; IPR2018-
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`01335 Petition (Paper 3) at 61-62. In its Institution Decision, the Board agreed that
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`Bauer and Svensson’s ISA is a “hardware buffer” because “[t]he intermediate storage
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`area of Bauer and Svensson is a buffer used to store data destined for another
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` 2
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`memory, and the intermediate storage area is in hardware inasmuch as SARAM and
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`DARAM [of Bauer and Svensson] are hardware.” See ID (Paper 10) at 27.
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`Following institution, Patent Owner construed “hardware buffer” as “a buffer
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`within a hardware transport mechanism that receives data sent from the primary
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`processor to the secondary processor.” POR (Paper 16) at 14. Under this construction,
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`Patent Owner argued that the ISA of Bauer and Svensson was not the “hardware
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`buffer” of the ’949 patent. Id. at 52-53. In its Reply, Petitioner argued that Patent
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`Owner’s transport mechanism construction improperly limited the claims to a single
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`exemplary embodiment, and that “hardware buffer” should be understood under its
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`BRI plain meaning as a “buffer implemented in hardware.” Petitioner’s Reply (Paper
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`21) at 8-11. In its Sur-Reply, Patent Owner pivoted to arguing that “hardware buffers”
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`cannot cover temporary buffers, which are “prior art embodiments … distinguished in
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`the ‘949 patent.” Patent Owner’s Sur-Reply (Paper 25) at 11-13.
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`B. Means-Plus-Function Limitations
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`The Petition identified functions and structures corresponding to the means-
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`plus-function terms of claim 16, from which claim 17 depends: (1) “means for
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`receiving at a secondary processor … an image header…”; (2) “means for
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`processing …”; (3) “means for receiving at the secondary processor … each data
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`segment…”; and (4) “means for scatter loading ….” See IPR2018-01335 Petition
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`(Paper 3) at 17-22. Notably, these constructions were proposed by Patent Owner in
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`a related ITC action in which the ’949 patent was asserted. See Ex. 1008 (joint
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`claim construction charts) at 4-6.
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`In its Institution Decision, the Board agreed with the identified functions but
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`questioned the adequacy of the corresponding structure in Patent Owner’s
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`construction for the “means for processing” and “means for scatter loading” terms.
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`IPR2018-01335 ID (Paper 10) at 13-15.
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`C.
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`Issues On Remand
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`On January 14, 2020, the Board issued its Final Written Decision, finding
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`that Petitioner failed to show that claims 1-9, 12, and 16-17 were unpatentable.2 On
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`appeal, the Federal Circuit agreed with Petitioner and vacated the Board’s decision
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`with respect to claims 1-9, 12, and 16-17 and remanded for further proceedings.
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`See Intel Corp. v. Qualcomm Inc., 21 F.4th 801, 814 (Fed. Cir. 2021).
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`On February 22, 2022, the Board authorized the parties to file briefing on a
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`discrete set of issues on remand: (1) the broadest reasonable interpretation of
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`“hardware buffer,” (2) the applicability of the construction of “hardware buffer” to the
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`asserted prior art, and (3) whether the Board can resolve the prior art challenge to the
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`patentability of claims 16 and 17. Order on Remand (Paper 34) at 2-3. Petitioner
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`2 Patent Owner did not cross-appeal the Board’s finding that claims 10, 11, 13-15 and
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`18-23 are unpatentable. Those claims are invalidated and are not at issue here.
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` 4
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`addresses these issues below.
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`III. ARGUMENT
`A.
`“Hardware Buffer” Should Be Given The Broadest Reasonable
`Interpretation Supported By The Intrinsic Record.
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`The “hardware buffer” limitation in claims 1-9 and 12 should be construed as
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`“memory that is physically separate from the memory into which the software image is
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`loaded for execution.” Ex. 1026 (Lin Remand Decl.) at ¶ 11. Because the IPR
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`Petitions at issue were filed before November 13, 2018, the challenged claims must be
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`given the broadest reasonable interpretation in light of the patent specification. See 83
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`Fed. Reg. 51,340 (Oct. 11, 2018). Here, neither intrinsic nor extrinsic evidence
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`supports a narrower interpretation than the one proposed by Petitioner.
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`1.
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`Petitioner’s proposed claim construction is consistent with the
`Federal Circuit’s opinion and the claim language.
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`
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`Petitioner’s construction is consistent with the claim language, the Federal
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`Circuit’s conclusions regarding that language, and the Board’s conclusion that the
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`claim language “does not define what implementation the hardware buffer must take or
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`what type of storage device the hardware buffer is.” FWD (Paper 30) at 13.
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`
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`First, Petitioner’s construction gives more meaning to the term “hardware
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`buffer” than “just a ‘buffer implemented in hardware,’” as the Federal Circuit
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`concluded. Intel, 21 F.4th at 809-810.
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` 5
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`Second, Petitioner’s construction is consistent with the Federal Circuit’s
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`guidance that “[b]ecause claim 1 requires both a ‘system memory’ and a ‘hardware
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`buffer,’” “there must be some distinction between those two concepts.” Id. at 810.
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`Independent claim 1 of the ’949 patent requires a “system memory and a hardware
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`buffer for receiving an image header and at least one data segment of an executable
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`software image” and a scatter load controller “to scatter load each received data
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`segment … directly from the hardware buffer to the system memory.” Petitioner’s
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`construction is consistent with this claim language and the Federal Circuit’s guidance
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`in that the “hardware buffer” is physically separate from the claimed “system
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`memory.” At the same time, Petitioner’s construction “does not foreclose the
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`possibility of implementing a [hardware] buffer in some other system memory,” as the
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`Board observed. FWD (Paper 30) at 13; Ex. 1026 (Lin Remand Decl.) at ¶¶ 12-18.
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`
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`Third, under Petitioner’s construction, the executable software image may be
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`moved directly from the hardware buffer to the final location in system memory from
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`which it is executed, as the Federal Circuit noted. See Intel, 21 F.4th at 810. This,
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`however, should not foreclose the possibility of moving the executable image from
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`some other physically separate system memory that serves as a “hardware buffer” to
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`the final location in the claimed system memory. Ex. 1026 (Lin Remand Decl.) at
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`¶ 18. Dependent claim 2 limits claim 1 by requiring that the executable software
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`image be loaded “without copying data between system memory locations on the
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` 6
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`secondary processor.” This further limiting of claim 1 confirms that neither claim 1
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`nor its “hardware buffer” limitation precludes the possibility of copying data between
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`system memory locations. Id. at ¶ 19. When Patent Owner wanted to narrow the
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`claims, it drafted claims to include the narrow features. Moreover, the point of claim 2
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`is to preclude copying data between locations within the claimed system memory, not
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`to preclude copying data from a physically separate system memory to the claimed
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`system memory. Id.
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`2.
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`The specification supports Petitioner’s proposed claim
`construction.
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`
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`The Board noted that the “[t]he written description of the ’949 patent, which
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`uses the term ‘hardware buffer’ only three times (Ex. 1001, 2:58-63, 9:37-41), does not
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`provide much, if any, guidance on what a ‘hardware buffer’ must be.” FWD (Paper
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`30) at 15. The specification only provides that the “hardware buffer” receives “at least
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`a portion of an executable software image,” which is directly loaded from the
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`“hardware buffer” to the “system memory.” Ex. 1001 (’949 patent) at 2:58-63; see
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`also id. at 9:37-41 (in one embodiment, “an entire executable software image” is not
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`stored in the “hardware buffer”).
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` From the above disclosure, it is clear that the “hardware buffer” is a storage area
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`that is physically separate from the claimed “system memory” but is not otherwise
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`limited in its location. Ex. 1026 (Lin Remand Decl.) at ¶ 15. The claimed system
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`memory, on the other hand, is repeatedly described by the specification as a memory
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`where an executable software image can be loaded and executed. See, e.g., Ex. 1001
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`(’949 patent) at 2:61-63 (describing “loading the executable software image directly
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`from the hardware buffer to the system memory”); id. at 5:31-35 (referring to RAM
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`112). This understanding is supported by both Petitioner’s and Patent Owner’s
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`experts. See Ex. 1026 (Lin Remand Decl.) at ¶ 16; Ex. 1023 (Lin Reply Decl.) at ¶¶ 9-
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`14; Ex. 1022 (Rinard Dep.) at 61:9-14 (“Q. Do you agree with Dr. Lin that system
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`memory is memory where programs can be loaded and executed by a processor? A.
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`That’s one of the things that system memory does, that you can do with system
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`memory....”); Ex. 2001 (Lin Dep.) at 25:10-12 (testifying “a system memory would be
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`a portion of the memory where programs could be loaded and executed”). It is also
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`supported by the common understanding of system memory to a POSITA. Ex. 1026
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`(Lin Remand Decl.) at ¶ 16. In sum, a POSITA would understand that “hardware
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`buffer” is memory that is physically separate from the memory into which the software
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`image is loaded for execution. See id. at ¶ 17.
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`Beyond being separate from the claimed system memory, the hardware buffer is
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`not described as being, and a POSITA would not understand it as being, located in any
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`particular area within the secondary processor. See Ex. 1026 (Lin Remand Decl.) at
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`¶¶ 18-20; Ex. 1023 (Lin Reply Decl.) at ¶ 23. No other part of the specification
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`explicitly limits the scope of “hardware buffer.” The Board should not import from the
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`specification the erroneous conclusion that a “hardware buffer” excludes the use of
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`“temporary buffers.” FWD (Paper 30) at 16 (citing ’949 patent at 2:23–34, 4:43–47,
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`5:31–35). The specification, as discussed below, aims to distinguish what is claimed
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`from other aspects of the prior art, not the use of temporary buffers per se.
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`
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`First, the ’949 patent contends that it improves upon conventional techniques
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`for transferring data “in favor of a more efficient direct loading process,” which allows
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`the loading of image segments instead of the entire executable software image. See
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`Ex. 1001 (’949 patent) at 9:43-46; see also id. at 9:37-43; id. at 9:46-54 (“the
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`exemplary load process of FIG. 3 does not require the intermediate buffer operations
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`…. Instead of scatter loading from a temporary buffer holding the entire image, the
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`exemplary load process of FIG. 3 allows for direct scatter load [sic] the image
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`segments to their respective target destinations directly from the hardware to the
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`system memory.”). The specification, therefore, distinguishes systems in which the
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`entire executable software image is copied into a temporary buffer. Ex. 1026 (Lin
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`Remand Decl.) at ¶ 23. In fact, the only time the specification uses the terms
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`“hardware buffer” and “temporary buffer” together distinguishes the patented
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`technique from storing the entire executable software image in the hardware buffer.
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`See Ex. 1001 (’949 patent) at 9:37-46 (loading technique occurs “without an entire
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`executable software image stored in the hardware buffer” and, consistently, prior art
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`“conventional techniques employing a temporary buffer for the entire image” are
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`bypassed). Ex. 1026 (Lin Remand Decl.) at ¶¶ 23-24.
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`Second, the ’949 claims require an image header that is separately received from
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`data segments and, in discussing temporary buffers, the specification focuses on prior
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`art approaches of copying packets with both headers and payloads into temporary
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`buffers. See Ex. 1001 (’949 patent) at claim 1 (“the image header and each data
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`segment being received separately”); 2:25-28 (“one way of performing such loading is
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`to allocate a temporary buffer into which each packet is received, and each packet
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`would have an associated packet header information along with the payload”); 2:50-
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`54 (“The packets are stored in an intermediate buffer, and some processing of the
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`received packets is then required for that data to be stored where it needs to go”); see
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`also id. at 2:14-22. The only distinction these parts of the specification make is
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`between the buffer receiving a header separately from data segments (as claimed) and
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`receiving a packet that includes both a header and data segments, and not that the
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`buffer is temporary. Ex. 1026 (Lin Remand Decl.) at ¶¶ 25-26.
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`Likewise, the specification’s discussion at column 4, lines 43-47 about avoiding
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`“use of a temporary buffer” must be read in light of the surrounding context. This
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`portion of the specification begins with, “[i]n one exemplary embodiment,” and is
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`followed by a discussion of the loading technique: “[f]or instance, … rather than
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`employing a packet-based communication in which the image is communicated via
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`10
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`packets that each include a respective header, the raw image data is loaded ….” Ex.
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`1001 (’949 patent) at 4:43-52. This portion of the specification, therefore, also
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`distinguishes receiving a packet that includes both a header and data segments, not the
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`use of temporary buffers for all purposes. Ex. 1026 (Lin Remand Decl.) at ¶ 27.
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`Third, column 5, lines 31-35, does not preclude the “hardware buffer” from
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`being a temporary buffer. FWD (Paper 30) at 16. Here, the specification describes
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`transferring the executable image into the final location in the system memory (i.e.,
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`RAM 112), without copying the data into a temporary buffer in the same system
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`memory (i.e., RAM 112). See Ex. 1001 (’949 patent) at 5:31-35. This part of the
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`specification does not teach against the use of all temporary buffers, but instead only
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`those in the same physical memory (i.e., RAM 112) into which the executable image
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`is loaded for execution. Ex. 1026 (Lin Remand Decl.) at ¶ 28.
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`Even if these passages are understood as teaching against use of a “temporary
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`buffer,” the specification repeatedly emphasizes that these are exemplary
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`embodiments. See, e.g., Ex. 1001 (’949 patent) at 4:43-47 (“In one exemplary aspect a
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`direct scatter load technique is disclosed …”); Ex. 1026 (Lin Remand Decl.) at ¶ 29.
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`3.
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`The prosecution history supports Petitioner’s proposed claim
`construction.
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`Finally, the prosecution history provides significant guidance on the broadest
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`reasonable interpretation of “hardware buffer.” In rejecting the pending claims in light
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`11
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`of Svensson during prosecution, the Examiner expressly identified Svensson’s ISA as a
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`“hardware buffer”: “Svensson teaches a secondary processor [client processor 104]
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`comprising system memory [DSP XRAM 110] and a hardware buffer [An intermediate
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`storage area is defined within the memory 108] for receiving at a [sic] least a portion of
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`an executable software image.” Ex. 1004 (7/19/13 Office Action) at 2.
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`Instead of arguing that Svensson lacked a “hardware buffer,” Patent Owner
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`amended the claims to overcome the rejection by adding new limitations relating to the
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`separate receipt of the image header and data segments. See Ex. 1005 (10/17/13
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`Response) at 2 (amending claim 1 to require “the image header and each data segment
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`being received separately” and a scatter loader controller configured “to load the image
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`header” and “to scatter load each received data segment based at least in part on the
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`loaded image header.”). Patent Owner explicitly relied on these new limitations in
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`attempting to distinguish Svensson. Id. at 8-9. These prosecution amendments and
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`arguments make clear that the “asserted advance” of the ’949 patent, Intel, 21 F.4th at
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`811, was not the “hardware buffer.” Ex. 1026 (Lin Remand Decl.) at ¶¶ 31-33.
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`Rather, it was the very elements added by amendment, including the separate receipt of
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`12
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`the header and data segments, that the specification uses to distinguish the prior art that
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`constitute the asserted advance. See supra Section III.A.2.3
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`Given the lack of narrowing language in the claims and specification, the BRI
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`standard, and the Examiner’s understanding of the term during prosecution, it would be
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`improper to adopt a construction of “hardware buffer” that excludes Svensson’s ISA.
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`On the other hand, construing “hardware buffer” as “memory that is physically
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`separate from the memory into which the software image is loaded for execution” is
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`consistent with the claims, specification, and prosecution history.
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`B.
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`The Intermediate Storage Area Of Bauer And Svensson Is A
`“Hardware Buffer.”
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`Under the correct construction of “hardware buffer,” Bauer and Svensson
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`combined disclose this limitation. Ex. 1026 (Lin Remand Decl.) at ¶¶ 34-38. As
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`explained in the Petitions, Bauer’s secondary processor comprises a DSP CPU 204
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`coupled to a “system memory” (DSP XRAM 210), and a separate “hardware buffer”
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`(ISA within the DSP SARAM & DARAM memory 208). Petition (Paper 3) at 26-27;
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`IPR2018-01335 Petition (Paper 3) at 61-62; Ex. 1009 (Bauer) at ¶¶ 35-36, Fig. 2; see
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`also Ex. 1010 (Svensson) at 3:54-58, 3:64-4:5, Fig. 1 (similar). As the Petitions also
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`3 Bauer and/or Kim (Ex. 1012), which disclose or render obvious these new
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`limitations, were not before the Patent Office during prosecution.
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`explain, Bauer and Svensson combined disclose that the secondary processor transfers
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`IPR2018-01334
`U.S. Patent No. 8,838,949
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`the image—different parts of the image are loaded to the hardware buffer and then to
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`the system memory, one part at a time—directly from the hardware buffer to the
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`system memory (DSP XRAM 110/210) for execution. Petition (Paper 3) at 45-46;
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`IPR2018-01335 Petition (Paper 3) at 45-57, 61-62; Ex. 1009 (Bauer) at ¶¶ 27, 31-36,
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`41, 43 (describing how the parts of the image can be stored in the system memory),
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`Figs. 1A-1C; Ex. 1010 (Svensson) at 5:21-28, 5:65-67, 6:12-15, Figs. 1-3. In
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`Svensson, while the ISA (the claimed “hardware buffer”) is responsible for temporarily
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`storing the software image, the software image is loaded to the separate DSP XRAM
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`(the claimed “system memory”) for execution.4 See Ex. 1002 (Lin Op. Decl.) at ¶ 80
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`(citing Ex. 1010 (Svensson) at 5:21-36 and Fig. 1 and describing how Svensson
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`reserves the ISA “for intermediate storage of information (code and/or data) to be
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`4 As discussed above, during prosecution, the Examiner rejected the challenged claims,
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`finding that Svensson taught most of the claim limitations, including the “hardware
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`buffer.” Ex. 1004 (7/19/13 Office Action) at 2. Patent Owner did not contend that
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`Svensson failed to disclose the “hardware buffer.” See Ex. 1005 (10/17/13 Response)
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`at 2, 8-9. This reinforces that the ISA of Bauer and Svensson is the claimed “hardware
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`buffer.”
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`transferred to the [client]-private memory, i.e., the memory that is invisible to the host,
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`such as ‘external’ XRAM 110”); Ex. 1022 (Rinard Dep.) at 108:21-109:4.
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`Bauer and Svensson’s ISA is physically separate from the claimed system
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`memory. First, Bauer and Svensson’s ISA is physically separate and distinct from
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`Bauer and Svensson’s DSP XRAM 110/210, which is the claimed “system memory.”
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`Ex. 1026 (Lin Remand Decl.) at ¶ 40. Bauer and Svensson combined disclose two
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`distinct and physically separate memories on its secondary processor: ISA within DSP
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`SARAM & DRAM 208/108 and external DSP XRAM 210/110. Ex. 1009 (Bauer) at
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`¶¶ 35-36, Fig. 2; Ex. 1010 (Svensson) at 3:64-4:3, Fig. 1. As the Board correctly
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`noted, “nothing in claim 1 [] prohibits the claimed ‘hardware buffer’ from being part of
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`some system memory,” ID (Paper 10) at 26, and the “recitation of a separate system
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`memory, by itself, does not foreclose the possibility of implementing a buffer in some
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`other system memory,” FWD (Paper 30) at 13. Even if the Board were to find that the
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`ISA is part of some system memory (as Patent Owner incorrectly argued in its Sur-
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`Reply (Paper 25) at 17-22), therefore, Bauer and Svensson combined still disclose a
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`“hardware buffer” because the DSP XRAM 110/210 (the “system memory” of the ’949
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`claims) is physically separate and distinct from the ISA. Ex. 1026 (Lin Remand Decl.)
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`at ¶ 40.
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`Second, the ISA is not part of any “system memory” because it is not part of any
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`memory where an executable image can be loaded and executed. See Petitioner’s
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`15
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`Reply (Paper 21) at 5-6, 32-35; Ex. 1023 (Lin Reply Decl.) at ¶ 67. Rather, the ISA is
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`reserved only for temporarily storing information to be transferred to the system
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`memory (DSP XRAM 210/110) for later execution. Ex. 1023 (Lin Reply Decl.) at
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`¶ 67; Ex. 1026 (Lin Remand Decl.) at ¶ 41. Patent Owner’s expert, Dr. Martin Rinard,
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`admitted that Svensson does not execute code from the ISA. Ex. 1022 (Rinard Dep.) at
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`107:8-108:4. Svensson states that the ISA is “reserved … for intermediate storage” at
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`bootup and is available for transfers any time afterward. Ex. 1010 (Svensson) at 5:21-
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`28, 8:17-21, 8:29-32 (“one can load and execute new software in the [client processor]
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`virtually any time the host processor is running,” meaning that the ISA is permanently
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`reserved for intermediate storage for the loading process), Fig. 2 (blocks 208-212 show
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`the reservation of the ISA at bootup); Ex. 1026 (Lin Remand Decl.) at ¶ 41. Neither
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`Svensson nor Bauer ever states that the ISA is deallocated for later use as a memory
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`from which code can be loaded and executed. Id.; Ex. 1023 (Lin Reply Decl.) at ¶ 67.
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`Even if the ISA is considered to be part of some system memory prior to being
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`“reserved” as Patent Owner incorrectly contends (see Sur-Reply (Paper 25) at 17-22),
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`after it is reserved the ISA functions solely and permanently as a hardware buffer.
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`Because Bauer and Svensson never disclose deallocation of the ISA, the sole purpose
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`of the ISA is that of a “hardware buffer” that meets the ’949 patent requirements. Ex.
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`1026 (Lin Remand Decl.) at ¶¶ 42-43.
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`16
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`Finally, even if “hardware buffer” is construed more narrowly than proposed by
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`Petitioner, the Board should still find the challenged claims obvious. Specifically,
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`even under a construction that excludes temporary buffers, the ISA would satisfy the
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`“hardware buffer” limitation, since the ISA is never deallocated and instead functions
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`solely as a permanent buffer. Ex. 1026 (Lin Remand Decl.) at ¶¶ 41, 44-45.
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`Moreover, it is undisputed that “hardware buffers” existed in the prior art to the
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`’949 patent. Patent Owner’s expert unequivocally agreed that “[m]any different
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`systems included hardware buffers, and those systems existed before the ’949 patent.”
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`Ex. 1022 (Rinard Dep.) at 43:11-17. In addition, ’949 patent inventor Steve
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`Haechnichen agreed that hardware buffers were well-known before the patent. See Ex.
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`2004 (Trial Transcript Day 2) at 236:2-12. Given the well-known use of “hardware
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`buffers” in the prior art, this limitation does not render patentable claims that are
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`otherwise unpatentable. Instead, a POSITA would have understood a “hardware
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`buffer” to have been obvious based on Bauer and Svensson, regardless of how the term
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`“hardware buffer” is construed. Ex. 1026 (Lin Remand Decl.) at ¶ 46.
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`C. Claims 16 And 17 Are Obvious In Light Of The Proposed Prior Art
`Or, At The Very Least, Indefinite.
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`As the Federal Circuit instructed, the Board must determine whether it can
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`resolve the prior art challenge to the patentability of claims 16 and 17 despite the
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`potential indefiniteness of the means-plus-function terms or determine that these
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`17
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`claims are indefinite and it is logically impossible for the Board to resolve the prior art
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`challenge. Intel, 21 F.4th at 813-14. Either way, the Board should not find that
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`Petitioner has failed to show unpatentability of claims 16 and 17.
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`1.
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`The Board should find claims 16-17 unpatentable.
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`In the IPR2018-01335 Petition, Petitioner presented the same constructions for
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`the “means for processing …” and “means for scatter loading …” terms of claims 16-
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`17 that Patent Owner had previously advanced in a separate ITC proceeding. Ex. 1008
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`(joint claim construction chart) at 4-6. Namely, the only purported structure identified
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`in the specification that relates to these terms is “a modem processor coupled to a
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`system memory.” IPR2018-01335 Petition (Paper 3) at 19-22; see also POR (Paper
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`16) at 18-21. Patent Owner did not present any other corresponding structure. If the
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`Board accepts this structure, it should find claims 16-17 unpatentable.
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`Petitioner has presented in detail how the prior art of record renders obvious
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`claims 16-17 under these constructions. See IPR2018-01335 Petition (Paper 3) at
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`Sections X.B.2.c, X.B.2.e, X.B.3. The only distinctions offered in the Patent Owner
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`Response have already been addressed and rejected by the Board in its Final Written
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`Decision. See FWD (Paper 30) at 26-50; 52. Therefore, if the Board finds that the
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`identified structures are sufficient, it should find these claims unpatentable.
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`Even if the Board finds that the identified structures are not sufficient, it should
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`find claims 16-17 unpatentable as obvious in view of the prior art combination set forth
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`18
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`in the Petition. As the Federal Circuit made clear, “[t]he indefiniteness of a limitation
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`IPR2018-013