FIFO Architecture, Functions,
`and Applications
`
`SCAA042A
`November 1999
`
` 1
`
`QUALCOMM EXHIBIT 2013
`Intel v. Qualcomm
`IPR2018-01334
`
`

`

`IMPORTANT NOTICE
`
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`
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`time of sale in accordance with TI’s standard warranty. Testing and other quality control
`techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing
`of all parameters of each device is not necessarily performed, except those mandated by
`government requirements.
`
`INVOLVE
`CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY
`POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR
`ENVIRONMENTAL DAMAGE
`(“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR
`PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
`USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
`INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY
`AT THE CUSTOMER’S RISK.
`
`In order to minimize risks associated with the customer’s applications, adequate design and
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`
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`
`Copyright  1999, Texas Instruments Incorporated
`
` 2
`
`QUALCOMM EXHIBIT 2013
`Intel v. Qualcomm
`IPR2018-01334
`
`

`

`Contents
`Title
`
`Page
`
`Abstract
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`Introduction
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`FIFO Types
`Exclusive Read/Write FIFOs
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Concurrent Read/Write FIFOs
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Metastability of Synchronizing Circuits
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Asynchronous FIFOs
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Synchronous FIFOs
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`1
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`1
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`6
`9
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`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`FIFO Architectures
`Fall-Through FIFOs
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Architecture
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Advantages and Drawbacks
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`FIFOs With Static Memory
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Architecture
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Advantages and Drawbacks
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`FIFOs From TI
`Features
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Data Outputs With Latches
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Synchronization of Flags
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Edges of Outputs
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Extending Word Width
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Extending Memory Depth
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Application Examples
`Asynchronous Operation of Exclusive Read/Write FIFOs
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Connection of Peripherals to Processors
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Block Transfer of Data
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Programmable Delay
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Collecting Data Before an Event
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Collecting Data Before and After an Event
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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`11
`11
`11
`13
`13
`13
`14
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`14
`14
`14
`15
`16
`16
`17
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`18
`18
`20
`23
`24
`24
`26
`
`Summary
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`29
`
`Acknowledgment
`
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`
`29
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`iii
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`QUALCOMM EXHIBIT 2013
`Intel v. Qualcomm
`IPR2018-01334
`
`

`

`Figure
`1
`2
`3
`4
`5
`6
`7
`
`List of Illustrations
`Page
`Title
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`2
`First-In First-Out Data Flow
`3
`Synchronization of External Signal
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Timing Diagram for the Metastable State
`4
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Block Diagram of Two-Level Synchronization
`4
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Timing Diagram for Two-Level Synchronization
`5
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`Signals of FIFO With Single-Level Synchronization (Recorded for 15 Hours Under Worst-Case Conditions)
`5
`. . . .
`Signals of TI SN74ACT7807 FIFO With Three-Level Synchronization
`(Recorded for 15 Hours Under Worst-Case Conditions)
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`6
`Connections of an Asynchronous FIFO
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`8
`6
`Timing Diagram for Asynchronous FIFO of Length 4
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`9
`7
`10 Asynchronism When Resetting FULL Signal
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`8
`11 Connections of a Synchronous FIFO
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`9
`12
`Timing Diagram for a Synchronous FIFO of Length 4
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`10
`13 Circuitry of 4 × 5 Fall-Through FIFO
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`11
`Timing Diagram of 4 × 5 Fall-Through FIFO in Figure 13
`14
`12
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`15 Circular FIFO With Two Pointers
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`13
`16 Block Diagram of FIFO With Static Memory
`14
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`17 Waveforms on FIFO Outputs
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`14
`18
`Signals in Synchronous FIFO SN74ACT7881 With Multilevel Synchronization of Status Outputs
`15
`. . . . . . . . . . . .
`19
`Extending Word Width of Asynchronous FIFOs
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`16
`20
`Extending Word Width of Synchronous FIFOs
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`17
`21
`Extending Memory Depth of Synchronous FIFOs
`17
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`22
`Timing Conditions for WRITE CLOCK and READ CLOCK
`18
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`23
`Synchronizing Circuit for Generating WRITE CLOCK and READ CLOCK Signals
`18
`. . . . . . . . . . . . . . . . . . . . . . .
`24
`Timing of Signals in Synchronizing Circuit
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`19
`25 Connection of Unidirectional Peripheral With the SN74ACT7881 FIFO
`20
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`26 Connection of Bidirectional Peripheral With the SN74ACT2235 FIFO
`21
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`27 Connection of Bidirectional Peripheral With DMA and SN74ACT2235 FIFO
`22
`. . . . . . . . . . . . . . . . . . . . . . . . . . . .
`28 Video Signal With Picture Information and Porch
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`22
`29 Digitizing and Compressing a Video Signal With the TMS320C30 Signal Processor
`23
`. . . . . . . . . . . . . . . . . . . . . . .
`30 Block Transfer of Data With Synchronous SN74ACT7881 FIFO
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`23
`31
`Programmable Digital Delay With the SN74ACT7881
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`24
`32
`Timing of Signals in Programmable Digital Delay With the SN74ACT7881
`24
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`33 Collecting Data Before an Event With the SN74ACT7881
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`25
`34
`Timing of Device Shown in Figure 33
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`25
`35 Collecting Data Before and After an Event With the SN74ACT7881
`26
`. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
`36
`Timing of Signals in the SN74ACT7881 During Initialization and Start of Data Capture
`27
`. . . . . . . . . . . . . . . . . . .
`37
`Timing of Signals in the SN74ACT7881 at End of Data Capture and Start of Readout
`. . . . . . . . . . . . . . . . . . . . .
`28
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`QUALCOMM EXHIBIT 2013
`Intel v. Qualcomm
`IPR2018-01334
`
`

`

`Abstract
`
`First-in first-out memories (FIFOs) have progressed from fairly simple logic functions to high-speed buffers incorporating
`large blocks of SRAM. This application report takes a detailed look at the evolution of FIFO device functionality and at the
`architecture and applications of FIFO devices from Texas Instruments (TI). The first part presents the different functions
`of FIFOs and the resulting types that are found. The second part deals with current FIFO architectures and the different ways
`in which they work. Finally, some application examples are given to illustrate the use of FIFOs from the TI product spectrum.
`
`Introduction
`
`In every item of digital equipment there is exchange of data between printed circuit boards (PCBs). Intermediate storage or
`buffering always is necessary when data arrive at the receiving PCB at a high rate or in batches, but are processed slowly or
`irregularly.
`
`Buffers of this kind also can be observed in everyday life (for example, a queue of customers at the checkout point in a
`supermarket or cars backed up at traffic lights). The checkout point in a supermarket works slowly and constantly, while the
`number of customers coming to it is very irregular. If many customers want to pay at the same time, a queue forms, which works
`by the principle of first come, first served. The backup at traffic lights is caused by the sporadic arrival of the cars, the traffic
`lights allowing them to pass through only in batches.
`
`In electronic systems, buffers of this kind also are advisable for interfaces between components that work at different speeds
`or irregularly. Otherwise, the slowest component determines the operating speed of all other components involved in data
`transfer.
`
`In a compact-disk player, for instance, the speed of rotation of the disk determines the data rate. To make the reproduced sound
`fluctuations independent of the speed, the data rate of the A/D converter is controlled by a quartz crystal. The different data
`rates are compensated by buffering. In this way, the sound fluctuations are largely independent of the speed at which disks
`rotate.
`
`A FIFO is a special type of buffer. The name FIFO stands for first in first out and means that the data written into the buffer
`first comes out of it first. There are other kinds of buffers like the LIFO (last in first out), often called a stack memory, and the
`shared memory. The choice of a buffer architecture depends on the application to be solved.
`
`FIFOs can be implemented with software or hardware. The choice between a software and a hardware solution depends on
`the application and the features desired. When requirements change, a software FIFO easily can be adapted to them by
`modifying its program, while a hardware FIFO may demand a new board layout. Software is more flexible than hardware. The
`advantage of the hardware FIFOs shows in their speed. A data rate of 3.6 gigabits per second is specified for a Texas Instruments
`(TI) SN74ABT7819 FIFO.
`This application report takes a detailed look at TI FIFO devices. The first part presents the different functions of FIFOs and
`the resulting types that are found. The second part deals with current FIFO architectures and the different ways in which they
`work. Finally, some application examples are given to illustrate the use of FIFOs available from TI.
`
`TI is a trademark of Texas Instruments Incorporated.
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`
`
`FIFO Types
`
`Every memory in which the data word that is written in first also comes out first when the memory is read is a first-in first-out
`memory. Figure 1 illustrates the data flow in a FIFO. There are three kinds of FIFO:
`•
`
`Shift register – FIFO with an invariable number of stored data words and, thus, the necessary synchronism between
`the read and the write operations because a data word must be read every time one is written
`•
`Exclusive read/write FIFO – FIFO with a variable number of stored data words and, because of the internal structure,
`the necessary synchronism between the read and the write operations
`• Concurrent read/write FIFO – FIFO with a variable number of stored data words and possible asynchronism
`between the read and the write operation
`
`Input Data
`
`Data Storage
`
`Data Storage
`
`Data Storage
`
`Data Storage
`
`Data Storage
`
`Data Storage
`
`Output Data
`
`Figure 1. First-In First-Out Data Flow
`
`The shift register is not usually referred to as a FIFO, although it is first-in first-out in nature. Consequently, this application
`report focuses exclusively on FIFOs that handle variable-length data.
`
`Two electronic systems always are connected to the input and output of a FIFO: one that writes and one that reads. If certain
`timing conditions must be maintained between the writing and the reading systems, we speak of exclusive read/write FIFOs
`because the two systems must be synchronized. But, if there are no timing restrictions in how the systems are driven, meaning
`that the writing system and the reading system can work out of synchronism, the FIFO is called concurrent read/write. The
`first FIFO designs to appear on the market were exclusive read/write because these were easier to implement. Nearly all present
`FIFOs are concurrent read/write because so many applications call for concurrent read/write versions. Concurrent read/write
`FIFOs can be used in synchronous systems without any difficulty.
`
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`Exclusive Read/Write FIFOs
`In exclusive read/write FIFOs, the writing of data is not independent of how the data are read. There are timing relationships
`between the write clock and the read clock. For instance, overlapping of the read and the write clocks could be prohibited. To
`permit use of such FIFOs between two systems that work asynchronously to one another, an external circuit is required for
`synchronization. But this synchronization circuit usually considerably reduces the data rate.
`
`Concurrent Read/Write FIFOs
`In concurrent read/write FIFOs, there is no dependence between the writing and reading of data. Simultaneous writing and
`reading are possible in overlapping fashion or successively. This means that two systems with different frequencies can be
`connected to the FIFO. The designer need not worry about synchronizing the two systems because this is taken care of in the
`FIFO. Concurrent read/write FIFOs, depending on the control signals for writing and reading, fall into two groups:
`•
`Synchronous FIFOs
`• Asynchronous FIFOs
`
`Metastability of Synchronizing Circuits
`In digital engineering, there is the constantly recurring problem of synchronizing two systems that work at different
`frequencies. Concurrent read/write FIFOs can also handle the data exchange between two systems of different frequencies,
`so internal synchronizing circuits are called for. This section is a brief introduction to the problems that are involved in
`synchronization.
`
`The problem of synchronizing an external signal with a local clock generator normally is solved by using a flip-flop (see
`Figure 2), but this means violating the setup and hold times stated in the data sheets for the devices. As a result, the flip-flop
`can go into a metastable state.
`
`Digital System
`
`Local
`Clock
`
`Asynchronous
`Signal
`
`D Q
`
`Synchronized
`Signal
`
`Figure 2. Synchronization of External Signal
`
`With a D-type flip-flop, the setup or hold times must be maintained. This means that for a short time before the clock edge (setup
`time) and for a short time afterward (hold time) the level on the D input must not change to ensure that the function of the
`flip-flop is executed correctly. If these conditions are not maintained, the flip-flop can become metastable. In an RS flip-flop,
`metastable states are possible if the reset and set inputs change from the active to the inactive state at the same time. In both
`cases, the flip-flop adopts an undefined and unstable, or metastable, state (see Figure 3). No defined state can be ensured on
`the Q outputs. After a time, the flip-flop goes into one of the two stable states, but it is impossible to predict which.
`
`3
`
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`Intel v. Qualcomm
`IPR2018-01334
`
`

`

`
`
`Data
`
`tsu
`
`Clock
`
`Q Output
`
`tpd max
`
`th
`
`tsu
`
`th
`
`Metastable Region
`
`Metastable Region
`
`Metastable
`Response
`
`tpd max
`
`Metastable
`Response
`
`Figure 3. Timing Diagram for the Metastable State
`
`–3 V
`
`0 V
`
`3 V
`
`–0 V
`
`3 V
`2 V
`0.8 V
`0 V
`
`These operating conditions for flip-flops can be maintained easily in synchronous circuits. But, with asynchronous circuits and
`in synchronizing circuits, violations of the operating conditions for D and RS flip-flops are unavoidable. Concurrent read/write
`FIFOs that are driven by two systems working asynchronously to one another must perform internal synchronization of the
`asynchronous external signals.
`
`For physical reasons, there are no ideal flip-flops with a setup and hold time of zero, so there can be no synchronizing circuit
`that works faultlessly. The quality of a synchronizing circuit is indicated by its mean time between failures (MTBF). This is
`calculated from the frequency of the asynchronous signal (fin), the clock frequency of the synchronizing circuit (fclk), and the
`length of the critical time window (td).
`1
`fin fclk td
`For fclk = 1 MHz, fin of 1 kHz, and td = 30 ps:
`1
`1 kHz 1 MHz 30 ps + 33.3 s
`If a flip-flop is used to synchronize two signals, you can no longer expect the maximum delays stated in the data sheets.
`Therefore, for reliable operation of a system, you must know how long it is necessary to wait after the clock pulse until data
`can be evaluated.
`
`(1)
`
`(2)
`
`MTBF +
`
`MTBF +
`
`MTBF can be improved appreciably by multilevel synchronization. Figure 4 illustrates a two-level synchronizing circuit, and
`the timing of the signals is shown in Figure 5. The second flip-flop can only go into a metastable state if the first flip-flop is
`already metastable. This metastability can considerably increase the delay of the first flip-flop. But if the period of the clock
`signal is longer than the sum of the increased delay plus the setup time of the second flip-flop, the second flip-flop can never
`go into a metastable state.
`
`Digital System
`
`Local
`Clock
`
`Asynchronous
`Signal
`
`D Q
`
`D Q
`
`Synchronized
`Signal
`
`Figure 4. Block Diagram of Two-Level Synchronization
`
`4
`
`QUALCOMM EXHIBIT 2013
`Intel v. Qualcomm
`IPR2018-01334
`
`

`

`Data
`
`tsu
`
`Clock
`
`th
`
`tsu
`
`th
`
`Metastable Region
`
`tpd max
`
`tpd max
`
`Metastable
`Response
`
`First Flip-Flop
`Q Output
`
`Second Flip-Flop
`Q Output
`
`–3 V
`
`–0 V
`
`3 V
`
`0 V
`
`3 V
`2 V
`0.8 V
`0 V
`
`3 V
`
`–0 V
`
`Figure 5. Timing Diagram for Two-Level Synchronization
`
`To measure metastability, conventional concurrent read/write FIFOs were operated in the metastable region, and the READ
`CLOCK input signal and EMPTY output signal were recorded for a period of 15 hours using a storage oscilloscope.
`
`The signal patterns for single-level synchronization are shown in Figure 6. It is easy to see that the synchronizing flip-flop
`sometimes decides for a 1 level and sometimes for a 0 level on the first clock edge. In some cases, the decision is obviously
`difficult for the flip-flop because it takes much more time than normal. After the second clock edge, the output is stable again
`in every case.
`
`READ CLOCK
`
`1 V/div
`
`EMPTY
`
`345.100 ns
`
`370.100 ns
`5 ns/div
`
`395.100 ns
`
`Figure 6. Signals of FIFO With Single-Level Synchronization
`(Recorded for 15 Hours Under Worst-Case Conditions)
`
`5
`
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`Intel v. Qualcomm
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`
`

`

`The measurement illustrated in Figure 7 was performed on a TI SN74ACT7807 FIFO. This FIFO features three-level
`synchronization. Here too, the decision for a high level on the EMPTY output sometimes comes one clock cycle later, but the
`metastable response, with the much longer time to decide, can no longer be observed.
`
`
`
`READ CLOCK
`
`1 V/div
`
`EMPTY
`
`150.720 ns
`
`165.720 ns
`3 ns/div
`
`180.720 ns
`
`Figure 7. Signals of TI SN74ACT7807 FIFO With Three-Level Synchronization
`(Recorded for 15 Hours Under Worst-Case Conditions)
`
`Asynchronous FIFOs
`The control signals of an asynchronous FIFO correspond most closely to human intuition and were, in the past, the only kind
`of FIFO driving. The block diagram in Figure 8 shows the control lines of an asynchronous FIFO, and Figure 9 illustrates the
`typical timing on these lines in a read and write operation.
`
`FULL
`
`WRITE CLOCK
`
`INPUT DATA
`
`EMPTY
`
`READ CLOCK
`
`OUTPUT DATA
`
`Asynchronous
`FIFO
`
`CLEAR
`
`Figure 8. Connections of an Asynchronous FIFO
`
`6
`
`QUALCOMM EXHIBIT 2013
`Intel v. Qualcomm
`IPR2018-01334
`
`

`

`CLEAR
`
`FULL
`
`ÏÏ
`ÏÏ
`
`WRITE
`CLOCK
`
`INPUT
`DATA
`
`EMPTY
`
`READ
`CLOCK
`
`OUTPUT
`DATA
`
`ÎÎ
`ÎÎ
`ÎÎ
`
`D1
`
`D2
`
`D3
`
`D4
`
`D5
`
`D1
`
`D2
`
`D3
`
`D4
`
`D5
`
`Reset
`FIFO
`
`D1–D3
`Write
`
`D1
`Read
`
`D4–D5
`Write
`
`D2–D5
`Read
`
`Figure 9. Timing Diagram for Asynchronous FIFO of Length 4
`
`The control lines WRITE CLOCK and FULL are used to write data. When a data word is to be written into an asynchronous
`FIFO, it is first necessary to check whether there is space available in the FIFO. This is done by querying the FULL status line.
`If free space is indicated, the data word is applied to the data inputs and written into the FIFO by a clock edge on the WRITE
`CLOCK input.
`
`In analogous fashion, the control lines READ CLOCK and EMPTY are used to read data. In this case, the EMPTY status output
`has to be queried before reading, because data can be read out only if it is stored in the FIFO. Then, a clock edge is applied
`to the READ CLOCK input, causing the first word in the data queue to appear on the data output.
`
`The timing diagram in Figure 9 shows the resetting of the FIFO that is always necessary at the beginning. Then, three data words
`are written in. The data words D1 through D3 appear one after the other on the INPUT DATA inputs and clock edges are applied
`to WRITE CLOCK for transfer of the data. Once the first data word has been written into the FIFO, the EMPTY signal changes
`from low level to high level. Another two data words are written into the FIFO before the first read cycle. The subsequent
`reading out of the first data word with the aid of a clock edge on READ CLOCK does not alter the status signals. With the
`writing of another two data words, the FIFO is full. This is indicated by the FULL signal. Finally, the four data words D2
`through D5 remaining in the FIFO are read out. Thus, the FIFO is empty again, so the EMPTY status line shows this by low
`level.
`
`The disadvantage of a FIFO of this kind is that the status signals cannot be fully synchronized with the read and write clock.
`An example of this is shown in Figure 10.
`
`7
`
`QUALCOMM EXHIBIT 2013
`Intel v. Qualcomm
`IPR2018-01334
`
`

`

`
`
`Writing System
`
`Reading System
`
`Clock
`
`FIFO
`
`DQ
`
`FULL
`
`EMPTY
`
`WRCLK RDCLK
`
`Clock
`
`WRCLK
`
`D–FF CLK
`
`FULL/D
`
`RDCLK
`
`Figure 10. Asynchronism When Resetting FULL Signal
`
`tsu + th
`of D–FF is Violated
`
`If there is space in the FIFO for only one data word, the next write cycle sets the FULL signal. Then, the writing system queries
`the FULL signal with the aid of its D flip-flop and waits until there is again space in the FIFO. When a data word is read, READ
`CLOCK resets the FULL status line. This reset is synchronous with the reading system but asynchronous to the writing system.
`In the worst case, the setup or hold time of the flip-flop in the writing system is violated. This flip-flop goes into a metastable
`state, the results of which were discussed previously.
`
`The problem described above also occurs with the EMPTY status signal. EMPTY should be synchronous with the reading
`system, but it is reset by the writing system. So, the resetting of EMPTY is inevitably asynchronous to the reading system.
`
`This asynchronism is a result of the system, and synchronization is not possible within the asynchronous FIFO. If
`synchronization becomes necessary, the designer must provide it externally. Nevertheless, there are wide-ranging application
`possibilities for asynchronous FIFOs.
`
`8
`
`QUALCOMM EXHIBIT 2013
`Intel v. Qualcomm
`IPR2018-01334
`
`

`

`Synchronous FIFOs
`Synchronous FIFOs are controlled based on methods of control proven in processor systems. Every digital processor system
`works synchronized with a system-wide clock signal. This system timing continues to run even if no actions are being executed.
`Enable signals, also often called chip-select signals, start the synchronous execution of write and read operations in the various
`devices, such as memories and ports.
`
`The block diagram in Figure 11 shows all the signal lines of a synchronous FIFO. It requires a free-running clock from the
`writing system and another from the reading system. Writing is controlled by the WRITE ENABLE input synchronous with
`WRITE CLOCK. The FULL status line can be synchronized entirely with WRITE CLOCK by the free-running clock. In an
`analogous manner, data words are read out by a low level on the READ ENABLE input synchronous with READ CLOCK.
`Here, too, the free-running clock permits 100 percent synchronization of the EMPTY signal with READ CLOCK.
`
`Free-Running
`WRITE CLOCK
`
`WRITE ENABLE
`
`FULL
`
`INPUT DATA
`
`Free-Running
`READ CLOCK
`
`READ ENABLE
`
`EMPTY
`
`OUTPUT DATA
`
`Synchronous
`FIFO
`
`CLEAR
`
`Figure 11. Connections of a Synchronous FIFO
`
`Thus, synchronous FIFOs are integrated easily into common processor architectures, offering complete synchronism of the
`FULL and EMPTY status signals with the particular free-running clock.
`
`Figure 12 shows the typical waveform in a synchronous FIFO. WRITE CLOCK and READ CLOCK are free running. The
`writing of new data into the FIFO is initialized by a low level on the WRITE ENABLE line. The data are written into the FIFO
`with the next rising edge of WRITE CLOCK. In analogous fashion, the READ ENABLE line controls the reading out of data
`synchronous with READ CLOCK.
`
`All status lines within the FIFO can be synchronized by the two free-running-clock signals. The FULL line only changes its
`level synchronously with WRITE CLOCK, even if the change is produced by the reading of a data word. Likewise, the EMPTY
`signal is synchronized with READ CLOCK. A synchronous FIFO is the only concurrent read/write FIFO in which the status
`signals are synchronized with the driving logic.
`
`All TI synchronous FIFOs feature multilevel synchronization of the status lines as described previously.
`
`9
`
`QUALCOMM EXHIBIT 2013
`Intel v. Qualcomm
`IPR2018-01334
`
`

`

`
`
`D1
`
`D2
`
`D3
`
`D4
`
`D5
`
`CLEAR
`
`ÏÏ
`ÏÏ
`FULL
`ÏÏ
`WRITE
`CLOCK
`
`WRITE
`ENABLE
`
`INPUT
`DATA
`
`ÎÎ
`EMPTY
`ÎÎ
`
`READ
`CLOCK
`
`READ
`ENABLE
`
`OUTPUT
`DATA
`
`Reset
`FIFO
`
`D1–D3
`Write
`
`D1
`
`D1
`Read
`
`D2
`
`D3
`
`D4
`
`D5
`
`D4–D5
`Write
`
`D2–D5
`Read
`
`Figure 12. Timing Diagram for a Synchronous FIFO of Length 4
`
`10
`
`QUALCOMM EXHIBIT 2013
`Intel v. Qualcomm
`IPR2018-01334
`
`

`

`FIFO Architectures
`
`All the kinds of FIFOs described in FIFO Types can be implemented in different hardware architectures. The architecture of
`conventional FIFOs has constantly been developed. Initially, FIFOs worked by the fall-through principle. Today, FIFOs are
`nearly always based on an SRAM, which produced a considerable increase in the number of data words stored, despite the faster
`speed. All possible hardware architectures also are found in software FIFOs.
`
`Fall-Through FIFOs
`Fall-through FIFOs were the first FIFO generation. The customers queuing at the checkout point of a supermarket could easily
`have been the mod