`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`www.uspto.gov
`
`APPLICATION NO.
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`
`
`
` FILING DATE
`
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`FIRST NAMED INVENTOR
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`ATTORNEY DOCKET NO.
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`
`
`
`CONFIRMATIONNO.
`
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`13/052,516
`
`03/21/2011
`
`Nitin Gupta
`
`101459
`
`6620
`
`23696
`7590
`07/19/2013
`QUALCOMM INCORPORATED
`5775 MOREHOUSEDR.
`SAN DIEGO,CA 92121
`
`EXAMINER
`ELAMIN, ABDELMONIEMI
`
`ART UNIT
`
`2116
`
`PAPER NUMBER
`
`
`
`NOTIFICATION DATE
`
`
`DELIVERY MODE
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`07/19/2013
`
`ELECTRONIC
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`The time period for reply, if any, is set in the attached communication.
`
`Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
`following e-mail address(es):
`us-docketing @qualcomm.com
`
`PTOL-90A (Rev. 04/07)
`
`INTEL 1004
`
`INTEL 1004
`
`

`

`
`Application No.
`Applicant(s)
`13/052,516
`GUPTA ET AL.
`
`Examiner
`Art Unit
`AIA (First Inventor to File)
`ABDELMONIEM ELAMIN
`2116 o
`
`-- The MAILING DATEof this communication appears on the cover sheet with the correspondence address--
`Period for Reply
`
`Office Action Summary
`
`A SHORTENED STATUTORY PERIOD FOR REPLYIS SET TO EXPIRE 3MONTH(S) OR THIRTY(30) DAYS,
`WHICHEVER IS LONGER, FROM THE MAILING DATE OF THIS COMMUNICATION.
`Extensions of time may be available under the provisions of 37 CFR 1.136(a).
`In no event, however, may a reply be timely filed
`after SIX (6) MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, evenif timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1.704(b).
`
`-
`-
`
`
`
`Status
`1) Responsive to communication(s) filed on27March2011.
`L] A declaration(s)/affidavit(s) under 37 CFR 1.130(b) was/were filedon___..
`2a)L] This action is FINAL.
`2b)X] This action is non-final.
`3)L] An election was made bythe applicant in responseto a restriction requirementset forth during the interview on
`
`; the restriction requirement and election have been incorporatedinto this action.
`4)L] Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordancewith the practice under Ex parte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`Disposition of Claims
`5)K] Claim(s) 1-24 is/are pending in the application.
`
`5a) Of the above claim(s)
`is/are withdrawn from consideration.
`
`6)L] Claim(s)
`is/are allowed.
`7) Claim(s) 1-24 is/are rejected.
`8)L] Claim(s)__ is/are objectedto.
`
`9)L] Claim(s)
`are subject to restriction and/or election requirement.
`* If any claims have been determined allowable, you may be eligible to benefit from the Patent Prosecution Highway program at a
`participating intellectual property office for the corresponding application. For more information, please see
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`nite://Awww.usoto.dov/patenis/init events/pph/index.isp
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`or send an inquiry to PPHieedback@uspte.dov.
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`Application Papers
`10) The specification is objected to by the Examiner.
`
`11) The drawing(s) filed on
`is/are: a)[_] accepted or b)[_] objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).
`
`Priority under 35 U.S.C. § 119
`12)L] Acknowledgmentis made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`Certified copies:
`a)LJ All
`b)L) Some* c)L] None of the:
`1.) Certified copies of the priority documents have been received.
`2.L] Certified copies of the priority documents have been received in Application No.
`3.0] Copies of the certified copies of the priority documents have been receivedin this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`3) TC Interview Summary (PTO-413)
`1) X Notice of References Cited (PTO-892)
`Paper No(s)/Mail Date.
`:
`:
`4 O Other:
`—_
`2) X Information Disclosure Statement(s) (PTO/SB/08)
`ther:
`Paper No(s)/Mail Date 09/17/2012: 05/30/2013.
`)
`
`U.S. Patent and Trademark Office
`PTOL-326 (Rev. 05-13)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 20130715
`
`

`

`Application/Control Number: 13/052,516
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`Art Unit: 2116
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`Page 2
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`DETAILED ACTION
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`Claim Rejections - 35 USC § 102
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`1,
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`The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that
`
`form the basis for the rejections under this section madein this Office action:
`
`A personshall be entitled to a patent unless —
`(b) the invention was patented or described in a printed publication in this or a foreign country or in
`public use or on sale in this country, more than one year prior to the date of application for patentin the
`United States.
`Claims 1-24 are rejected under pre-AIA 35 U.S.C. 102(b) as being anticipated by
`
`2.
`
`Svensson,International Publication No. WO 2006/077068 A2 (cited by Applicant).
`
`3.
`
`Claims 1, 3, 7-8, 19, 21, Svensson teaches a secondary processor [client processor 104]
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`comprising system memory [DSPXRAM 1/10] and a hardware buffer [An intermediate storage
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`area is defined within the memory 108] for receiving at a least a portion of an executable
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`software
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`image [this reserved block of memory is used for intermediate storage of information (code
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`and/or data) to be transferred to the slave- private memory, see page 7, lines 5-8. On receipt of
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`the slave's information,
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`the second stage of the host boot loaderfills the intermediate storage
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`area with information (code and/or data) to be loaded into the slave's invisible memory (Step
`
`216) page7,
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`lines25-27],
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`the secondary processor comprising a scatter loader controller for
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`loading the executable software image directly from the hardware buffer to the system memory
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`[The slave copies the contents of the intermediate storage area to appropriate locations in its
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`slave-private memory (Step 220), thereby implementing its actual loading, see page 7, last line -
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`page &, line 2];
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`a primary processor [host processor102] coupled with a memory [non-volatile memory
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`106],
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`the memory storing the executable software image for the secondary processor [This
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`

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`Application/Control Number: 13/052,516
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`Art Unit: 2116
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`Page 3
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`can be
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`inferred from The first stage resets and holds
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`the slave 104 in the
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`reset
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`state (Step 202) and pushes information (program instructions and/or data) (Step 204) in the
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`usual way from the non-volatile memory 106 into the commonly visible memories 108, see page
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`5, lines 23-26]; and
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`an interface communicatively coupling the primary processor and the secondary
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`processor via which the executable software image is received by the secondary processor [The
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`arrows in FIG. 1 indicate access paths, e.g., busses and DMA paths, between the CPUs and the
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`memories. The ARM host CPU 102 can access the non-volatile memory 106 and the SARAM and
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`DARAM 108 of the DSP, but not the DSP's XRAM 110, and the DSP slave CPU 104 can
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`access all of the RAMs 108, 110, see page 5, lines 8-12].
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`4,
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`Claim 2, Svensson teaches the scatter loader controller is configured to load the
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`executable software image directly from the hardware buffer to the system memory of the
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`secondary processor without copying data between system memorylocations on the secondary
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`processor [there is no indication that data is copied between system memory locations on the
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`secondary processor when loading the executable software image from the hardware buffer to
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`the system memory of the secondary processor].
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`5.
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`Claims 4-6, Svensson teaches the executable software image comprises an image header
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`and at least one data segment[Fig. 3, it is clear that the executable software image comprises an
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`image header and at least one segment].
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`6.
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`Claim 9, Svensson teaches the portion of the executable software image is loaded into the
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`system memory of the secondms, processor without an entire executable software image being
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`stored in the hardware buffer [This also means that a block should besplit if it is larger than the
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`

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`Application/Control Number: 13/052,516
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`Art Unit: 2116
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`Page 4
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`remaining part of the intermediate storage area, and one part transferred to the intermediate
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`storage area with the remaining part transferred in the next block. Moreover, if a block is
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`several times larger than the intermediate storage area, it may have to be split more than once,
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`see page &, line 27]
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`vs
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`Claims 10, 20, 22, Svensson teaches the multi-processor system is integrated into a
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`computer
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`[This
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`invention relates to initialization of electronic systems having multiple
`
`programmable processors, see page 1, line 4].
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`8.
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`Claims 11, 14-15, 17, 23, Svensson teaches receiving at a secondary processor [client
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`processor 104], from a primary processor [host processor 102] via an inter- chip communication
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`bus [The arrows in FIG. 1 indicate access paths, e.g., busses and DMA paths, between the CPUs
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`and the memories. The ARM host CPU 102 can access the non-volatile memory 106 and the
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`SARAM and DARAM 108 of the DSP, but not the DSP's XRAM 110, and the DSP. slave
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`CPU 104 can access all of the RAMs 108, 110, see page 5, lines 8-12], an image header for an
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`executable software image for the secondary processor that is stored in memory coupled to the
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`primary processor, the executable software image comprising the image headerandat least one
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`data segment
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`[A block of code and/or data to be transferred into the intermediate storage
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`area includes a header);
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`processing, by the secondary processor,
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`the image header to determine at least one
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`location within system memory to which the secondary processor is coupled to store the at least
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`one data segment[that indicates the length of the block and whereit is to be loaded in the slave
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`memory, i.e., the destination address, see page 8, lines 15-18];
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`

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`Application/Control Number: 13/052,516
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`Art Unit: 2116
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`Page 5
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`receiving at
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`the secondary processor, from the primary processor via the inter-chip
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`communication bus, the at least one data segment [The first stage resets and holds the slave 104
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`in the reset state (Step 202) and pushes information (program instructions and/or data) (Step
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`204) in the usual way from the non-volatile memory 106 into the commonly visible memories
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`108, see page 5, lines 23-26]; and
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`loading, by the secondary processor,
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`the at
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`least one data segment directly to the
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`determined at least one location within the system memory [The slave copies the contents of the
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`intermediate storage area to appropriate locations in its slave-private memory (Step 220),
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`thereby implementing its actual loading, see page 7, last line- page 8, line 2].
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`9.
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`Claim 12, Svensson teaches booting the secondary processor using the executable
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`software image [The information pushed into these memories is mainly the boot loader, the OS,
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`and any necessary start-up code for the OS ... When this "push"is finished (Step 206), the slave
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`104 is allowed to boot (Step 208) and to start up the OS, see page§, line].
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`10.
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`Claim 13, Svensson teaches the scatter loader controller is configured to load the
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`executable software image directly from the hardware buffer to the system memory of the
`
`secondary processor without copying data between system memorylocations on the secondary
`
`processor [there is no indication that data is copied between system memory locations on the
`
`secondary processor when loading the executable software image from the hardware buffer to
`
`the system memory of the secondary processor].
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`11.
`
`Claims 16, 18, 24, Svensson teaches the multi-processor system is integrated into a
`
`computer
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`[This
`
`invention relates to initialization of electronic systems having multiple
`
`programmable processors, see page 1, line 4].
`
`

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`Application/Control Number: 13/052,516
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`Art Unit: 2116
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`Page 6
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`Conclusion
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`Any inquiry concerning this communication or earlier communications from the
`
`examiner should be directed to ABDELMONIEM ELAMIN whose telephone number is
`
`(571)272-3674. The examiner can normally be reached on MON - THUR 10:00 AM-6::00 PM.
`
`If attempts to reach the examiner by telephone are unsuccessful,
`
`the examiner’s
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`supervisor, Kim Huynh can be reached on 571-272-4147. The fax phone number for the
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`organization where this application or proceeding is assigned is 571-273-8300.
`
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`
`July 15, 2013
`
`/ABDELMONIEM ELAMIN/
`Primary Examiner, Art Unit 2116
`
`