`
`
`
`IPR2018-01334
`Petitioner’s Demonstrative Exhibits on Remand
`
`U.S. Patent No. 8,838,949
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`Intel Corporation
`Petitioner
`
`v.
`
`QUALCOMM INCORPORATED
`Patent Owner
`
`
`
`Trial No. IPR2018-013341
`U.S. Patent No. 8,838,949
`
`
`
`PETITIONER’S DEMONSTRATIVE EXHIBITS ON REMAND
`
`
`
`
`
`
`1 IPR2018-01335 and IPR2018-01336 have been consolidated with the instant
`proceeding.
`
`
`
`United States Patent and Trademark Office
`Before the Patent Trial and Appeal Board
`
`Intel Corporation, Petitioner,
`v.
`Qualcomm Incorporated, Patent Owner
`
`Case No: IPR2018-01334
`(Consolidated with IPR2018-01335, -01336)
`Petitioner’s Demonstrative Exhibits on Remand
`Inter Partes Review of U.S. Patent No. 8,838,949 on Remand
`August 4, 2022
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`1
`
`
`
`Overview
`
` Overview of the ʼ949 Patent
` Overview of the Prior Art
`
` Disputed Issues
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`2
`
`
`
`Overview
`
` Overview of the ʼ949 Patent
` Overview of the Prior Art
`
` Disputed Issues
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`3
`
`
`
`’949 Patent
`
`Pet. Op. Br. (Paper 35) at 2; -01334 Pet. at 9-15.
`
`Ex. 1001 (’949 Patent) at cover page, 9:42-56.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`4
`
`
`
`’949 Patent:
`Remaining Challenged Claims: 1-9, 12, and 16-17
`
` Claims 1-9 and 12
` Independent claim 1 is a system claim
` Claims 2-9 depend directly or indirectly on claim 1
` Claim 12 is a method claim that depends on independent claim 10
` Claim 12 requires a “hardware buffer”
`
` Claims 16-17
` Independent claim 16 is an apparatus claim that uses means-plus-
`function terms
` Claim 17 depends on claim 16
`
`Pet. Op. Br. (Paper 35) at 1; -01334 Pet.; -01335 Pet.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`5
`
`
`
`’949 Patent:
`Claim 1
`
`secondary processor
`system memory &
`hardware buffer
`image header and each data
`segment received separately
`
`Pet. Op. Br. (Paper 35) at 6, 8, 10; -01334 Pet.
`at 25-52.
`
`Ex. 1001 (’949 Patent) at Claim 1 (highlights and annotations added).
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`6
`
`
`
`’949 Patent:
`Claim 16
`
`means for processing
`
`means for scatter loading
`
`Pet. Op. Br. (Paper 35) at 1, 3-4; -01335
`Pet. at 17-22.
`
`Ex. 1001 (’949 Patent) at Claim 16 (highlights and annotations added).
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`7
`
`
`
`Overview
`
` Overview of the ʼ949 Patent
` Overview of the Prior Art
`
` Disputed Issues
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`8
`
`
`
`U.S. 7,356,680 (“Svensson”): Hardware Buffer &
`System Memory
`
`Memory
`
`Primary
`Processor
`
`Interface
`
`Secondary
`Processor
`
`Hardware
`Buffer
`
`Pet. Op. Br. (Paper 35) at 13-14; -01334 Pet. at 17-19, 25-27, 50-52.
`
`System Memory
`Ex. 1010 (Svensson) at cover, Fig. 1 (highlights and annotations added).
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`9
`
`
`
`U.S. 2006/0288019 (“Bauer”)
`
`Pet. Op. Br. (Paper 35) at 13-14; -01334 Pet. at 19-21.
`
`Ex. 1009 (Bauer) at cover, Fig. 2.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`10
`
`
`
`Bauer and Svensson:
`Same Multi-Processor System
`
`Ex. 1010 (Svensson) at Fig. 1.
`
`Ex. 1009 (Bauer) at Fig. 2.
`
`Pet. Op. Br. (Paper 35) at 13-14; -01334 Pet. at 19-21, 23-24.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`11
`
`
`
`Overview
`
` Overview of the ʼ949 Patent
` Overview of the Prior Art
` Disputed Issues
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`12
`
`
`
`Overview: Issues on Remand
`
`1. Claim construction for “hardware buffer.”
`
`2. Whether Bauer and Svensson disclose a “hardware buffer.”
`
`3. Whether the Board can resolve the prior art challenge to the
`patentability of claims 16 and 17 despite the potential
`indefiniteness of the means-plus function terms, along with
`whether these means-plus-function terms of claims 16 and 17
`are indefinite.
`
`Pet. Op. Br. (Paper 35) at 1.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`13
`
`
`
`Federal Circuit Guidance: “Hardware Buffer”
`
`“First, because every buffer in our (physical) world is ultimately
`implemented on a physical device (i.e., hardware), a ‘hardware buffer’ must
`mean something more than just a ‘buffer implemented in hardware,’ as
`Intel urges, or else the word “hardware” would be erased from the claims. …
`
`Second, because claim 1 requires both a ‘system memory’ and a ‘hardware
`buffer,’ there must be some distinction between those two concepts.
`
`Third, because claim 2 requires loading the executable software image
`‘directly from the hardware buffer to the system memory of the secondary
`processor without copying data between system memory locations on the
`secondary processor,’ the meaning of ‘hardware buffer’ relates to the ability
`to move the software image ‘directly’ to the second processor’s system
`memory and to avoid ‘copying data between system memory locations.’”
`
`Intel Corp. v. Qualcomm Inc., 21 F.4th 801, 809-10 (Fed. Cir. 2021) (emphases added).
`
`Pet. Op. Br. (Paper 35) at 5-7; Ex. 1026 (Lin Remand Decl.) at ¶¶ 11-12.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`14
`
`
`
`Proposed Constructions for “Hardware Buffer”
`
`Petitioner
`
`Construction
`
`“memory that is physically separate
`from the memory into which the
`software image is loaded for
`execution”
`
`Patent Owner
`
`“a permanent, dedicated buffer that is
`distinct from system memory”
`
`Pet. Op. Br. (Paper 35) at 5; Pet. Reply Br. (Paper 39) at 1-6; Ex. 1026 (Lin Remand Decl.) at ¶¶ 31-34.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`15
`
`
`
`Petitioner’s Construction of “Hardware Buffer”:
`Can Be Anywhere in the Secondary Processor
`
`
`
`‘949 specification and the term “hardware buffer”
`
`Ex. 1001 (‘949 patent) at 2:58-63 (highlights added).
`
`Ex. 1001 (‘949 patent) at 9:37-41 (highlights added).
`Pet. Op. Br. (Paper 35) at 7-8; Ex. 1026 (Lin Remand Decl.) at ¶¶ 14-15.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`16
`
`
`
`Petitioner’s Construction of “Hardware Buffer”:
`“System Memory”
`
`Ex. 1001 (‘949 patent) at 2:61-63, (highlights added).
`
`Ex. 1001 (‘949 patent) at 5:31-35.
`
`Pet. Op. Br. (Paper 35) at 7-8; Ex. 1026 (Lin Remand Decl.) at ¶16.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`17
`
`
`
`Petitioner’s Construction of “Hardware Buffer”:
`“System Memory”
`
`
`
`Experts agree that claimed “system memory” is memory where
`programs can be loaded and executed.
`
`Dr. Bill Lin (Petitioner’s expert)
`
`Q. Would you consider a memory that stores an operating system for execution by a
`processor to be a system memory?
`A. So a system memory would be a portion of the memory where programs could
`be loaded and executed . . . . .
`
`Dr. Martin Rinard (Patent Owner’s expert)
`
`Ex. 2001 (Lin Dep.) at 25:10-12.
`
`Q. Do you agree with Dr. Lin that system memory is memory where programs can be
`loaded and executed by a processor?
`A. That’s one of the things that system memory does, that you can do with system
`memory . . . .
`
`Pet. Op. Br. (Paper 35) at 8; Ex. 1026 (Lin Remand Decl.) at ¶ 16.
`
`Ex. 1022 (Rinard Dep.) at 61:9-14.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`18
`
`
`
`Petitioner’s Construction of “Hardware Buffer”:
`Differentiation between Claims 1 and 2
`
`Ex. 1001 (’949 Patent) at Claim 2 (highlights added).
`
`Ex. 1001 (’949 Patent) at Claim 1 (highlights added).
`
`Pet. Op. Br. (Paper 35) at 6-7; Ex. 1026 (Lin Remand Decl.) at ¶¶ 18-19.
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`19
`
`
`
`Petitioner’s Construction of “Hardware Buffer”:
`Can Be a Temporary Buffer
`
`Specification does not
`distinguish use of a
`temporary buffer per se,
`but instead:
` Transferring entire
`executable software
`image to a buffer
` Receipt of image
`header and data
`segment together
` Having “hardware
`buffer” in claimed
`“system memory”
`Pet. Op. Br. (Paper 35) at 9-11; Ex. 1026 (Lin Remand Decl.)
`at ¶¶ 21-29.
`
`Ex. 1001 (‘949 patent) at 7:60-63 (highlights added).
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`20
`
`
`
`Petitioner’s Construction of “Hardware Buffer”:
`’949 Figure 3
`
`Pet. Op. Br. (Paper 35) at 9.
`
`Ex. 1001 (’949 patent)
`at Fig. 3.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`21
`
`
`
`Petitioner’s Construction of “Hardware Buffer”:
`Can Be a Temporary Buffer
`Passages distinguishing transferring entire executable software image to a
`temporary buffer
`
`
`
`Ex. 1001 (’949 patent)
`at 9:37-41 (highlights
`added).
`
`Ex. 1001 (’949 patent)
`at 9:42-46 (highlights
`added).
`
`Ex. 1001 (’949 patent)
`at 9:46-54 (highlights
`added).
`
`Pet. Op. Br. (Paper 35) at 9-10; Ex. 1026 (Lin Remand Decl.) at ¶¶ 23-24.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`22
`
`
`
`Petitioner’s Construction of “Hardware Buffer”:
`Can Be a Temporary Buffer
`Passages distinguishing receipt of image header and data
`segment together
`
`
`
`Ex. 1001 (’949 patent) at 2:14-22 (highlights added).
`
`Ex. 1001 (’949 patent) at 2:25-28 (highlights added).
`
`Pet. Op. Br. (Paper 35) at 10; Ex. 1026 (Lin Remand Decl.) at ¶¶ 25-27.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`23
`
`
`
`Petitioner’s Construction of “Hardware Buffer”:
`Can Be a Temporary Buffer
`Passages distinguishing receipt of image header and data
`segment together (cont’d)
`
`
`
`Ex. 1001 (’949 patent) at 4:43-47 (highlights added).
`
`Ex. 1001 (’949 patent) at 4:47-52 (highlights added).
`Pet. Op. Br. (Paper 35) at 10-11; Ex. 1026 (Lin Remand Decl.) at ¶¶ 25-27.
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`24
`
`
`
`Petitioner’s Construction of “Hardware Buffer”:
`Can Be a Temporary Buffer
`
` One passage distinguishes only temporary buffers that reside in
`the same physical “system memory” as claimed
`
`Ex. 1001 (’949 patent) at 5:31-35 (highlights added).
`
`Pet. Op. Br. (Paper 35) at 11; Ex. 1026 (Lin Remand Decl.) at ¶ 28.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`25
`
`
`
`Petitioner’s Construction of “Hardware Buffer”:
`Can Be a Temporary Buffer
`
`Ex. 1001 (’949 patent) at 4:43-47 (highlights added).
`
`Ex. 1001 (’949 patent) at 9:46-54 (highlights added).
`
`Pet. Op. Br. (Paper 35) at 9, 11; Ex. 1026 (Lin Remand Decl.) at ¶ 29.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`26
`
`
`
`Petitioner’s Construction of “Hardware Buffer”:
`Prosecution History
`
` Rejection from Patent Office
`
`Ex. 1004 (7/19/13 Office Action) at 2
`(highlights added).
`
`Pet. Op. Br. (Paper 35) at 11-12; Ex. 1026 (Lin Remand Decl.) at ¶¶ 31-33.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`27
`
`
`
`Petitioner’s Construction of “Hardware Buffer”:
`Prosecution History
`
`
`
`Patent Owner’s amendment to claim 1 during prosecution
`
`Pet. Op. Br. (Paper 35) at 11-12; Ex. 1026 (Lin Remand Decl.) at ¶¶ 31-33.
`
`Ex. 1005 (10/17/13 Response) at 2
`(highlights added).
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`28
`
`
`
`Petitioner’s Construction of “Hardware Buffer”:
`Prosecution History
`Patent Owner’s argument during prosecution
`
`
`Pet. Op. Br. (Paper 35) at 12; Ex. 1026 (Lin Remand Decl.) at ¶¶ 31-33.
`
`Ex. 1005 (10/17/13 Response) at 8-9.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`29
`
`
`
`Proposed Constructions for “Hardware Buffer”
`
`Construction
`
`Petitioner
`
`“memory that is physically separate from the
`memory into which the software image is
`loaded for execution”
`
`Patent Owner “a permanent, dedicated buffer that is distinct
`from system memory”
`
`Pet. Op. Br. (Paper 35) at 5; Pet. Reply Br. (Paper 39) at 1-8; Ex. 1026 (Lin Remand Decl.) at ¶¶ 31-34.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`30
`
`
`
`Patent Owner’s Construction of “Hardware Buffer”:
`Zero Copy Is a Misnomer
`
`Pet. Reply Br. (Paper 39) at 3; Ex. 1027 (Lin Reply Decl.) at ¶¶ 13-14; PO Resp. Br. at 4-10.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`Ex. 1001 (‘949 Patent) at Claim 1
`(highlights and annotations added).
`
`31
`
`
`
`Patent Owner’s Construction of “Hardware Buffer”:
`Construction Is Unsupported by Specification
`
` Use of a “permanent, dedicated buffer” to aid alleged efficiency of
`scatter loading process is not mentioned in the specification
`
`Ex. 1001 (‘949 Patent) at 4:43-47.
`
`Ex. 1001 (‘949 Patent) at 7:20-26.
`
`Pet. Reply Br. (Paper 39) at 3; Ex. 1027 (Lin Reply Decl.) at ¶ 15; PO Resp. Br. at 6-7.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`32
`
`Ex. 1001 (‘949 Patent) at 11:17-24.
`
`
`
`Patent Owner’s Construction of “Hardware Buffer”:
`Construction Is Unnecessary for Alleged Advance
`
`Pet. Reply Br. (Paper 39) at 4; Ex. 1027 (Lin Reply Decl.) at ¶¶ 18-26.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`33
`
`Ex. 2014 (Hennessy and Patterson 4th Ed.) at 288.
`
`
`
`Overview: Issues on Remand
`
`1. Claim construction for “hardware buffer.”
`
`2. Whether Bauer and Svensson disclose a “hardware
`buffer.”
`
`3. Whether the Board can resolve the prior art challenge to the
`patentability of claims 16 and 17 despite the potential
`indefiniteness of the means-plus function terms, along with
`whether these means-plus-function terms of claims 16 and 17
`are indefinite.
`
`Pet. Op. Br. (Paper 35) at 1.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`34
`
`
`
`Disclosure of “Hardware Buffer”:
`ISA Is “Hardware Buffer” Under Either Construction
`
`Construction
`
`Petitioner
`
`“memory that is physically separate
`from the memory into which the
`software image is loaded for
`execution”
`
`Bauer and
`Svensson
`
`
`Patent Owner “a permanent, dedicated buffer that is
`distinct from system memory”
`
`
`
`Pet. Op. Br. (Paper 35) at 13-17; Pet. Reply Br. (Paper 39) at 6-8; Ex. 1026 (Lin Remand Decl.) at ¶¶ 31-34.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`35
`
`
`
`Disclosure of “Hardware Buffer”:
`Separate from Claimed System Memory
`
`
`
`Figure 1 of Svensson (and Figure 2 of Bauer) discloses an
`intermediate storage area separate from the DSP XRAM
`
`Hardware Buffer
`
`System Memory
`
`Ex. 1010 (Svensson) at Fig. 1
`(highlights and annotations added);
`see also Ex. 1009 (Bauer) at Fig. 2.
`
`Pet. Op. Br. (Paper 35) at 13-15; Ex. 1026 (Lin Remand Decl.) at ¶ 40.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`36
`
`
`
`Disclosure of “Hardware Buffer”:
`ISA Is Separate from Any System Memory
`
`Ex. 1010 (Svensson) at 5:21-28 (highlights added).
`
`Ex. 1010 (Svensson) at 8:29-32 (highlights added).
`
`Pet. Op. Br. (Paper 35) at 16; Ex. 1026 (Lin Remand Decl.) at ¶ 41.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`37
`
`
`
`Disclosure of “Hardware Buffer”:
`ISA Is Separate from Any System Memory
`
`
`
`The intermediate storage area of Bauer/Svensson is not a “system memory”
`because code is not executed from it
`
`Dr. Martin Rinard (Patent Owner’s Expert)
`
`Q. Am I right that in the client processor 104 does not execute code directly the
`intermediate storage area?
`It could in theory. But I believe in the system described in Svensson, it doesn’t.
`
`A.
`
`Ex. 1022 (Rinard Dep.) at 107:21-108:4 (emphasis added).
`
`Q. Do you agree with me that in Svensson the client processor 104 executes code
`from the XRAM 110?
`A. That's one of the places where it’s described as potentially being able to execute
`from, sure.
`
`Pet. Op. Br. (Paper 35) at 14-16; Ex. 1026 (Lin Remand Decl.) at ¶ 41.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`38
`
`Ex. 1022 (Rinard Dep.) at 108:21-109:4 (emphasis added).
`
`
`
`Disclosure of “Hardware Buffer”:
`ISA Is “Hardware Buffer” Under Either Construction
`
`Construction
`
`Petitioner
`
`“memory that is physically separate
`from the memory into which the
`software image is loaded for
`execution”
`
`Bauer and
`Svensson
`
`
`Patent Owner “a permanent, dedicated buffer that is
`distinct from system memory”
`
`
`
`Pet. Op. Br. (Paper 35) at 13-17; Pet. Reply Br. (Paper 39) at 6-8; Ex. 1026 (Lin Remand Decl.) at ¶¶ 31-34.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`39
`
`
`
`Disclosure of “Hardware Buffer”:
`Bauer and Svensson’s ISA Is Efficient
`
`Ex. 1010 (Svensson) at 3.64-4.3.
`
`Pet. Reply Br. (Paper 39) at 7; Ex. 1026 (Lin Remand Decl.) at ¶ 33.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`40
`
`
`
`Disclosure of “Hardware Buffer”:
`“Hardware Buffer” Can Be Implemented in RAM
`
`Dr. Martin Rinard (Patent Owner’s Expert)
`Q. Could the hardware buffer in the ‘949 Patent be implemented
`in RAM?
`A. … So “’hardware buffer’ should be construed as ‘a permanent,
`dedicated buffer that is distinct from system memory,” so that proposed
`construction focuses on one particular aspect of it. It doesn’t focus on
`any specific technology for implementing it. I would say in some
`situations, depending on the kind of RAM that you’re talking about, it
`could potentially be implemented in RAM, but, again, you’d have to
`take a look at the specific system and see that in the context of the
`claim, that it makes sense for the hardware buffer to be implemented in
`that particular whatever technology you’re talking about.
`And, again, I’d point out that RAM here is not limited to DRAM. DRAM
`is a kind of RAM. And we also talked earlier about SRAM, which is static
`RAM.
`
`Pet. Reply Br. (Paper 39) at 4.
`
`Ex. 1028 (Rinard Dep.) at 77:8-80:1 (emphasis added).
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`41
`
`
`
`Overview: Issues on Remand
`
`1. Claim construction for “hardware buffer.”
`
`2. Whether Bauer and Svensson disclose a “hardware buffer.”
`
`3. Whether the Board can resolve the prior art challenge
`to the patentability of claims 16 and 17 despite the
`potential indefiniteness of the means-plus function
`terms, along with whether these means-plus-function
`terms of claims 16 and 17 are indefinite.
`
`Pet. Op. Br. (Paper 35) at 1.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`42
`
`
`
`Federal Circuit Guidance: Claims 16 and 17
`
`“Importantly, it is not always impossible to adjudicate a prior-art challenge,
`one way or the other, just because some aspect of a claim renders the claim
`indefinite. . . . The indefiniteness of a limitation (here, a means-plus-
`function limitation) precludes a patentability determination only when the
`indefiniteness renders it logically impossible for the Board to reach such a
`decision.
`
`On remand, the Board must decide one or both of two issues. One is
`whether it can resolve the prior-art challenge to the patentability of claims 16
`and 17 despite the potential indefiniteness of the means-plus-function terms.
`The other is whether those terms are actually indefinite. We express no view
`on which issue the Board should consider first. If the Board determines both
`that there is indefiniteness and that such indefiniteness renders it impossible
`to adjudicate the prior-art challenge on its merits, then the Board should
`conclude that it is impossible to reach a decision on the merits of the
`challenge and so state in its decision.”
`
`Intel Corp. v. Qualcomm Inc., 21 F.4th 801, 813-14 (Fed. Cir. 2021).
`
`Pet. Op. Br. (Paper 35) at 17-20.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`43
`
`
`
`Claims 16 and 17: There Is Only One Possible
`Corresponding Structure, Whether Adequate or Not
`
` The parties have proposed a single corresponding structure for
`the two means-plus-function limitations at issue
`
`Patent Owner in
`ITC Action
`
`Petition
`
`The purported “structure”
`identified in the specification
`that relates to the claimed
`function is “a modem
`processor coupled to a system
`memory,” as described in the
`’949 patent at Abstract, 1:24-
`33, 4:10-15, 4:58-5:43, 5:59-
`6:39, 7:60-10:44, 8:21-30,
`8:62-67, 9:3-8, 9:16-56,
`10:13-18 and 10:27-32, and
`as shown in Figs. 1-3.
`
`Ex. 1008 (joint claim construction chart) at 4-6.
`
`IPR2018-01335 Petition (Paper 3) at 19-22.
`
`Patent Owner’s
`Response
`The structure for the claimed
`“means for scatter loading
`…” is therefore a modem
`processor coupled to a system
`memory, as described in the
`’949 patent, with the scatter
`loader controller of the
`modem processor receiving
`incoming data and scatter
`loading it to the system
`memory based on the image
`header.
`POR (Paper 16) at 18-21.
`
`Pet. Op. Br. (Paper 35) at 18; IPR2018-01355 Petition (Paper 3) at 19-22.
`
`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
`
`44
`
`
`
`Claims 16 and 17: If There Is Inadequate Structure and It Is
`Logically Impossible to Decide Unpatentability, Board Should
`Decline to Rule on Merits
`
`“On remand, the Board must decide one or both of two issues.
`One is whether it can resolve the prior-art challenge to the
`patentability of claims 16 and 17 despite the potential
`indefiniteness of the means-plus-function terms.
`The other is whether those terms are actually indefinite. We express
`no view on which issue the Board should consider first. If the
`Board determines both that there is indefiniteness and that such
`indefiniteness renders it impossible to adjudicate the prior-art
`challenge on its merits, then the Board should conclude that it is
`impossible to reach a decision on the merits of the challenge and
`so state in its decision.”
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`Intel Corp. v. Qualcomm Inc., 21 F.4th 801, 813-14 (Fed. Cir. 2021) (emphases added).
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`Pet. Op. Br. (Paper 35) at 20.
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`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
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`45
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`IPR2018-01334
`Petitioner’s Demonstrative Exhibits on Remand
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`U.S. Patent No. 8,838,949
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`Respectfully Submitted,
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`Dated: August 2, 2022
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`/Joseph F. Haag/
`Joseph F. Haag
`Reg. No. 42,612
`Counsel for Petitioner
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`IPR2018-01334
`Petitioner’s Demonstrative Exhibits on Remand
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`U.S. Patent No. 8,838,949
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`CERTIFICATE OF SERVICE
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`I hereby certify that on August 2, 2022, I caused a true and correct copy of the
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`foregoing material:
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` PETITIONER’S DEMONSTRATIVE EXHIBITS ON REMAND
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`to be served via electronic mail on the following attorneys of record:
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`David B. Cochran, Reg. No. 39,142 (dcochran@jonesday.com)
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`Matthew W. Johnson, Reg. No. 59,108 (mwjohnson@jonesday.com)
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`Joseph M. Sauer, Reg. No. 47,919 (jmsauer@jonesday.com)
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`Joshua R. Nightingale, Reg. No. 67,865 (jrnightingale@jonesday.com)
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`David M. Maiorana, Reg. No. 41,449 (dmaiorana@jonesday.com)
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`/Joseph F. Haag/
`Joseph F. Haag
`Reg. No. 42,612
`Counsel for Petitioner
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