UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`Intel Corporation
`Petitioner
`v.
`Qualcomm Incorporated
`Patent Owner of U.S. Patent No. 8,838,949
`
`____________________________________________
`Trial No. IPR2018-013341
`____________________________________________
`REPLY DECLARATION OF BILL LIN, PH.D.
`ON BEHALF OF PETITIONER
`
`1 IPR2018-01335 and IPR2018-01336 have been consolidated with the instant
`
`proceeding.
`
`IPR2018-01334
`Intel v. Qualcomm
`INTEL 1023
`
`

`

`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D.
`
`TABLE OF CONTENTS
`INTRODUCTION ........................................................................................... 1
`I.
`QUALIFICATIONS ........................................................................................ 2
`II.
`III. RELEVANT LAW .......................................................................................... 2
`PATENT OWNER’S PROPOSED CONSTRUCTIONS ARE
`IV.
`INCORRECT ................................................................................................... 2
`“System Memory” ................................................................................. 2
`A.
`“Image Header” ..................................................................................... 5
`B.
`“Hardware Buffer” ................................................................................ 7
`C.
`“Scatter Loader Controller” .................................................................. 9
`D.
`E. Means-Plus-Function Limitations ....................................................... 11
`CLAIMS 1-23 ARE OBVIOUS .................................................................... 12
`The Discussion of “Bauer and Svensson Combined”
`A.
`Identifies the Relevant Disclosure ...................................................... 14
`A POSITA Would Have Been Motivated To Combine
`Bauer And Svensson ........................................................................... 16
`It Would Have Been Obvious To Transfer An Image In
`Bauer’s File Format To A System Memory Of A
`Secondary Processor Using Svensson’s Program Loader .................. 17
`Bauer in Combination with Svensson Meets the “System
`Memory” Requirements ...................................................................... 27
`The Combination of Bauer And Svensson Teaches The
`“Scatter Loading” Limitations ............................................................ 31
`The Combination Of Bauer And Svensson Alone Or
`With Kim Teaches The Secondary Processor Receiving
`The Image Header And Each Data Segment Separately .................... 36
`
`D.
`
`E.
`
`F.
`
`i
`
`V.
`
`B.
`
`C.
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`

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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D.
`
`G.
`
`H.
`
`The Combination of Bauer and Svensson Teaches a
`“Hardware Buffer” .............................................................................. 41
`The Combination of Bauer and Svensson Teaches a
`“Scatter Loader Controller” ................................................................ 43
`Dependent Claims 2 and 12 are Obvious ............................................ 46
`I.
`VI. CONCLUSION ............................................................................................. 48
`VII. AVAILABILITY FOR CROSS-EXAMINATION ...................................... 48
`VIII. RIGHT TO SUPPLEMENT .......................................................................... 48
`IX.
`JURAT ........................................................................................................... 49
`
`
`ii
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D.
`
`1.
`
`I, Bill Lin, Ph.D. declare as follows:
`
`I.
`
`INTRODUCTION
`2.
`I have been retained by Intel Corporation (“Intel” or “Petitioner”) as
`
`an independent expert consultant in this proceeding before the United States Patent
`
`and Trademark Office. I previously prepared and submitted Declarations in
`
`support of the Petitions in IPR2018-01334, IPR2018-01335, and IPR2018-01336,
`
`dated July 2, 2018 and July 3, 2018 (Exs. 1002, 1102, and 1202). I understand that
`
`IPR2018-01335 and IPR2018-01336 have been consolidated with IPR2018-01334.
`
`3.
`
`Since preparing my Declaration, I have reviewed Qualcomm’s Patent
`
`Owner’s Preliminary Responses (“POPRs”) in IPR2018-01334, IPR2018-01335,
`
`and IPR2018-01336, the Board’s Decision on Institution (“DOIs”) in IPR2018-
`
`01334, IPR2018-01335, and IPR2018-01336, Qualcomm’s Patent Owner
`
`Response (“POR”) in the consolidated IPR2018-01334 proceeding, Dr. Rinard’s
`
`declaration submitted in support of the POR (Ex. 2007), and the transcript of Dr.
`
`Rinard’s deposition on August 28, 2019 (Ex. 1022). I have been asked to review
`
`and respond to the POR, Dr. Rinard’s opinions and the Board’s Decisions on
`
`Institution.
`
`4.
`
`I am being compensated for my work on this matter, but my opinions
`
`are based on my own views of the patents and the prior art. My compensation in
`
`no way depends on the outcome of this proceeding or the content of my testimony.
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D.
`
`5.
`
`In preparing this Declaration, I reviewed and considered the
`
`specification, claims, and file history of U.S. Patent No. 8,838,949 (“’949 patent”)
`
`(Ex. 1001). I have also reviewed and considered the documents cited by Dr.
`
`Rinard in his declaration (Ex. 2007). Additionally, I have reviewed the related
`
`Reply, which I understand Intel will file at the United States Patent and Trademark
`
`Office (USPTO) at the same time as this Declaration is filed at the USPTO.
`
`6.
`
`I have also reviewed all of the documents I cite in this declaration
`
`II. QUALIFICATIONS
`7.
`I describe my qualifications in my first Declarations. Ex. 1002, ¶¶2-
`
`12; Ex. 1102, ¶¶1-11; Ex. 1202, ¶¶1-12.
`
`III. RELEVANT LAW
`8.
`In my first Declarations, I set forth the applicable principles of patent
`
`law that were provided to me by counsel. Ex. 1002, ¶¶16-27; Ex. 1102, ¶¶15-26;
`
`Ex. 1202, ¶¶16-27. As appropriate, I have continued to apply those principles in
`
`providing my opinions in this Declaration.
`
`IV. PATENT OWNER’S PROPOSED CONSTRUCTIONS ARE
`INCORRECT
`A.
` “System Memory”
`9.
`Patent Owner asserts that the term “system memory” in independent
`
`claims 1, 10, 16, 18, 20, and 22 (and dependent claims 2, 4, 5, 8, and 12) should be
`
`interpreted to mean “memory that is addressable by the secondary processor.”
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D.
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`POR at 9. Petitioner did not ask to construe this term, the Board found it
`
`unnecessary in its Institution Decisions to construe this term, 1334 DI at 8; 1335
`
`DI at 15; 1336 DI at 8, and Patent Owner itself did not seek a construction of
`
`“system memory” in the district court or ITC litigations. See Ex. 1008; Ex. 1024.
`
`10.
`
`If the Board decides to construe the term, Patent Owner’s proposed
`
`construction should be rejected.
`
`11. First, Patent Owner asserts that its proposed construction reflects the
`
`plain meaning of “system memory.” However, Patent Owner does not cite any
`
`intrinsic evidence in support of that assertion beyond generic statements in the
`
`patent referring to “system memory.” Patent Owner’s construction does not reflect
`
`plain meaning. Instead, Patent Owner’s proposal tries to convert the requirement
`
`for “system memory” into just “memory.” This would make it so the limitation
`
`could be met by any type of memory addressable by a processor. For example,
`
`Patent Owner’s construction is so broad that it could cover non-volatile memory
`
`such as flash memory and read only memory (ROM) addressable by a processor—
`
`even though a POSITA would not have considered either to be a type of system
`
`memory. System memory is where an executable software image can be loaded
`
`and executed. This cannot be done with a non-volatile memory like a flash
`
`memory or read only memory (ROM).
`
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D.
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`12. Second, Patent Owner’s proposed construction does not specify what
`
`sets a “system memory” apart from other memories. In other words, it does not
`
`specify that a system memory is where an executable software image can be loaded
`
`and executed.
`
`13. This is also the same meaning used in the ’949 patent, which
`
`consistently describes system memory as the memory where programs (e.g., scatter
`
`loaded data segments of an executable software image) are loaded and executed.
`
`Ex. 1001, 2:61-63 (describing “loading the executable software image directly
`
`from the hardware buffer to the system memory”); id., 5:48-51 (“The modem Boot
`
`ROM code 126 may then jump into that modem executable image 132 and start
`
`executing the main modem program from the modem processor RAM 112 [i.e.,
`
`system memory]”); id., 8:18-21 (referring to “where the modem image executable
`
`data is to be eventually placed into the system memory of the secondary processor
`
`305”); id., 9:37-41 (“[T]he executable software image is loaded into the system
`
`memory of the secondary processor ….”); id., claim 22 (requiring “scatter
`
`load[ing] each received data segment directly to a system memory of the
`
`secondary processor; and executing, at the secondary processor, the executable
`
`software image”). The purpose of loading an “executable software image” to
`
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D.
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`target locations in “system memory” in the ’949 patent is so that the executable
`
`software image can be executed.
`
`14. Therefore, if the Board construes the term, it should be defined to
`
`mean “memory where an executable software image can be loaded and executed.”
`
`B.
`15.
`
`“Image Header”
`I understand that Patent Owner agreed in the district court and ITC
`
`litigations that “image header” means “a header associated with the entire image
`
`that specifies where the data segments are to be placed in the system memory,” and
`
`Patent Owner has adopted the same construction in this proceeding. POR at 12-13;
`
`Ex. 1008 at 10; Ex. 1024 at 25. Petitioner agreed that construction should apply
`
`here, 1334 Pet. at 17, but the Board has identified three potential issues with this
`
`agreed-upon construction.
`
`16. First, the Board noted that the proposed construction does not provide
`
`a separate definition for a “header.” 1334 DI at 7; 1335 DI at 7; 1336 DI at 7. I
`
`understand that no party sought a separate construction of that term in either of the
`
`litigations (or here) because the term has a well-known plain meaning. Ex. 1008;
`
`Ex. 1024. Thus, whether the prior art discloses the “header” portion of the
`
`limitation is a factual question.
`
`17. Second, the Board found that the “at least one data segment” language
`
`of the challenged claims can be met by an executable software image containing
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D.
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`just a single data segment, but suggested the plural term “data segments” in the
`
`agreed-to construction might require multiple data segments. 1334 DI at 7; 1335
`
`DI at 7; 1336 DI at 7. I understand that Petitioner agrees that the claims can be met
`
`by a single data segment, but disagrees that the term “data segments” in the
`
`construction requires multiple data segments. Rather, the plural term simply
`
`reflects that if a secondary processor in the claimed system receives multiple data
`
`segments, the “image header” must scatter load all of them (plural). In other
`
`words, the plural term “data segments” in the agreed-to construction refers to all
`
`data segments of an image, whether the image has one or more than one data
`
`segment. If the Board believes that clarification is needed, consistent with that
`
`understanding, changing “data segments” in the proposed construction to “one or
`
`more data segments” would be acceptable.
`
`18. Third, the Board stated that the agreed-to construction is unduly
`
`narrow to the extent it requires the “image header” to specify where data segments
`
`are to be placed in system memory. 1334 DI at 7; 1335 DI at 7; 1336 DI at 7. I
`
`respectfully submit that this requirement is consistent with the ’949 patent’s
`
`description of an “image header.” E.g., Ex. 1001, 8:18-21 (“The image header
`
`includes information used to identify where the modem image executable data is to
`
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D.
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`be eventually placed into the system memory of the secondary processor 305.”);
`
`see 1334 Pet. at 17.
`
`19. Petitioner has shown how the prior art teaches an “image header”
`
`under the agreed-upon construction, that is, a construction that specifies where data
`
`segments are to be placed in system memory. 1334 Pet. at 26-35 (citing relevant
`
`portions of my initial declaration). If the Board affirms its initial conclusion that
`
`“the image header is perhaps better described as having information that can be
`
`used to determine the placement of the at least one data segment in the system
`
`memory,” 1334 DI at 8; 1335 DI at 8; 1336 DI at 8, the prior art will even more
`
`clearly meet the “image header” limitation under that broader definition.
`
`C.
`“Hardware Buffer”
`20. Patent Owner asserts that the term “hardware buffer” (claims 1, 2, 8,
`
`and 12) should be interpreted to mean “a buffer within a hardware transport
`
`mechanism that receives data sent from the primary processor to the secondary
`
`processor.” POR at 14. Petitioner did not construe this term, the Board found it
`
`unnecessary to construe this term, 1334 DI at 8; 1335 DI at 15; 1336 DI at 8, and
`
`Patent Owner did not seek a construction of this term in the district court or ITC
`
`proceeding. See Ex. 1008; Ex. 1024.
`
`21.
`
`If the Board decides to construe the term, Patent Owner’s proposed
`
`construction should be rejected.
`
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D.
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`22. First, Patent Owner has failed to offer evidence suggesting that a
`
`POSITA would have understood the plain meaning of a “hardware buffer” to
`
`require a buffer residing in a “hardware transport mechanism.” Nor has Patent
`
`Owner identified any instance in which the intrinsic evidence purports to define a
`
`“hardware buffer” in such a specialized, non-plain meaning manner. There is no
`
`such instance.
`
`23. To the contrary, the language of claim 1 merely requires the
`
`“hardware buffer” to be part of the “secondary processor.” It does not require it to
`
`exist in any specific place within that processor, and in fact, does not even mention
`
`a “hardware transport mechanism.” Ex. 1001, claim 1 (“a secondary processor
`
`comprising … a hardware buffer”). Further, the specification only uses the term
`
`“hardware buffer” twice—(1) when repeating the language of claim 1, Ex. 1001,
`
`2:58-61 (“a secondary processor having … a hardware buffer”), and (2) when
`
`describing how, in one embodiment, the “entire” executable software image is not
`
`stored in the hardware buffer. Ex. 1001, 9:37-41 (“In one aspect, the executable
`
`software image is loaded into the system memory of the secondary processor
`
`without an entire executable software image being stored in the hardware buffer of
`
`the secondary processor.”). As such, there is no intrinsic support for Patent
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D.
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`Owner’s attempt to require the “hardware buffer” to reside within a “hardware
`
`transport mechanism.”
`
`24. Second, Patent Owner’s construction relies entirely on the fact that
`
`Figure 3 of the ’949 patent shows a “Hardware Buffer” within a “Hardware
`
`Transport Mechanism.” POR at 14-15. But the specification expressly states that
`
`Figure 3 is merely “exemplary,” and Patent Owner has identified no evidence
`
`suggesting that the named inventors intended to limit the “hardware buffer” of
`
`claim 1 to that single example. Ex. 1001, 7:60-63 (“In one aspect of the present
`
`disclosure, the loading process is divided into two stages, as illustrated in the
`
`exemplary flow shown in FIG. 3.”). Moreover, the location of the buffer does not
`
`characterize the buffer itself, so it does not make sense to construe it in that
`
`manner.
`
`25. Patent Owner’s construction should therefore be rejected, and the term
`
`“hardware buffer” should be given its ordinary meaning of “a buffer implemented
`
`in hardware.”
`
`D.
`“Scatter Loader Controller”
`26. Patent Owner asserts that the term “scatter loader controller” (claims 1
`
`and 2) should be interpreted to mean “a component of a hardware transport
`
`mechanism that scatter loads data received from the primary processor directly into
`
`the system memory of the secondary processor.” POR at 15. Once again,
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D.
`
`Petitioner did not construe this term, the Board did not find it necessary to construe
`
`this term, 1334 DI at 8; 1335 DI at 15; 1336 DI at 8, and Patent Owner did not
`
`request a construction of this term in the district court or ITC litigations. See Ex.
`
`1008; Ex. 1024.
`
`27. No construction of the term is needed. If the Board decides to
`
`construe the term, Patent Owner’s proposed definition should be rejected.
`
`28. First, Patent Owner has offered no evidence that a POSITA would
`
`have understood that the plain meaning of a “scatter loader controller” requires a
`
`component to necessarily reside in a “hardware transport mechanism.” Nor am I
`
`aware of any such evidence. Rather, a “scatter loader controller” is simply a
`
`controller that performs scatter loading, such as “scatter load[ing] each received
`
`data segment,” as recited in claim 1.
`
`29. Second, the plain language of claim 1 does not support Patent
`
`Owner’s proposed construction. The claim simply requires the “scatter loader
`
`controller” to be part of the “secondary processor,” without identifying any
`
`specific location where it must sit within the secondary processor, and without any
`
`mention of a “hardware transport mechanism.” Ex. 1001, claim 1 (“a secondary
`
`processor comprising … a scatter loader controller”). That is, the location of the
`
`scatter loader controller does not characterize the scatter loader controller itself.
`
`10
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D.
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`30. Third, nothing in the specification purports to define or otherwise
`
`require the claimed “scatter loader controller” to have the narrow meaning that
`
`Patent Owner proposes here (but did not propose in either litigation). See Ex.
`
`1008; Ex. 1024. And although Figure 3 shows controller 304 in a box labelled
`
`“Hardware Transport Mechanism,” it would be error to limit the claims to that
`
`single “exemplary” embodiment for the same reasons discussed above for the
`
`“hardware buffer” limitation.
`
`31.
`
`It is not necessary to construe the term “scatter loader controller.”
`
`Claim 1 sufficiently sets forth what the scatter loader controller must do—i.e.,
`
`“load the image” and “scatter load each received data segment.” Ex. 1001, claim
`
`1.
`
`E. Means-Plus-Function Limitations
`32.
`In the IPR2018-01335 proceeding, Petitioner proposed constructions
`
`for four means-plus-function terms recited in claim 16. 1335 Pet. at 18-22. In its
`
`Institution Decision, the Board agreed that each of these terms is a means-plus-
`
`function limitation and agreed with Petitioner’s identification of the claimed
`
`function. 1335 DI at 13.
`
`33. For the “means for processing …” and “means for scatter loading …”
`
`clauses, however, the Board found that the cited portions of the specification
`
`included insufficient structure to perform the claimed functions. 1335 DI at 14.
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D.
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`The Board encouraged the parties to address this issue, including the impact on this
`
`proceeding if the Board determines that the ’949 specification provides inadequate
`
`corresponding structure for the recited functions. 1335 DI at 14-15.
`
`34. Patent Owner disagrees with the Board and supports Petitioner’s
`
`proposed constructions—which are the same constructions that Patent Owner
`
`proposed in the ITC proceeding. POR at 18-21; Ex. 1008 at 4-6. I agree with the
`
`Board that the ’949 specification fails to disclose sufficient structure to perform the
`
`recited functions. This is the same position that Apple took for these terms in the
`
`ITC investigation. Ex. 1008 at 4-6.
`
`35. Further, I agree with Patent Owner that “[n]one of the arguments
`
`Qualcomm makes [in its Response] to distinguish the prior art requires
`
`construction of these [means-plus-function] limitations.” POR at 17.
`
`V. CLAIMS 1-23 ARE OBVIOUS
`36. As the Board preliminarily found, the challenged claims2 are
`
`unpatentable in view of the combination of Svensson and Bauer, or alternatively,
`
`
`2 The Board did not reach a preliminary conclusion as to claim 16 because it of its
`
`questions about the sufficiency of the corresponding structure, as noted above.
`
`1335 DI at 13-15. See above, §IV.E.
`
`12
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D.
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`in view of the combination of Bauer and Svensson with one or more of Kim, Zhao,
`
`and Lim:
`
`(1) Svensson teaches a multi-processor system in which a program loader
`
`can transfer an executable software image from a memory of a primary processor
`
`to system memory of a secondary processor via an intermediate hardware buffer;
`
`(2) Bauer discloses an executable software image format for use with
`
`Svensson’s system that contains one or more data segments and a header portion
`
`specifying where each data segment should be loaded for execution, and also
`
`teaches having a secondary processor receive the header portion separately from
`
`the data segments;
`
`(3) Kim confirms that having a processor separately receive the header
`
`and data segment portions of an executable software image was known in the prior
`
`art; and
`
`(4) Zhao and Lim confirm that conventional components such as modem
`
`processors and primary processor file systems were known. 1334 DI at 29; 1335
`
`DI at 37; 1336 DI at 31.
`
`37. Therefore, each challenged claim should be cancelled as obvious.
`
`38.
`
`In its Response, Patent Owner advances several arguments, none of
`
`which has merit. For example, Patent Owner argues that a POSITA would not
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D.
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`have been motivated to combine Svensson and Bauer—even though the references
`
`share the same inventors and much of the same disclosure, and Bauer expressly
`
`states that its invention was specifically designed for use with Svensson’s system.
`
`Patent Owner also maintains that, even if combined, the prior art still fails to teach
`
`multiple limitations. Many of those arguments depend on claim constructions that
`
`are incorrect for the reasons set forth above (and under which the claims are
`
`invalid in any event). Patent Owner’s other arguments depend on an inaccurate
`
`reading of the asserted prior art references that is not consistent with the
`
`references’ actual disclosure.
`
`39. Patent Owner has presented no reason for the Board to depart from its
`
`preliminary conclusion that the challenged claims are obvious in view of the
`
`asserted prior art. The Board should reach the same conclusion here and find that
`
`the claims are not patentable.
`
`A. The Discussion of “Bauer and Svensson Combined” Identifies the
`Relevant Disclosure
`40. Patent Owner argues that Petitioner has failed to demonstrate
`
`invalidity because the Petitions refer to Bauer and Svensson collectively using the
`
`phrase “Bauer and Svensson combined.” POR at 35-37. But as the Board
`
`previously found, and as explained in the Petitions and my initial declarations, that
`
`label is merely shorthand used to reflect the fact that Bauer and Svensson contain
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D.
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`significant overlap in their disclosures. 1334 DI at 16 (Board observing that
`
`“[b]ased on the interrelatedness of the references, Petitioner refers to the teachings
`
`of ‘Bauer and Svensson combined’”); 1334 Pet. at 24-25 (explaining shorthand use
`
`of term); Ex. 1002, ¶¶101-106.
`
`41. Moreover, despite Patent Owner’s claims to the contrary, the Petitions
`
`and my initial declarations identify the specific disclosures that Petitioner and I are
`
`relying on from each reference, as well as their key respective differences, as
`
`Patent Owner elsewhere admits in its Response. That is, that Bauer does not
`
`describe the multiprocessor system with the same level of detail as Svensson, and
`
`that Svensson does not disclose the improved file format introduced in Bauer.
`
`E.g., 1334 Pet. at 24-25 (“Bauer does not describe the multiprocessor system with
`
`the same level of detail as Svensson.”); id. at 30-31 (describing the multi-processor
`
`system “as described in Svensson, using Bauer’s file format”); id. at 33 (explaining
`
`how “Bauer expressly cites to Svensson as one example of a program loader that
`
`can load data using the invention described in Bauer.”); POR at 61 (“Recognizing
`
`that ‘Bauer does not explicitly describe the loading process from the primary
`
`processor to the secondary processor in much detail’ (Paper 3 at 33), Petitioner
`
`generally relies on Svensson as disclosing how data would be loaded in the
`
`described multi-processor system.”).
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D.
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`42.
`
`In addition, each time the petitions (and my initial declarations) use
`
`the phrase “Bauer and Svensson combined,” the petitions cite specific disclosures
`
`from Bauer, Svensson, or Bauer and Svensson, so that Patent Owner knows exactly
`
`what Petitioner relies on as teaching each claim limitation. E.g., 1334 Petition at
`
`25-26 (using term “Bauer and Svensson combined” for the preamble of claim 1
`
`and citing specific disclosures from each reference); id. at 26-27 (using term
`
`“Bauer and Svensson combined” and citing specific disclosures for each reference
`
`for the “secondary processor” limitation); id. at passim.
`
`B. A POSITA Would Have Been Motivated To Combine Bauer And
`Svensson
`43. Patent Owner suggests that a POSITA would not have been motivated
`
`to combine Bauer and Svensson in the manner that Petitioner has proposed. POR
`
`at 37. That argument is incorrect for several reasons.
`
`44. First, Bauer and Svensson are closely interrelated; as Petitioner
`
`previously explained, the two references were filed just four months apart, and
`
`they both share the same inventors, same assignee, same figures, and much of the
`
`same disclosure. 1334 Pet. at 23-25 (citing relevant discussion in my initial
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`declarations). This significant overlap alone weighs strongly in favor of finding a
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`motivation to combine the two references.
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D.
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`45. Second, Patent Owner’s lack of motivation to combine arguments are
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`incorrect because Bauer explicitly describes its file format as an improvement over
`
`Svensson’s format, and explicitly states that the new file format can be used with
`
`Svensson’s program loader and multi-processor system. 1334 Pet. at 23-24; Ex.
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`1009, cover ¶¶27, 31-36, 43, Figs. 1A-1C, 2; Ex. 1010, cover, Fig. 1, 3:49-4:8; Ex.
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`1002, ¶¶102-04; 1334 DI at 15 (“Bauer expressly cites Svensson’s program loader
`
`as an example of a program loader that can use the file format disclosed in
`
`Bauer.”); POR at 37 (Patent Owner admitting “it is conceivable that the POSA
`
`would be motivated to combine Bauer and Svensson”).
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`46. For these reasons, a POSITA would have been motivated to combine
`
`Bauer and Svensson precisely as I have proposed.
`
`C.
`
`It Would Have Been Obvious To Transfer An Image In Bauer’s
`File Format To A System Memory Of A Secondary Processor
`Using Svensson’s Program Loader
`47. As the Board found, it would have been obvious to use an executable
`
`software image in Bauer’s disclosed file format in connection with Svensson’s
`
`multi-processor system and program loader—such that the image is directly loaded
`
`into and executed from DSP XRAM memory 210 (system memory) of the
`
`secondary processor. 1334 Pet. at 25-52; 1335 Pet. at 29-57; 1336 Pet. at 26-66;
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`1334 DI at 15-29; 1335 DI at 22-37; 1336 DI at 15-32 (finding limitations met).
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D.
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`48.
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`In its Response, Patent Owner concedes that, in Bauer’s file format,
`
`“header 102 contains information about the total size and the total number of
`
`sections 106” (i.e., information associated with the entire image), and that “section
`
`information 104 contains an entry for each section 106 that includes information
`
`about the section length and load address” (i.e., information specifying where to
`
`scatter load the data segments into their final destination in system memory). POR
`
`at 27, 38-39.3 Patent Owner agrees that “Bauer expressly references Svensson as
`
`disclosing a program loader capable of ‘reading the stored information’ of data
`
`images in Bauer’s file format.” POR at 37, 48, 49, 50.4
`
`49. According to Patent Owner, however, a POSITA only would have
`
`been motivated to use Bauer’s file format for the image as originally stored in non-
`
`
`3 These two structures contain information similar to the ELF header (contains
`
`information about the entire image) and ELF program header table (identifies
`
`where to load each data segment in system memory for execution) that Patent
`
`Owner accused in related litigation as collectively meeting the “image header”
`
`requirements of the claims. E.g., Ex. 1025 at 6.
`
`4 Patent Owner offers the same file format conversion theory/arguments in multiple
`
`different sections of its brief. For convenience of the Board, I address that theory
`
`and related arguments in this single section.
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D.
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`volatile memory 106/206 of Svensson’s ARM CPU 102/202 (primary processor) in
`
`the combination of Bauer and Svensson. Patent Owner claims that, when loading
`
`the image for execution, a POSITA would have converted the image to Svensson’s
`
`disclosed file format—and added a header for each data segment—before loading
`
`and executing the image, because the only file format that Svensson discloses for
`
`use with its program loader is the file format disclosed in Svensson. POR at 38-47.
`
`That argument is incorrect for several reasons.
`
`50. First, as discussed below, a POSITA would have been motivated to
`
`use Bauer’s file format for all stages, including when loading and executing the
`
`image.
`
`51. Second, Patent Owner’s argument that because Bauer expressly states
`
`that its disclosed file format is suitable for loading the image for execution,
`
`including by Svensson’s program loader:
`
`There are many possible applications of this format and its
`
`individually coded sections. For example, an operating system
`
`memory manager can load and unload sections of memory
`
`according to images in this format. It can also be used as a file
`
`format in which executable files are stored, and linkers and
`
`program loaders can be readily adapted to support (read,
`
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`U.S. Patent No. 8,838,949
`Reply Declaration of Bill Lin, Ph.D.
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`write, and interpret) the format. Object code and data can also
`
`be stored in this file format, with a program loader reading the
`
`stored information and processing stored sections
`
`accordingly. One example of such a program loader is
`
`described in U.S. patent application Ser. No. 11/040,798 filed
`
`on Jan. 22, 2005, by M. Svensson et al. for “Operating-
`
`System-Friendly Bootloader”.
`
`Ex. 1009 at [0031]. It would make no sense to conclude that a POSITA would not
`
`use Bauer’s file format when loading an image for execution in Svensson’s system
`
`when Bauer itself instructs to use Svensson’s program loader for that very purpose.
`
`52. Bauer also explicitly states that images in its file format shown in
`
`Figures 1A, 1B, and 1C could be stored in “any one or more” of the memories—
`
`which include both the intermediate storage area (hardware buffer) and the DSP
`
`XRAM 210 (system memory) of the secondary processor DSP CPU 204:
`
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`U.S. Patent No. 8,838,949
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`
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`Ex. 1009, Fig. 2; id. at [0036] (“The arrows in FIG. 2 indicate access paths, e.g.,
`
`busses and dir