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`UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________
`
`Intel Incorporated
`Petitioner
`
`v.
`
`Qualcomm Incorporated
`Patent Owner
`______________________
`
`Case IPR2018-013341
`Patent 8,838,949
`______________________
`
`PATENT OWNER RESPONSE TO PETITION FOR INTER PARTES
`REVIEW PURSUANT TO 37 C.F.R. § 42.220
`
`
`
`
`
`
`1 IPR2018-01335 and IPR2018-01336 have been consolidated with the instant
`proceeding.
`
`

`

`TABLE OF CONTENTS
`INTRODUCTION ........................................................................................... 1 
`I. 
`THE ALLEGED GROUND OF UNPATENTABILITY ............................... 2 
`II. 
`III.  THE ’949 PATENT AND ITS PROSECUTION HISTORY ......................... 3 
`A.  Overview of the ’949 Patent .................................................................. 3 
`B. 
`Prosecution History of the ’949 Patent ................................................. 8 
`IV.  CLAIM CONSTRUCTION ............................................................................ 9 
`A. 
`System Memory .................................................................................... 9 
`B. 
`Image Header ...................................................................................... 12 
`C.  Hardware Buffer .................................................................................. 14 
`D. 
`Scatter Loader Controller .................................................................... 15 
`E.  Means-Plus-Function Limitations ....................................................... 17 
`“means for processing, by the secondary processor, the image
`1. 
`
`header to determine at least one location within system memory
`
`to which the secondary processor is coupled to store each data
`
`segment” .................................................................................... 18 
`2. 
`“means for scatter loading, by the secondary processor, each
`
`data segment directly to the determined at least one location
`
`within the system memory, and each data segment being scatter
`
`loaded based at least in part on the processed image
`
`header” ...................................................................................... 20 
`LEVEL OF ORDINARY SKILL IN THE ART ........................................... 21 
`V. 
`VI.  OVERVIEW OF THE CITED REFERENCES ............................................ 22 
`A.  Overview of Svensson ......................................................................... 22 
`B.  Overview of Bauer .............................................................................. 26 
`C.  Overview of Kim ................................................................................. 28 
`
`

`

`D.  Overview of Zhao ................................................................................ 31 
`E. 
`Overview of Lim ................................................................................. 32 
`VII.  PETITIONER’S PROPOSED REFERENCE COMBINATIONS DO NOT
`
`RENDER CLAIMS 1-23 OBVIOUS ............................................................ 33 
`The Petitions Fail to Establish a Prima Facie Case of
`A. 
`
`Obviousness. ........................................................................................ 35 
`B. 
`The POSA Would Not Combine Bauer, Svensson, and Kim as
`
`Proposed by Petitioner, and the Reference Combinations Therefore
`
`Fail to Render Obvious the Challenged Claims. ................................. 37 
`Bauer Is Directed to a File Format of a Binary Data Image and
`1. 
`
`Provides No Disclosure on Loading Data in a Multi-Processor
`
`System. ...................................................................................... 38 
`2. 
`Svensson Discloses a Bootloader and Method of Loading Data
`
`from a Primary Processor to a Secondary Processor. ............... 40 
`3. 
`In Combining Bauer and Svensson, the POSA Would Follow
`
`the Express Teachings of Svensson to Transfer Data to the
`
`Secondary Processor in a Block Format. .................................. 43 
`4. 
`Properly Combined, the References Fail to Meet Multiple
`
`Claim Limitations. .................................................................... 48 
`Even if the POSA Was Motivated to Combine the References Such
`that the Secondary Processor Receives the Binary Data Image of
`Bauer, the Reference Combinations Still Fail to Meet Multiple
`Limitations. .......................................................................................... 50 
`Loading Each Received Data Segment Directly to System
`1. 
`
`Memory of the Secondary Processor ........................................ 50 
`2. 
`Scatter Loading ......................................................................... 58 
`3. 
`The Secondary Processor Receiving the Image Header and
`
`Each Data Segment Separately ................................................. 61 
`Hardware Buffer ....................................................................... 70 
`4. 
`
`C. 
`
`
`
`
`

`

`Scatter Loader Controller .......................................................... 71 
`5. 
`The Limitations of Dependent Claims 2 and 12 ....................... 75 
`6. 
`CONCLUSION ................................................................................... 78 
`
`VIII. 
`
`
`

`

`Pursuant to the Board’s Institution Decisions in IPR2018-01334, -01335, and
`
`-01336 (Paper 10 in each proceeding, entered March 18, 2019), Patent Owner
`
`Qualcomm, Inc. (“Qualcomm” or “Patent Owner”) submits this response in
`
`opposition to the Petitions for Inter Partes Review of U.S. Patent No. 8,838,949 (the
`
`“’949 patent”) filed by Intel Incorporated (“Intel” or “Petitioner”).
`
`I.
`
`INTRODUCTION
`The ’949 patent describes and claims improved systems for loading a data
`
`image from a first “primary” processor onto a target “secondary” processor. The
`
`patent describes that in prior-art approaches, a data image is loaded to a secondary
`
`processor using an intermediate buffering step, where data is transferred into a
`
`temporary buffer of the system memory and then loaded into “target locations” of
`
`the system memory. Ex. 10012 at 2:17-34. The ’949 patent improves upon the
`
`conventional technology by providing “a direct scatter load technique” for loading
`
`an image from a primary processor to a secondary processor without using “the
`
`intermediate step of buffering required in traditional loading processes.” Id. at 4:43-
`
`47; 7:20-26. The ’949 patent refers to this as a “Zero Copy Transport Flow” and
`
`describes the technique in detail. Id. at 7:16-12:57.
`
`
`2 All citations to Petitioner’s exhibits herein refer to the exhibits listed in
`Petitioner’s Consolidated Exhibit List (Paper 14), as filed in IPR2018-01334.
`
`
`
`1
`
`

`

`Claims 1-23 of the ’949 patent recite systems, methods, and apparatuses that
`
`cover the direct scatter load technique described in the specification. Id. at 12:59-
`
`16:21. Petitioner challenges these claims as allegedly being obvious, but the
`
`fundamental problem with Petitioner’s case is that none of the applied references
`
`relate to loading an image from a primary processor to a secondary processor without
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`an intermediate buffering step. In fact, in the hypothetical combinations of
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`references proposed by Petitioner, data is first loaded into one part of system
`
`memory and then copied to target locations of the system memory—the very same
`
`intermediate buffering step that the ’949 patent seeks to avoid. See, e.g., Ex. 2007
`
`(Rinard Decl.) at ¶¶135, 138, 144. Petitioner’s obviousness grounds are deficient
`
`for this reason and those detailed below, and the combinations of references thus fail
`
`to render obvious any of the challenged claims.
`
` Claims 1-23 of the ’949 patent should be confirmed.
`
`II. THE ALLEGED GROUND OF UNPATENTABILITY
`The Board instituted inter partes review in cases IPR2018-01334, -01335, and
`
`-01336, and consolidated the trials. Paper 12. 3 The alleged grounds of
`
`unpatentability for this consolidated trial are:
`
`
`3 All citations to papers (e.g., “Paper 12”) herein refer to documents filed in
`IPR2018-01334 unless otherwise noted.
`
`
`
`2
`
`

`

` Claims 1-15, 22, and 23 are unpatentable under 35 U.S.C. § 103 over
`
`Bauer, Svensson, and Kim;
`
` Claims 16 and 17 are unpatentable under 35 U.S.C. § 103 over Bauer,
`
`Svensson, Kim, and Zhao; and
`
` Claims 18–21 are unpatentable under 35 U.S.C. § 103 over Bauer,
`
`Svensson, Kim, and Lim.
`
`Id. at 3.
`
`III. THE ’949 PATENT AND ITS PROSECUTION HISTORY
`A. Overview of the ’949 Patent
`U.S. Patent No. 8,838,949 (“the ’949 patent”), titled “Direct Scatter Loading
`
`of Executable Software Image From a Primary Processor to One or More Secondary
`
`Processor in a Multi-Processor System,” generally relates to multi-processor
`
`systems in which a primary processor is coupled to a non-volatile memory storing
`
`executable software image(s) of one or more secondary processors that are each
`
`coupled to a dedicated volatile memory, where the executable software images are
`
`efficiently communicated from the primary processor to the secondary processor(s)
`
`in a segmented format (e.g., using a direct scatter load process). Ex. 1001 at 1:25-
`
`33. The ’949 patent issued on September 16, 2014 from an application filed on
`
`March 21, 2011. The ’949 patent claims priority to three provisional applications,
`
`the earliest of which was filed on April 14, 2010.
`
`
`
`3
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`

`

`“In a multi-processor system, each processor may require respective boot code
`
`for booting up. As an example, in a smartphone device that includes an application
`
`processor and a modem processor, each of the processors may have respective boot
`
`code for booting up.” Id. at 1:39-43. The ’949 patent explains that in some multi-
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`processor systems, one of the processors is responsible for storing the boot code for
`
`one or more other processors in the system and loading the respective boot code to
`
`the other processor(s) at power-up. “In this type of system, the software (e.g., boot
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`image) is downloaded from the first processor to the other processor(s) (e.g., to
`
`volatile memory of the other processor(s)), and thereafter the receiving processor(s)
`
`boots with the downloaded image.” Id. at 2:1-14.
`
`The Background section of the ’949 patent describes systems in which the
`
`boot image is loaded onto a target “secondary” processor from a first “primary”
`
`processor using “an intermediate step where the binary multi-segmented image is
`
`transferred into the system memory and then later transferred into target locations
`
`by the boot loader.” Id. at 2:17-22. “[O]ne way of performing such loading is to
`
`allocate a temporary buffer into which each packet is received.” Id. at 2:25-26.
`
`“[T]he temporary buffer would be some place in system memory, such as in internal
`
`random-access-memory (RAM) or double data rate (DDR) memory, for example.”
`
`Id. at 2:32-34.
`
`
`
`4
`
`

`

`The ’949 patent improves upon the technology described in its Background
`
`section by providing “a direct scatter load technique” for loading a segmented image
`
`from a primary processor’s non-volatile memory to a secondary processor’s volatile
`
`memory without using “the intermediate step of buffering required in traditional
`
`loading processes.” Id. at 4:43-47; 7:20-26. The ’949 patent refers to this as a “Zero
`
`Copy Transport Flow,” an example of which is illustrated in Fig. 3, reproduced
`
`below.
`
`
`
`5
`
`

`

`
`
`Id. at Fig. 3.
`
`In Fig. 3, a software image (e.g., boot image) for the secondary processor 302
`
`is stored to non-volatile memory of the primary processor 301. Id. at 7:67-8:2. The
`
`software image 303 is a multi-segmented image that includes an image header and
`
`multiple data segments (shown as data segments 1-5). Id. at 8:2-5. In a first stage
`
`of the loading process, the image header is transferred from the primary
`
`
`
`6
`
`

`

`processor 301 to a scatter loader controller 304 of the secondary processor 302. Id.
`
`at 8:9-11; 9:21-23. The image header includes information used by the secondary
`
`processor 302 to identify where each of the image data segments are to be placed
`
`into system memory 305. Id. at 8:18-21; 8:57-63; 9:23-24. “Data segments are then
`
`sent from system memory 307 to the primary hardware transport mechanism 308.
`
`The segments are then sent from the hardware transport mechanism 308 of the
`
`primary processor 301 to a hardware transport mechanism 309 of the secondary
`
`processor 302 over an inter-chip communication bus 310 (e.g., a HS-USB cable.)”
`
`Id. at 8:24-30. Using the information from the image header, the scatter load
`
`controller 304 transfers the image segments from the hardware buffer of the
`
`hardware transport mechanism 309 directly into their respective target locations in
`
`the secondary processor’s system memory 305. Id. at 9:21-27.
`
`
`
`Claim 1 of the ’949 patent is exemplary:
`
`1. A multi-processor system comprising:
`a secondary processor comprising:
`system memory and a hardware buffer for receiving an image header
`and at least one data segment of an executable software image, the
`image header and each data segment being received separately,
`and
`a scatter loader controller configured:
`to load the image header, and
`to scatter load each received data segment based at least in part
`on the loaded image header, directly from the hardware buffer
`to the system memory;
`
`
`
`7
`
`

`

`a primary processor coupled with a memory, the memory storing the
`executable software image for the secondary processor; and
`an interface communicatively coupling the primary processor and the
`secondary processor, the executable software image being received
`by the secondary processor via the interface.
`
`B.
`Prosecution History of the ’949 Patent
`U.S. Patent Application No. 13/052,516, which later issued as the ’949 patent,
`
`was filed on March 21, 2011. The original claims of the application were all rejected
`
`in an Office Action issued on July 19, 2013 as allegedly being anticipated by
`
`International Publication No. WO 2006/077068 to Svensson (Ex. 1003), which is
`
`referred to by Petitioner as “Svensson PCT.” Ex. 1004. Svensson PCT claims
`
`priority to, and includes the same disclosure as, the Svensson patent (Ex. 1010) that
`
`is relied on throughout the Petitions as the primary reference.
`
`In response to the rejections over Svensson PCT, the independent claims were
`
`amended to require receiving, at a secondary processor, an image header and at least
`
`one data segment of an executable software image, with “the image header and each
`
`data segment being received separately.” Ex. 1005 at 2-7. The claims were further
`
`amended to require scatter loading each data segment directly to system memory of
`
`the secondary processor. Id.
`
`
`
`Following the amendments distinguishing the claims from Svensson PCT, no
`
`further prior-art rejections were made by the Patent Office. The ’949 patent was
`
`allowed on May 9, 2014 (Ex. 1006), and issued on September 16, 2014.
`
`
`
`8
`
`

`

`IV. CLAIM CONSTRUCTION
`
`37 C.F.R. § 42.100(b) states that claims must be given their broadest reasonable
`
`interpretation in light of the specification (“BRI”).
`
`A.
`System Memory
`
`Independent claims 1, 10, 16, 18, 20, and 22 of the ’949 patent recite the term
`
`
`
`“system memory” of a secondary processor. The claim term “system memory”
`
`should be interpreted to mean “memory that is addressable by the secondary
`
`processor.” Ex. 2007 at ¶52. This interpretation is consistent with the plain and
`
`ordinary meaning of the term as understood by the POSA, and support for this
`
`interpretation is found in the ’949 patent itself. Id. at ¶¶52-54.
`
`
`
`Specifically, the ’949 patent indicates that system memory is allocated by the
`
`secondary processor (Ex. 1001 at 2:14-34), which means that the system memory
`
`must be addressable by the secondary processor. Ex. 2007 at ¶52. Additionally, a
`
`purpose of the invention of the ’949 patent is to provide efficient loading of
`
`executable images into their final destinations in system memory so that the
`
`secondary processor can execute the code in the images. Id. at ¶53 (citing Ex. 1001
`
`at 7:17-20, 10:42-44 (“the secondary processor 302 may … execute transferred
`
`images”)). In order for the secondary processor to execute the code in the system
`
`memory, the system memory must necessarily be addressable by the secondary
`
`processor. Ex. 2007 at ¶53.
`
`
`
`9
`
`

`

`
`
`Further, the ’949 patent states that “the secondary processor’s CPU processes
`
`the image header in [system] memory 305.” Ex. 1001 at 9:27-28. This is shown in
`
`in Fig. 3 of the ’949 patent, which depicts an arrow extending from the image header
`
`in the system memory 305 to the CPU of the secondary processor 302. Id. at Fig. 3;
`
`Ex. 2007 at ¶54. The ’949 patent thus makes clear that the CPU of the secondary
`
`processor processes the image header stored in system memory, and this means that
`
`the system memory must be addressable by the secondary processor. Ex. 2007
`
`at ¶54.
`
`
`
`Support for the interpretation of “system memory” as “memory that is
`
`addressable by the secondary processor” is also found in the testimony of
`
`Petitioner’s declarant Dr. Lin. Id. at ¶¶55-58. At deposition, Dr. Lin defined
`
`“system memory” in the context of the ’949 patent as follows:
`
`[S]ystem memory … is the place where you load and run programs or
`where programs can be loaded and executed.
`
`Ex. 2001 (Lin Depo. Transcript) at 24:17-21. As seen above, Dr. Lin testified that
`
`system memory is memory where programs can be loaded and executed by a
`
`processor. Such memory is necessarily addressable by the processor, and Dr. Lin’s
`
`testimony thus supports Qualcomm’s proposed construction of system memory as
`
`“memory that is addressable by the secondary processor.” Ex. 2007 at ¶¶55-56.
`
`
`
`At a district court proceeding directed to the ’949 patent, Dr. Lin further
`
`characterized system memory as follows:
`
`
`
`10
`
`

`

`[S]ystem memory is a type of memory that the processor needs to have
`the program loaded into in order for it to run. DRAM is another name
`[for system memory]. It stands for dynamic random access memory.…
`And what’s referred to as DDR is a particular type of system memory.
`
`Ex. 2005 at 1162-1163. Similar to his deposition testimony, Dr. Lin testified that
`
`system memory stores a program executed by a processor and may be, for example,
`
`dynamic random access memory (DRAM) or double data rate (DDR) memory. Such
`
`memory is necessarily addressable by the processor, and this testimony thus supports
`
`Qualcomm’s proposed construction of “system memory.” Ex. 2007 at ¶¶57-58.
`
`
`
`Petitioner did not propose a construction for the term “system memory” in its
`
`Petitions. See Paper 3 at 16-17. However, the Petitions and supporting declarations
`
`of Dr. Lin provide ample support for Qualcomm’s proposed construction. Ex. 2007
`
`at ¶¶59-60. Specifically, the Petitions and declarations of Dr. Lin include a
`
`technology background section that characterizes “system memory” as follows:
`
`A processor usually must load a multi-segmented software image into
`its system memory before the processor can execute that image…. The
`processor first reads information about the image in the headers and/or
`tables or other structures of the image, and then uses that information
`to load the data segments into memory and execute the image. Ex-1002,
`¶44.
`Paper 3 at 7; Ex. 1002 (Lin Decl.) at ¶44 (emphasis added).
`
`Many prior art image formats were designed for scatter loading by
`including information in the image about where each data segment of
`the image should be loaded in system memory for later execution. Ex-
`1001, 2:37-41, 4:34-42. Ex-1002, ¶45.
`Paper 3 at 8; Ex. 1002 at ¶45 (emphasis added).
`
`
`
`11
`
`

`

`When a multi-processor system is first powered on, one or more
`processors typically load and execute “boot code” (or “boot software”)
`to enable the processor(s) to begin to operate. The boot code is often
`stored in a processor’s non-volatile memory, and during boot up, the
`boot code is typically loaded and executed from the processor’s system
`memory.
`Paper 3 at 8-9; Ex. 1002 at ¶¶49-50 (emphasis added).
`
`
`
`Each of the above statements of Petitioner and Dr. Lin confirms that system
`
`memory stores code for execution by a processor and is thus addressable by the
`
`processor. Ex. 2007 at ¶¶59-60. These statements provide further support for
`
`Qualcomm’s proposed construction. Id.
`
`
`
`For all of these reasons, the term “system memory” should be interpreted to
`
`mean “memory that is addressable by the secondary processor.”
`
`B.
`Image Header
`Independent claims 1, 10, 16, 18, 20, and 22 of the ’949 patent recite the term
`
`
`
`“image header.” Petitioner and its declarant Dr. Lin state that the term should be
`
`construed as “a header associated with the entire image that specifies where the data
`
`segments are to be placed in the system memory.” Paper 3 at 16-17; Ex. 1002 at ¶77.
`
`At deposition, Dr. Lin confirmed his opinion that the term should be construed as
`
`proposed in the Petitions. Ex. 2001 (Lin Depo. Transcript) at 21:3-16. As noted in
`
`the Petitions (Paper 3 at 17), the parties agreed to the proposed construction in the
`
`related ITC case (Ex. 1008 at 3), and Qualcomm agrees that the proposed
`
`
`
`12
`
`

`

`construction
`
`is
`
`the broadest reasonable
`
`interpretation consistent with
`
`the
`
`specification and should therefore be applied in this IPR proceeding.
`
`
`
`In its Institution Decisions, however, the Board stated that “Petitioner’s
`
`proposed construction is problematic for [multiple] reasons.” Paper 10 at 7. The
`
`Board described the alleged problems with the proposed construction, including that
`
`the construction “recites ‘data segments,’ suggesting that plural data segments are
`
`required, but the claims recite ‘at least one data segment’ and, therefore, are met by
`
`only a single data segment.” Id. The Board concluded that “the image header is
`
`perhaps better described as having information that can be used to determine the
`
`placement of the at least one data segment in the system memory.” Id. at 8.
`
`
`
`Respectfully, the Board’s criticism of the proposed construction is misplaced,
`
`especially given the agreement of the parties. In any event, Qualcomm disagrees
`
`with the Board’s conclusion that “the image header is perhaps better described as
`
`having information that can be used to determine the placement of the at least one
`
`data segment in the system memory” (id.) at least because it fails to capture the
`
`requirement that the image header must be associated with the entire image.
`
`Ex. 2007 at ¶¶62-68. The Board provided three reasons why Petitioner’s proposed
`
`construction is allegedly problematic (Paper 10 at 7-8), and none of these reasons is
`
`directed to the part of the construction requiring the image header to be “associated
`
`with the entire image.” This part of the construction is consistent with the
`
`
`
`13
`
`

`

`specification and claims of the ’949 patent (see, e.g., Ex. 1001 at 7:48-52, 8:18-21,
`
`8:57-60, 9:23-24, 10:3-6, 13:56-59) and should be maintained. Ex. 2007 at ¶¶64-68.
`
`
`
`Thus, even assuming arguendo that the image header need only have
`
`information that can be used to determine the placement of one data segment in the
`
`system memory, as the Board asserts (Paper 10 at 8), the image header must
`
`nevertheless be associated with the entire image. Ex. 2007 at ¶¶64-68. This means
`
`that the image header must be associated with each and every data segment of the
`
`image, even if the image contains only one data segment. Id. at ¶68.
`
`C. Hardware Buffer
`Claims 1-9 and 12 of the ’949 patent require a “hardware buffer.” This term
`
`
`
`should be interpreted to mean “a buffer within a hardware transport mechanism that
`
`receives data sent from the primary processor to the secondary processor.” Ex. 2007
`
`at ¶69. This interpretation is consistent with the plain and ordinary meaning of the
`
`term as understood by the POSA, and support for this interpretation is found in
`
`the ’949 patent. Id. at ¶¶69-71.
`
`
`
`Specifically, the ’949 patent discloses that “[t]he system includes a secondary
`
`processor having a system memory and a hardware buffer for receiving at … least a
`
`portion of an executable software image.” Ex. 1001 at 2:58-61. Fig. 3 shows that
`
`the hardware buffer is a component within hardware transport 309. Id. at Fig. 3;
`
`Ex. 2007 at ¶70. Fig. 3 further shows that the hardware buffer receives data from
`
`
`
`14
`
`

`

`primary processor 301 via inter-chip communication bus 310 (e.g., a HS-USB cable).
`
`Ex. 2007 at ¶70. The patent describes the hardware buffer’s receipt of data from the
`
`primary processor 301, stating that “[d]ata segments are … sent from system
`
`memory 307 to the primary hardware transport mechanism 308. The segments are
`
`then sent from the hardware transport mechanism 308 of the primary processor 301
`
`to a hardware transport mechanism 309 of the secondary processor 302 over an inter-
`
`chip communication bus 310 (e.g., a HS-USB cable).” Id. at 8:24-30. Thus, in
`
`the ’949 patent, it is the hardware buffer inside the hardware transport mechanism
`
`that receives data sent from the primary processor. Ex. 2007 at ¶70.
`
`
`
`For at least these reasons, the term “hardware buffer” should be interpreted to
`
`mean “a buffer within a hardware transport mechanism that receives data sent from
`
`the primary processor to the secondary processor.”
`
`D.
`Scatter Loader Controller
`Claims 1-9 of the ’949 patent require a “scatter loader controller.” This term
`
`
`
`should be interpreted to mean “a component of a hardware transport mechanism that
`
`scatter loads data received from the primary processor directly into the system
`
`memory of the secondary processor.” Ex. 2007 at ¶72. This interpretation is
`
`consistent with the plain and ordinary meaning of the term as understood by the
`
`POSA, and support for this interpretation is found in the ’949 patent. Id. at ¶¶72-75.
`
`
`
`15
`
`

`

`
`
`In the ’949 patent, the scatter loader controller receives software image data
`
`from the primary processor via a physical data pipe such as a HS-USB cable. Id.
`
`at ¶73. These components and their interconnections are shown in Fig. 3, and the
`
`patent discloses that “[s]econdary processor 302 includes a hardware transport
`
`mechanism 309 (e.g. a USB controller) that includes a scatter loader controller 304.
`
`In the second stage of the loading process, the boot loader programs the inter-chip
`
`connection controller’s engine to receive incoming data and scatter load it into the
`
`secondary processor’s corresponding target memory regions 305 according to the
`
`header information received in the first stage.” Ex. 1001 at 8:60-67. In Fig. 3, the
`
`arrow denoting data movement goes directly from controller 304 within hardware
`
`transport mechanism 309 to system memory 305. Ex. 2007 at ¶73. As this
`
`disclosure shows, the scatter loader controller is a component within the hardware
`
`transport mechanism that receives data from the primary processor via an inter-chip
`
`communication mechanism and scatter loads the received data into the system
`
`memory of the secondary processor. Id. at ¶73.
`
`
`
`For at least these reasons, the term “scatter loader controller” should be
`
`interpreted to mean “a component of a hardware transport mechanism that scatter
`
`loads data received from the primary processor directly into the system memory of
`
`the secondary processor.”
`
`
`
`16
`
`

`

`E. Means-Plus-Function Limitations
`Independent claim 16 recites the following means-plus-function limitations:
`
`
`
`means for processing, by the secondary processor, the image header to
`determine at least one location within system memory to which the
`secondary processor is coupled to store each data segment;
`
`means for scatter loading, by the secondary processor, each data
`segment directly to the determined at least one location within the
`system memory, and each data segment being scatter loaded based at
`least in part on the processed image header.
`
`Ex. 1001 at 14:26-29, 14:33-37.
`
`
`
`Petitioner attempted to construe these terms in its Petition filed in IPR2018-
`
`01335 (Paper 3 at 17-22), and the Board stated that it has “questions as to the
`
`sufficiency of Petitioner’s identified structures.” Paper 10 (IPR2018-01335) at 13.
`
`
`
`In any event, these terms do not need to be construed in order for the Board
`
`to reach its Final Written Decision. None of the arguments Qualcomm makes below
`
`to distinguish the prior art requires construction of these limitations. The Board has
`
`stated that “[o]nly terms which are in controversy need to be construed, and then
`
`only to the extent necessary to resolve the controversy and material to the decision.”
`
`Facebook, Inc. v. Sound View Innovations, LLC, IPR2017-01005, Paper 13 at 6
`
`(PTAB Sept. 1, 2017) (citing Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d
`
`795, 803 (Fed. Cir. 1999)). The Board routinely declines to construe terms when it
`
`is unnecessary for reaching its final written decision. See, e.g., Unified Patents Inc.
`
`v. First-Class Monitoring, LLC, IPR2017-01932, Paper 23 at 8 (PTAB Mar. 13,
`
`
`
`17
`
`

`

`2019) (citing Vivid Techs. and declining to construe terms when constructions are
`
`unnecessary to resolve any issues in final written decision).
`
`
`
`To the extent the Board decides to construe the means-plus-function
`
`limitations reproduced above, the claimed function and corresponding structure in
`
`the specification of the ’949 patent for the respective limitations are as follows.
`
`1.
`
`“means for processing, by the secondary processor, the
`image header to determine at least one location within
`system memory to which the secondary processor is coupled
`to store each data segment”
`The function of the above limitation, as recited in claim 16, is processing, by
`
`
`
`the secondary processor, the image header to determine at least one location within
`
`system memory to which the secondary processor is coupled to store each data
`
`segment. Ex. 2007 at ¶79.
`
`
`
`The corresponding structure identified in the specification is a modem
`
`processor coupled to a system memory, as described in the ’949 patent at 3:9-12,
`
`4:58-5:43, 5:59-6:39, 7:60-10:44, 8:50-56, and 9:27-41, and as shown in Figs. 1-3.
`
`Ex. 2007 at ¶¶80-82. More specifically, the ’949 patent discloses that “[k]nowing
`
`the size of the segment and the destination address allows the software to program
`
`the scatter loader controller 304 of the secondary processor 302 for the transfer of
`
`the entire segment directly into the target memory location (within system memory
`
`305) with minimum software intervention by the secondary processor 302.”
`
`Ex. 1001 at 9:3-9. The ’949 patent also discloses that the “image header provides
`
`
`
`18
`
`

`

`information as to where the data segments are to be located in the system
`
`memory 305. The scatter loader controller 304 accordingly transfers the image
`
`segments directly into their respective target locations in the secondary processor’s
`
`system memory 305. That is, once the secondary processor’s CPU processes the
`
`image header in its memory 305 and programs the scatter loader controller 304, the
`
`scatter loader controller 304 knows exactly where the image segments need to go
`
`within the secondary processor’s memory 305, and thus the hardware scatter loader
`
`controller 304 is then programmed accordingly to transfer the data segments directly
`
`into their target destinations.” Id. at 9:23-37 (emphasis added).
`
`
`
`As shown by the passages quoted above, the ’949 patent discloses that the
`
`CPU of the secondary processor 302 processes the image header in system
`
`memory 305 to determine where to place the image segments within the secondary
`
`processor’s system memory 305. Ex. 2007 at ¶¶80-81. The CPU uses this
`
`information to program the scatter loader controller to transfer the data segments
`
`directly into their target destinations in the system memory 305. Id. at ¶81. The
`
`structure for the claimed “means for processing …” is therefore a modem processor
`
`coupled to a system memory, as described in the ’949 patent, with the CPU of the
`
`modem processor processing the image header to determine at least one location
`
`within system memory to store each data segment