`Filed on behalf of Intel Corporation
`By:
`David L. Cavanaugh, Reg. No. 36,476 (David.Cavanaugh@wilmerhale.com)
`Thomas E. Anderson, Reg. No. 37,063 (Tom.Anderson@wilmerhale.com)
`Joseph H. Haag, Reg. No. 42,612 (Joseph.Haag@wilmerhale.com)
`Wilmer Cutler Pickering Hale and Dorr LLP
`1875 Pennsylvania Avenue, N.W.
`Washington, DC 20006
`Tel: (202) 663-6000
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
`Intel Corporation
`Petitioner
`
`v.
`
`QUALCOMM INCORPORATED
`Patent Owner
`
`
`
`Trial No. IPR2018-013341
`U.S. Patent No. 8,838,949
`
`
`
`PETITIONER’S DEMONSTRATIVE EXHIBITS
`
`
`
`
`
`
`1 IPR2018-01335 and IPR2018-01336 have been consolidated with the instant
`proceeding.
`
`
`
`1
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`STRATIVEEXHIBIT–NOTEV
`
`December 12, 2019
`
`Inter Partes Review w of U.S. Patent No. 8,838,949
`
`Petitioner’s Demonstrative Exhibits
`
`(Consolidated with IPR20188-8-01335, 5-, -01336)
`
`Case No: IPR20188-8-01334
`
`Qualcomm Incorporated, Patent Owner
`
`Intel Corporation, Petitioner,
`
`v.
`
`Before the Patent Trial and Appeal Board
`United States Patent and Trademark Office
`
`
`
`
`
`22
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`(cid:131)Disputed Issues
`
`(cid:131)Summary of the Proceeding
`
`(cid:131)Obviousness of the Challenged Claims
`
`(cid:131)Overview of the Prior Art
`(cid:131)Overview of the ʼ949 Patent
`
`Overview
`
`
`
`
`
`33
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`(cid:131)Disputed Issues
`
`(cid:131)Summary of the Proceeding
`
`(cid:131)Obviousness of the Challenged Claims
`
`(cid:131)Overview of the Prior Art
`(cid:131)Overview of the ʼ949 Patent
`
`Overview
`
`
`
`
`
`44
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Ex. 1001 (’949 Patent); -01334 Pet. at 9-15; Ex. 1002 (Lin Decl.) ¶¶ 53-59.
`
`’949 Patent
`
`
`
`
`
`55
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Ex. 1001 (’949 Patent) at Claim 1 (highlighting and annotations added); -01334 Pet. at 25-52; Ex. 1002 (Lin Decl.) ¶¶ 107-155.
`
`& Secondary Processor
`Interface Between Primary
`
`with Memory
`Primary Processor
`
`Scatter Loader Controller
`
`segment received separately
`Image header and each data
`Hardware Buffer
`System Memory &
`Secondary Processor
`
`Claim 1
`’949 Patent:
`
`
`
`
`
`66
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`-01334 Pet. at 12; Ex. 1002 (Lin Decl.) ¶¶ 59-67; Ex. 1001 (’949 Patent) at Fig. 3 (highlighting and annotations added).
`
`Segment 3
`
`Data
`
`Segment 2
`
`Data
`
`Segment 1
`
`Data
`
`Header
`Image
`
`Segment
`Partial Data
`
`Segment 3
`
`Data
`
`Segment 2
`
`Data
`
`Segment 1
`
`Data
`Header
`Image
`
`Segment
`Partial Data
`
`Figure 3
`’949 Patent Alleged Invention:
`
`
`
`
`
`77
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`-01334 Pet.; -01335 Pet.; -01336 Pet.
`
`(cid:131)Dependent claims 2-9, 11-15, 17, 19, 21, 23
`
`configuration parameters, which are not in dispute
`system and a second non-volatile memory storing
`
`(cid:131)Claims 18 and 20 add well-known features such as a file
`(cid:131)Claim 16 uses “means for” terms
`
`system memory
`segment and scatter loading each received data segment into
`
`(cid:131)All recite separately receiving an image header and a data
`
`(cid:131)Independent claims include multi-processor system (claims 1,
`
`18, 20), method (claim 10, 22), and apparatus (claim 16)
`
`(cid:131)Independent claims 1, 10, 16, 18, 20, and 22
`
`Challenged Claims
`’949 Patent:
`
`
`
`
`
`88
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`(cid:131)Disputed Issues
`
`(cid:131)Summary of the Proceeding
`
`(cid:131)Obviousness of the Challenged Claims
`
`(cid:131)Overview of the Prior Art
`(cid:131)Overview of the ʼ949 Patent
`
`Overview
`
`
`
`
`
`99
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Ex. 1010 (Svensson); -01334 Pet. at 17-19.
`
`U.S. 7,356,680 (“Svensson”)
`
`
`
`10
`10
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Ex. 1010 (Svensson) at Fig. 1 (highlighting and annotations added); -01334 Pet. at 17-19, 25-27, 50-52.
`
`System Memory
`
`Buffer
`Hardware
`
`Processor
`Secondary
`
`Interface
`
`Processor
`Primary
`
`Memory
`
`Hardware Buffer & System Memory
`Svensson: Primary & Secondary Processors,
`
`
`
`11
`11
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Ex. 1010 (Svensson) at Fig. 3 (highlighting added); -01334 Pet. at 19.
`
`Header with Destination Address
`Svensson:
`
`
`
`12
`12
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Ex. 1009 (Bauer); -01334 Pet. at 19-21.
`
`U.S. 2006/0288019 (“Bauer”)
`
`
`
`13
`13
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Ex. 1010 (Svensson); Ex. 1009 (Bauer); -01334 Pet. at 19-21, 23-24.
`
`Ex. 1009 (Bauer) at Fig. 2.
`
`Ex. 1010 (Svensson) at Fig. 1.
`
`Same Multi-Processor System as Svensson
`Bauer:
`
`
`
`14
`14
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Ex. 1009 (Bauer); -01334 Pet. at 19-21; Ex. 1009 (Lin Decl.) ¶¶ 27-34, 88-90.
`
`Ex. 1009 (Bauer) at Figs. 1A-1C (highlighting added).
`
`(highlighting added).
`Ex. 1010 (Svensson) at Fig. 3
`
`that Used in Svensson
`Bauer: Improved Header and File Format Over
`
`
`
`15
`15
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Ex. 1009 (Bauer) at ¶31(highlighting added); -01334 Pet. at 20, 24, 32-33.
`
`Loader Using Bauer’s File Format
`Bauer: Cites to Svensson for Example of Program
`
`
`
`16
`16
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Ex. 1011, 1012 (Kim); -01334 Pet. at 21-22; Ex. 1002 (Lin Decl.) ¶¶ 91-93.
`
`.
`.
`.
`.
`
`K.R. 10-2002-0036354 (“Kim”)
`
`
`
`17
`17
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Block
`Request Program
`
`R
`
`P
`
`Ex. 1011, 1012 (Kim) at Fig. 3 (highlights and annotations added); -01334 Pet. at 21-22, 40-42.
`
`Receive Header
`
`Request Header
`
`Processor
`Secondary
`
`Block
`Transmit Program
`Proogggggggggggrraamm
`
`Transmit Header
`
`Processor
`Primary
`
`Separately from Program Block
`Kim: Secondary Processor Receives Header
`
`
`
`18
`18
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`(cid:131)Disputed Issues
`
`(cid:131)Summary of the Proceeding
`
`(cid:131)Obviousness of the Challenged Claims
`(cid:131)Overview of the Prior Art
`(cid:131)Overview of the ʼ949 Patent
`
`Overview
`
`
`
`19
`19
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`-01334 Pet. at 23-52; Ex. 1002 (Lin Decl.) ¶¶ 101-155.
`01334Pt
`t2352E1002(LiDl)¶¶101155
`
`Svensson
`
`Bauer
`
`+
`
`Svensson
`
`Bauer
`
`+
`
`Svensson
`
`Bauer
`
`+
`
`(and alternatively Kim)
`(and
`
`Svensson
`
`Bauer
`
`+
`
`Svensson
`
`Bauer
`
`+
`
`secondary processor via the interface.
`secondary processor, the executable software image being received by the
`
`[1f] an interface communicatively coupling the primary processor and the
`
`[1e] a primary processor coupled with a memory, the memory storing the
`
`executable software image for the secondary processor; and
`
`system memory;
`on the loaded image header, directly from the hardware buffer to the
`and to scatter load each received data segment based at least in part
`
`[1d] a scatter loader controller configured: to load the image header;
`
`[1c] the image header and each data segment being received separately, and
`
`software image,
`for receiving an image header and at least one data segment of an executable
`
`[1b]a secondary processor comprising: system memory and a hardware buffer
`
`[1a].A multi-processor system comprising:
`
`Claim 1
`alternatively with Kim)
`Claim 1 is Obvious Over Bauer and Svensson (and
`
`Svensson
`
`+
`
`Bauer
`Discloses?
`
`
`
`20
`20
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`-01334 Pet. at 25-52; Ex. 1002 (Lin Decl.) ¶¶ 151-155; see generally POR; Ex. 2007 (Rinard).
`
`via the interface.
`processor, the executable software image being received by the secondary processor
`
`[1f]an interface communicatively coupling the primary processor and the secondary
`
`[1e] a primary processor coupled with a memory, the memory storing the executable
`[1b] a secondary processor comprising: system memory …
`
`software image for the secondary processor; and
`
`Discloses?
`
`(highlighting and annotations added).
`Ex. 1010 (Svensson) at Fig. 1
`
`System Memory
`
`[1a]. A multi-processor system comprising:
`
`Claim 1
`
`Processor
`Secondary
`
`Interface
`
`Processor
`Primary
`
`teach the below limitations
`that Bauer and Svensson
`Dr. Rinard do not dispute
`Patent Owner and its expert
`
`(cid:131)
`
`Memory
`
`alternatively with Kim)
`Claim 1 is Obvious Over Bauer and Svensson (and
`
`
`
`21
`21
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`(cid:131)Disputed Issues
`
`(cid:131)Summary of the Proceeding
`(cid:131)Obviousness of the Challenged Claims
`
`(cid:131)Overview of the Prior Art
`(cid:131)Overview of the ʼ949 Patent
`
`Overview
`
`
`
`22
`22
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`-01334 DI; -01335 DI; -01336 DI; see generally POR.
`
`(cid:131)Whether Dependent Claims 2 and 12 Are Obvious
`(cid:131)Disclosure of “Scatter Loader Controller” in Combination of Bauer And Svensson
`
`(cid:131)Disclosure of Secondary Processor Receiving the Image Header and Each Data Segment
`(cid:131)Disclosure of “Scatter Loading” in Combination of Bauer And Svensson
`
`Separately in Combination of Bauer and Svensson (and alternatively with Kim)
`
`(cid:131)Disclosure of “System Memory” and “Hardware Buffer” in Combination of Bauer And
`
`Svensson
`
`Loader
`Bauer’s File Format to a System Memory of a Secondary Processor Using Svensson’s Program
`
`(cid:131)Motivation To Combine Bauer And Svensson --Obviousness of Transferring an Image in
`(cid:131)Claim Construction
`
`(cid:131)Patent Owner contests the challenged claims based on the following:
`
`IPR2018-01334, -01335, -01336 into a single proceeding: IPR2018-01334
`(cid:131)The Board instituted trial on all grounds and all claims and consolidated
`
`Summary of the Proceeding
`
`
`
`23
`23
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`(cid:131)Disputed Issues
`(cid:131)Summary of the Proceeding
`
`(cid:131)Obviousness of the Challenged Claims
`
`(cid:131)Overview of the Prior Art
`(cid:131)Overview of the ʼ949 Patent
`
`Overview
`
`
`
`24
`24
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`6.Bauer And Svensson Alone or with Kim Teach Separate Receipt of the Image
`
`Header from Each Data Segment
`
`5.Bauer and Svensson Disclose “Scatter Loading”
`
`4.Bauer and Svensson Disclose a “System Memory” and a “Hardware Buffer”
`
`(cid:131)“Scatter Loader Controller”
`(cid:131)“Image Header”
`(cid:131)“Hardware Buffer”
`(cid:131)“System Memory”
`
`3.Claim Construction
`
`Svensson’sProgram Loader
`It Would Be Obvious to Transfer an Image in Bauer’s File Format Using
`
`2.
`
`1.Motivation to Combine Bauer and Svensson
`
`Issues Raised By Patent Owner
`Overview:
`
`
`
`25
`25
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`-01334 Pet. at 23-25; Reply Br. at 19-21; Ex. 1002 (Lin Decl.) ¶¶ 101-106.
`
`Ex. 1009 (Bauer) at Fig. 2.
`
`Ex. 1010 (Svensson) at Fig. 1.
`
`(cid:131)Bauer and Svensson are closely interrelated:
`
`Motivated To Combine Bauer And Svensson
`A POSITA Would Have Been
`
`
`
`26
`26
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Reply Br. at 20-21; Ex. 1022 (Rinard Dep.) at 177:3-12 (emphasis added).
`
`A.Yes.
`
`Q.And you think that’s an accurate statement, correct?
`
`art, “would be motivated to combine Bauer and Svensson.”
`conceivable that the POSA,” a person of ordinary skill in the
`A.Okay. Here I’m on Paragraph 107 [of my report], and I say “it is
`
`would combine the teachings of Bauer and Svensson?
`
`Q.Do you agree with me that a person of ordinary skill in the art
`
`Patent Owner’s Expert
`Dr. Martin Rinard
`
`been obvious to combine Bauer and Svensson:
`Patent Owner’s own expert Dr. Rinard admits it would have
`
`(cid:131)
`
`Motivated To Combine Bauer And Svensson
`A POSITA Would Have Been
`
`
`
`27
`27
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Ex. 1009 (Bauer) at ¶31(highlighting added); -01334 Pet. at 20, 24, 32-33; Reply Br. at 19-20; Ex. 1002 (Lin Decl.) ¶¶ 101-106, 120-122.
`
`(cid:131)Bauer explicitly states that its file format can be used with
`
`Svensson’s program loader:
`
`Motivated To Combine Bauer And Svensson
`A POSITA Would Have Been
`
`
`
`28
`28
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`-01334 Pet. at 23-25, 31-36; Reply Br. at 19-21; Ex. 1002 (Lin Decl.) ¶¶ 101-106, 120-128.
`
`(highlighting added).
`Ex. 1009 (Bauer) at Figs. 1A-1C
`
`(highlighting added).
`Ex. 1010 (Svensson) at Fig. 3
`
`Svensson as expressly instructed by the references:
`
`(cid:131)Obvious to combine file format of Bauer with related system of
`
`Motivated To Combine Bauer And Svensson
`A POSITA Would Have Been
`
`
`
`29
`29
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`6.Bauer And Svensson Alone or with Kim Teach Separate Receipt of the Image
`
`Header from Each Data Segment
`
`5.Bauer and Svensson Disclose “Scatter Loading”
`
`4.Bauer and Svensson Disclose a “System Memory” and a “Hardware Buffer”
`
`(cid:131)“Scatter Loader Controller”
`(cid:131)“Image Header”
`(cid:131)“Hardware Buffer”
`(cid:131)“System Memory”
`
`3.Claim Construction
`
`2.It Would Be Obvious to Transfer an Image in Bauer’s File Format
`
`Using Svensson’sProgram Loader
`
`1.Motivation to Combine Bauer and Svensson
`
`Issues Raised By Patent Owner
`Overview:
`
`
`
`30
`30
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Ex. 1009 (Bauer) at ¶31(highlighting added); -01334 Pet. at 20, 24, 32-33; Reply Br. at 23-24.
`
`Bauer’s file format when loading an image for execution:
`
`(cid:131)Bauer explicitly instructs to use Svensson’s program loader with
`
`Svensson’s Program Loader
`Obvious to Use Bauer’s File Format with
`
`
`
`31
`31
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Reply Br. at 24-25; Ex. 1022 (Rinard Dep.) at 127:16-128:2; -01334 Pet. at 33, 45-46.
`
`Ex. 1009 (Bauer) at Fig. 2 (highlighting added).
`
`Ex. 1009 (Bauer) at ¶36(highlighting added).
`
`used in any one or more of the memories in Figure 2:
`
`(cid:131)Bauer sets forth that its file format from Figures 1A-1C can be
`
`Svensson’s Program Loader
`Obvious to Use Bauer’s File Format with
`
`
`
`32
`32
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Ex. 1009 (Bauer) at Fig. 2 (highlighting added).
`
`Reply Br. at 25-26.
`
`Ex. 1022 (Rinard Dep.) at 127:16-128:2 (emphasis added)
`
`format.
`these memories can store information in that
`can store information in memories. Any of
`disclose a method of storing information. You
`
`A.Yeah. I mean, this is a –Figures 1A to 1C
`
`format of Figures 1A to 1C of Bauer, correct?
`Figure 2 of Bauer can store an image in the file
`Q.Okay. So any of memories 206, 208 and 210 in
`
`Patent Owner’s Expert
`Dr. Martin Rinard
`
`format can be stored in any of memories 206, 208, 210:
`Patent Owner’s own expert Dr. Rinard admits Bauer’s file
`
`(cid:131)
`
`Svensson’s Program Loader
`Obvious to Use Bauer’s File Format with
`
`
`
`33
`33
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Ex. 1009 (Bauer) at ¶43 (highlights added), Figs. 1A-1C; Reply Br. at 19, 26; -01334 Pet. at 19-20, 32, 35, 44.
`
`(cid:131)Bauer teaches that its approach “simplifies optimization” and
`
`“makes memory loading efficient”:
`
`Svensson’s Program Loader
`Obvious to Use Bauer’s File Format with
`
`
`
`34
`34
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Ex. 1009 (Bauer) at ¶30 (highlights added), Figs. 1A-1C; Reply Br. at 27-29; -01334 Pet. at 46.
`
`reading any of the data segments:
`will “retrieve” header 102 and section information 104 before
`(cid:131)Bauer explains that its file format can be used so that a loader
`
`Svensson’s Program Loader
`Obvious to Use Bauer’s File Format with
`
`
`
`35
`35
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`6.Bauer And Svensson Alone or with Kim Teach Separate Receipt of the Image
`
`Header from Each Data Segment
`
`5.Bauer and Svensson Disclose “Scatter Loading”
`
`4.Bauer and Svensson Disclose a “System Memory” and a “Hardware Buffer”
`
`(cid:131)“Scatter Loader Controller”
`(cid:131)“Image Header”
`(cid:131)“Hardware Buffer”
`(cid:131)“System Memory”
`3.Claim Construction
`
`Svensson’s Program Loader
`It Would Be Obvious to Transfer an Image in Bauer’s File Format Using
`
`2.
`
`1.Motivation to Combine Bauer and Svensson
`
`Issues Raised By Patent Owner
`Overview:
`
`
`
`36
`36
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`POR at 9-12; 1334 DI at 8; Reply Br. at 3, 6.
`
`executable software image can be loaded and executed”
`
`(cid:131)No construction necessary or “memory where an
`
`(cid:131)Petitioner (reply):
`
`“memory that is addressable by the secondary processor”
`
`(cid:131)
`
`(cid:131)Patent Owner’s construction should be rejected:
`
`(cid:131)Petitioner (in petitions) & Board’s Institution Decision:
`
`(cid:131)No construction necessary
`
`“System Memory”
`Claim Construction:
`
`
`
`37
`37
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`(emphasis added).
`Reply Br. at 5; Ex. 1023 (Lin Reply Decl.) ¶12; Ex. 1022 (Rinard Dep.) at 61:9-14 (emphasis added); Ex. 2001 (Lin Dep.) at 25:6-12
`
`A.So a system memory would be a portion of the memory
`
`where programs could be loaded and executed. …
`
`…
`
`system for execution by a processor to be a system memory?
`
`Q.Would you consider a memory that stores an operating
`
`Petitioner’s expert
`Dr. Bill Lin
`
`p
`
`A.That’s one of the things that system memory does, that
`
`you can do with system memory. It’s not the only thing.
`
`Q.Do you agree with Dr. Lin that system memory is memory
`
`processor?
`where programs can be loaded and executed by a
`
`Patent Owner’s Expert
`Dr. Martin Rinard
`
`p
`
`executable software image can be “loaded and executed”:
`
`(cid:131)Both parties’ experts agree that a “system memory” is where an
`
`“System Memory”
`Claim Construction:
`
`
`
`38
`38
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Reply Br. at 5-6; Ex. 1001 (‘949 patent) at 2:61-63, 8:18-21, 9:37-41 (highlighting added); Ex. 1023 (Lin Reply Decl.) ¶13.
`
`where programs are loaded and executed:
`’949 specification describes “system memory” as memory
`
`(cid:131)
`
`“System Memory”
`Claim Construction:
`
`
`
`39
`39
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Reply Br. at 8-11; -1334 DI at 8.
`
`secondary processor”
`receives data sent from the primary processor to the
`“a buffer within a hardware transport mechanism that
`
`(cid:131)
`
`(cid:131)Patent Owner’s construction should be rejected:
`
`(cid:131)No construction necessary
`
`(cid:131)Petitioner and Board’s Institution Decision:
`
`“Hardware Buffer”
`Claim Construction:
`
`
`
`40
`40
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Reply Br. at 9; Ex. 1001 (‘949 patent) at claim 1(highlighting added).
`
`mechanism”:
`and without even mentioning a “hardware transport
`requiring it to exist in any specific place within that processor,
`buffer” to be part of the “secondary processor”—without
`(cid:131)Claim 1 of the ‘949 patent merely requires the “hardware
`
`“Hardware Buffer”
`Claim Construction:
`
`
`
`41
`41
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Reply Br. at 9-10; Ex. 1001 (‘949 patent) at 2:58-61, 9:37-41(highlighting added).
`
`“hardware transport mechanism”:
`of the “secondary processor”—without mentioning a
`twice, merely to require the “hardware buffer” to be part
`‘949 specification uses the term “hardware buffer” only
`
`(cid:131)
`
`“Hardware Buffer”
`Claim Construction:
`
`
`
`42
`42
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Reply Br. at 10; Ex. 1001 (‘949 patent) at 7:60-63(highlighting added).
`
`that specific embodiment:
`merely “exemplary” and there is no reason to limit the claim to
`Patent Owner’s reliance on Figure 3 is improper, given that it is
`
`(cid:131)
`
`“Hardware Buffer”
`Claim Construction:
`
`
`
`43
`43
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Reply Br. at 8; -1334 DI at 8; -1335 DI at 8; -1336 DI at 8.
`
`under Board’s initial construction, which is broader
`(cid:131)Claims invalid under agreed construction and also
`
`of the at least one data segment in the system memory”
`information that can be used to determine the placement
`“the image header is perhaps better described as having
`
`(cid:131)
`
`(cid:131)Board’s initial construction:
`
`system memory”
`where the data segments are to be placed in the
`“header associated with the entire image that specifies
`
`(cid:131)
`
`(cid:131)Parties’ agreed construction:
`
`“Image Header”
`Claim Construction:
`
`
`
`44
`44
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Reply Br. at 11-13; -1334 DI at 8.
`
`processor”
`directly into the system memory of the secondary
`scatter loads data received from the primary processor
`“a component of a hardware transport mechanism that
`
`(cid:131)
`
`(cid:131)Patent Owner’s construction should be rejected:
`
`(cid:131)No construction necessary
`
`(cid:131)Petitioner and Board’s Institution Decision:
`
`“Scatter Loader Controller”
`Claim Construction:
`
`
`
`45
`45
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Reply Br. at 11-13; Ex. 1023 (Lin Reply Decl.) ¶¶28-29; Ex. 1001 (‘949 patent) at claim 1.
`
`comprising … a scatter loader controller”)
`Ex. 1001 (‘949 patent) at claim 1 (“a secondary processor
`
`(cid:131)
`
`requiring it to exist in any specific place
`to be part of the “secondary processor”—without
`
`(cid:131)Claim 1 merely requires the “scatter loader controller”
`
`that it reside in a “hardware transport mechanism”
`plain meaning of a “scatter loader controller” requires
`
`(cid:131)No evidence a POSITA would have understood that the
`
`(cid:131)Patent Owner’s construction should be rejected:
`
`“Scatter Loader Controller”
`Claim Construction:
`
`
`
`46
`46
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Reply Br. at 10, 12; Ex. 1001 (‘949 patent) at 7:60-63(highlighting added).
`
`limit the claim to that specific embodiment:
`that it is merely “exemplary” and there is no reason to
`(cid:131)Patent Owner’s reliance on Figure 3 is improper, given
`
`“Scatter Loader Controller”
`Claim Construction:
`
`
`
`47
`47
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`6.Bauer And Svensson Alone or with Kim Teach Separate Receipt of the Image
`
`Header from Each Data Segment
`
`5.Bauer and Svensson Disclose “Scatter Loading”
`
`4.Bauer and Svensson Disclose a “System Memory” and a
`
`“Hardware Buffer”
`
`(cid:131)“Scatter Loader Controller”
`(cid:131)“Image Header”
`(cid:131)“Hardware Buffer”
`(cid:131)“System Memory”
`
`3.Claim Construction
`
`Svensson’sProgram Loader
`It Would Be Obvious to Transfer an Image in Bauer’s File Format Using
`
`2.
`
`1.Motivation to Combine Bauer and Svensson
`
`Issues Raised By Patent Owner
`Overview:
`
`
`
`48
`48
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Reply Br. at 31-32; -1334 Pet. at 26-27, 46-48; Ex. 1009 (Bauer) at Fig. 2; Ex. 1010 (Svensson) at Fig. 1 (highlights and annotations added).
`
`System Memory
`
`Hardware Buffer
`
`from DSP XRAM 210 (“system memory”):
`intermediate storage area (“hardware buffer”) that is separate
`(cid:131)But Figure 1 of Svensson (and Figure 2 of Bauer) discloses an
`at 52-58.
`“hardware buffer” that is separate from “system memory.” POR
`Patent Owner argues that Bauer and Svensson do not disclose a
`
`(cid:131)
`
`“System Memory” & “Hardware Buffer”
`Combination of Bauer And Svensson discloses
`
`
`
`49
`49
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Reply Br. at 34-36; Ex. 1022 (Rinard Dep.) at 107:1-7, 108:21-109:4 (emphasis added).
`
`A.That's one of the places where it’s described as potentially being able to execute
`
`from, sure.
`
`Q.Do you agree with me that in Svensson the client processor 104 executes code
`
`from the XRAM 110?
`
`A.That, I believe, is the intention of the patent, yes. Although in theory, I suppose it
`
`could, but that's not the intention of the patent.
`
`Q.Am I right that in Svensson the client processor 104 does not execute code
`
`directly from the intermediate storage area?
`
`Patent Owner’s Expert p
`Dr. Martin Rinard
`
`not the intermediate storage area:
`Patent Owner’s expert Dr. Rinard agrees that code is executed from the XRAM 110,
`
`of Bauer/Svensson is not a “system memory” because code is not executed from it
`Under the correct, plain meaning of “system memory,” the intermediate storage area
`
`(cid:131)
`
`(cid:131)
`
`“System Memory” & “Hardware Buffer”
`Combination of Bauer And Svensson discloses
`
`
`
`50
`50
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Reply Br. at 8-11, 47-49; -1334 Pet. at 26-27; POR at 14-15.
`
`(cid:131)Bauer’s and Svensson’sintermediate storage area meets
`
`Patent Owner’s construction
`
`(cid:131)The “hardware transport mechanism” requirement is
`a structure within a “hardware transport mechanism”
`construction of “hardware buffer” as being limited to
`“hardware buffer” also hinge on its proposed
`
`(cid:131)Patent Owner’s arguments for alleging lack of a
`
`rejected for this reason
`incorrect, and Patent Owner’s argument should be
`
`“System Memory” & “Hardware Buffer”
`Combination of Bauer And Svensson discloses
`
`
`
`51
`51
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`6.Bauer And Svensson Alone or with Kim Teach Separate Receipt of the Image
`
`Header from Each Data Segment
`
`5.Bauer and Svensson Disclose “Scatter Loading”
`
`4.Bauer and Svensson Disclose a “System Memory” and a “Hardware Buffer”
`
`(cid:131)“Scatter Loader Controller”
`(cid:131)“Image Header”
`(cid:131)“Hardware Buffer”
`(cid:131)“System Memory”
`
`3.Claim Construction
`
`Svensson’sProgram Loader
`It Would Be Obvious to Transfer an Image in Bauer’s File Format Using
`
`2.
`
`1.Motivation to Combine Bauer and Svensson
`
`Issues Raised By Patent Owner
`Overview:
`
`
`
`52
`52
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Reply Br. at 37-41; -1334 Pet. at 47-48; POR at 60; Ex. 1009 (Bauer) at ¶37 (highlights added).
`
`memory and (2) can be arranged in the image in any suitable order:
`(destination) address specifying where to place the data segment in system
`
`(cid:131)But Bauer teaches that each data segment (1) has its own load
`DSP device’s XRAM (the “system memory”)
`Patent Owner argues that Bauer does not disclose “scatter loading” into the
`
`(cid:131)
`
`Bauer And Svensson Disclose “Scatter Loading”
`
`
`
`53
`53
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Ex. 1001 (‘949 patent), Fig 3 (highlights added).
`ddd)
`
`)Fi3(hihlih
`
`001(‘949
`
`Reply Br. at 40-41; -1334 Pet. at 47-48.
`
`Ex. 1001 (‘949 patent),9:12-15 (highlights added).
`
`Ex. 1001 (‘949 patent),4:36-37 (highlights added).
`
`contiguous or non-contiguous locations:
`segments are scattered when loaded into
`(cid:131)The ‘949 specification recognizes that data
`
`Bauer And Svensson Disclose “Scatter Loading”
`
`
`
`54
`54
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Ex. 1001 (‘949 patent), Fig 3 (highlights added).
`E1001(‘949
`ddd)
`
`)Fi3(hihlih
`
`Reply Br. at 36-37; POR at 56-57.
`
`Ex. 1009 (Bauer), Fig 2 (highlights and annotations added)
`E1009(B
`ddd)
`
`)F2(hhlh
`
`d
`
`Memory
`Memory
`System
`System
`
`Hardware
`Hardware
`
`Buffer
`Buffer
`
`path to the system memory
`components—including controller 304—in the
`
`(cid:131)But Figure 3 of the ‘949 patent has numerous
`
`memory DSP XRAM 210/110
`processor ARM CPU 202/102 and system
`there are other components between primary
`not teach “direct” “scatter loading” because
`
`(cid:131)Patent Owner argues that Bauer/Svensson do
`
`Bauer And Svensson Disclose “Scatter Loading”
`
`
`
`55
`55
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Reply Br. at 41-42; Ex. 1022 (Rinard Dep.) at 36:20-37:5 (emphasis added); -1334 Pet. at 47-48.
`
`prior to the ’949 patent, yes.
`I think the general concept of scatter loading was known
`
`A.
`
`…
`
`Q.Scatter loading image data from one location to another location
`
`was known in the prior art to the ’949 patent, correct?
`
`Patent Owner’s Expert
`Dr. Martin Rinard
`
`loading was known in the prior art to the ‘949 patent:
`(cid:131)Patent Owner’s expert Dr. Rinard admits that scatter
`
`Bauer And Svensson Disclose “Scatter Loading”
`
`
`
`56
`56
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`6.Bauer And Svensson Alone or with Kim Teach Separate Receipt of
`
`the Image Header from Each Data Segment
`
`5.Bauer and Svensson Disclose “Scatter Loading”
`
`4.Bauer and Svensson Disclose a “System Memory” and a “Hardware Buffer”
`
`(cid:131)“Scatter Loader Controller”
`(cid:131)“Image Header”
`(cid:131)“Hardware Buffer”
`(cid:131)“System Memory”
`
`3.Claim Construction
`
`Svensson’sProgram Loader
`It Would Be Obvious to Transfer an Image in Bauer’s File Format Using
`
`2.
`
`1.Motivation to Combine Bauer and Svensson
`
`Issues Raised By Patent Owner
`Overview:
`
`
`
`57
`57
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Reply Br. at 42-43; -01334 Pet. at 37-39; Ex. 1009 (Bauer) at ¶30, Abstract (highlights added).
`
`from—the data segments:
`“image header”) are “retrieved” before—and thus, separately
`
`(cid:131)But Bauer teaches that header 102 and section information 104 (the
`the separate receipt requirement. POR at 61.
`Patent Owner argues that Bauer provides “no details” with respect to
`
`(cid:131)
`
`Each Data Segment Separately
`Bauer Discloses Receiving the Image Header and
`
`
`
`58
`58
`
`DEMONSTRATIVE EXHIBIT –NOT EVIDENCE
`
`Ex-1012 (Kim) at Fig. 3 (highlights and annotations added)
`
`Reply Br. at 45-47; -01334 Pet. at 21-22, 40-42.
`
`Block
`Request Program
`
`tPP
`
`RR
`
`Receive Header
`
`iHd
`
`R
`
`Request Header
`
`Processor
`Secondary
`
`Ex. 1011, 1012 (Kim) at Fig. 3 (highlights and annotations added); -01334 Pet. at 21-22, 40-42.
`
`Block Block
`Transmit Program
`Proogrgrggggggggggamam
`
`Transmit Header
`
`Processor
`Primary
`
`Bauer and Svensson
`would combine it with
`prior art and a POSITA
`already known in the
`Kim teaches what was
`
`the teachings of Svensson. POR at 67-69.
`not be combined with Bauer and Svensson because it would be contrary to
`the image header from the data blocks, but instead argues that Kim would
`Patent Owner never contends that Kim does not teach separate receipt of
`
`(cid:131)
`
`(cid:131)
`
`Each Data Segment Separately
`Kim Discloses Receiving the Image Header and
`
`
`
`
`
`IPR2018-01334
`Petitioner’s Demonstrative Exhibits
`0107131.00568US1
`
`
`
`Respectfully Submitted,
`
`Dated: December 9, 2019
`
`
`
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`
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`
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`
`
`/Thomas E. Anderson/
`Thomas E. Anderson
`Reg. No. 37,063
`Counsel for Petitioner
`
`
`
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`
`
`59
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`
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`IPR2018-01334
`Petitioner’s Demonstrative Exhibits
`0107131.00568US1
`
`CERTIFICATE OF SERVICE
`
`I hereby certify that on December 9, 2019, I caused a true and correct copy of
`
`the foregoing material:
`
`• PETITIONER’S DEMONSTRATIVE EXHIBITS
`
`to be served via electronic mail on the following attorneys of record:
`
`
`David B. Cochran, Reg. No. 39,142 (dcochran@jonesday.com)
`
`Matthew W. Johnson, Reg. No. 59,108 (mwjohnson@jonesday.com)
`
`Joseph M. Sauer, Reg. No. 47,919 (jmsauer@jonesday.com)
`
`Joshua R. Nightingale, Reg. No. 67,865 (jrnightingale@jonesday.com)
`
`David M. Maiorana, Reg. No. 41,449 (dmaiorana@jonesday.com)
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`/Thomas E. Anderson/
`Thomas E. Anderson
`Reg. No. 37,063
`Counsel for Petitioner
`
`60
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