Paper 10
`Trials@uspto.gov
`571-272-7822 Entered: March 18, 2019
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`QUALCOMM INCORPORATED,
`Patent Owner.
`
`____________
`
`Case IPR2018-01335
`Patent 8,838,949 B2
`____________
`
`
`
`
`
`Before TREVOR M. JEFFERSON, DANIEL J. GALLIGAN, and
`AARON W. MOORE, Administrative Patent Judges.
`
`
`GALLIGAN, Administrative Patent Judge.
`
`
`
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`

`

`IPR2018-01335
`Patent 8,838,949 B2
`
`
`I. INTRODUCTION
`
`Intel Corporation (“Petitioner”) filed a Petition requesting inter partes
`
`review of claims 10–17 of U.S. Patent No. 8,838,949 B2 (“the ’949 patent,”
`
`Ex. 1101). Paper 3 (“Pet.”). Qualcomm Incorporated (“Patent Owner”)
`
`filed a Preliminary Response. Paper 7 (“Prelim. Resp.”). Under 37 C.F.R.
`
`§ 42.4(a), we have authority to determine whether to institute review.
`
`The standard for instituting an inter partes review is set forth in
`
`35 U.S.C. § 314(a), which provides that an inter partes review may not be
`
`instituted unless the information presented in the Petition and the
`
`Preliminary Response shows “there is a reasonable likelihood that the
`
`petitioner would prevail with respect to at least 1 of the claims challenged in
`
`the petition.”
`
`After considering the Petition, the Preliminary Response, and
`
`associated evidence, we institute an inter partes review as to all challenged
`
`claims and on all grounds raised in the Petition.
`
`A. Related Matters
`
`As required by 37 C.F.R. § 42.8(b)(2), each party identifies various
`
`judicial or administrative matters that would affect or be affected by a
`
`decision in this proceeding. Pet. 2–3; Paper 4, 2. Among those related
`
`matters are IPR2018-01334 and IPR2018-01336, each of which involves
`
`different claims of the ’949 patent.
`
`B. Real Parties in Interest
`
`Petitioner identifies itself and Apple Inc. as real parties in interest.
`
`Pet. 2.
`
`
`
`2
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`IPR2018-01335
`Patent 8,838,949 B2
`
`
`C. The ’949 Patent and Illustrative Claim
`
`The ’949 patent generally relates to loading software from one
`
`processor to another in a multi-processor system. Ex. 1101, at [57]. One
`
`example disclosed in the ’949 patent involves loading modem image
`
`executable data by first retrieving and processing an image header, which
`
`“includes information used to identify where the modem image executable
`
`data is to be eventually placed into the system memory of the secondary
`
`processor.” Ex. 1101, 8:9–21. Figure 3 of the ’949 patent is reproduced
`
`below.
`
`
`
`3
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`IPR2018-01335
`Patent 8,838,949 B2
`
`Figure 3 shows “operational flow for an exemplary loading process for
`
`loading an executable image from a primary processor to a secondary
`
`processor according to one aspect of the present disclosure.” Ex. 1101,
`
`4:10–13. Referring to various components depicted in Figure 3, the ’949
`
`patent discloses the following:
`
`The header information is used by the secondary processor 302
`to program the scatter loader/direct memory access controller
`304 receive address when receiving the actual executable data.
`Data segments are then sent from system memory 307 to the
`primary hardware transport mechanism 308. The segments are
`then sent from the hardware transport mechanism 308 of the
`primary processor 301 to a hardware transport mechanism 309
`of
`the
`secondary processor 302 over an
`inter-chip
`communication bus 310 (e.g., a HS-USB cable.) The first
`segment transferred may be the image header, which contains
`information used by the secondary processor to locate the data
`segments into target locations in the system memory of the
`secondary processor 305. The image header may include
`information used to determine the target location information for
`the data.
`
`Ex. 1101, 8:21–35.
`
`Challenged claims 10 and 16 are independent and are reproduced
`
`below.
`
`10. A method comprising:
`receiving at a secondary processor, from a primary
`processor via an inter-chip communication bus, an image header
`for an executable software image for the secondary processor
`that is stored in memory coupled to the primary processor, the
`executable software image comprising the image header and at
`least one data segment, the image header and each data segment
`being received separately;
`processing, by the secondary processor, the image header
`to determine at least one location within system memory to
`which the secondary processor is coupled to store each data
`segment;
`
`
`
`4
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`IPR2018-01335
`Patent 8,838,949 B2
`
`
`receiving at the secondary processor, from the primary
`processor via the inter-chip communication bus, each data
`segment; and
`scatter loading, by the secondary processor, each data
`segment [directly1] to the determined at least one location within
`the system memory, and each data segment being scatter loaded
`based at least in part on the processed image header.
`
`16. An apparatus comprising:
`means for receiving at a secondary processor, from a
`primary processor via an inter-chip communication bus, an
`image header for an executable software image for the secondary
`processor that is stored in memory coupled to the primary
`processor, the executable software image comprising the image
`header and at least one data segment, the image header and each
`data segment being received separately;
`means for processing, by the secondary processor, the
`image header to determine at least one location within system
`memory to which the secondary processor is coupled to store
`each data segment;
`means for receiving at the secondary processor, from the
`primary processor via the inter-chip communication bus, each
`data segment; and
`means for scatter loading, by the secondary processor,
`each data segment directly to the determined at least one location
`within the system memory, and each data segment being scatter
`loaded based at least in part on the processed image header.
`
`
`D. References
`
`Petitioner relies upon the following references:
`
`Bauer
`
`US 2006/0288019 A1 Dec. 21, 2006
`
`Ex. 1109
`
`Zhao
`
`US 2007/0140199 A1
`
`June 21, 2007
`
`Ex. 1113
`
`
`1 The issued patent recites “reedy,” which appears to be a printing error.
`The April 30, 2014 claim listing submitted by the applicants during
`prosecution states “directly.”
`
`
`
`5
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`IPR2018-01335
`Patent 8,838,949 B2
`
`
`Svensson
`
`US 7,356,680 B2
`
`Apr. 8, 2008
`
`Ex. 1110
`
`Kim
`
`Korean Publication 10-
`2002-0036354
`
`May 16, 2002
`
`Exs. 1111,
`11122
`
`E. Asserted Grounds of Unpatentability
`
`Petitioner asserts the following two grounds of unpatentability:
`
`(1) claims 10–15 are unpatentable under 35 U.S.C. § 103 as obvious over the
`
`combined teachings of Bauer, Svensson, and Kim (Pet. 29–67); and
`
`(2) claims 16 and 17 are unpatentable under 35 U.S.C. § 103 as obvious over
`
`the combined teachings of Bauer, Svensson, Kim, and Zhao (Pet. 67–77).
`
`
`
`II. ANALYSIS
`
`A. Claim Construction
`
`In an inter partes review for a petition filed before November 13,
`
`2018, a claim in an unexpired patent shall be given its broadest reasonable
`
`construction in light of the specification of the patent in which it appears.
`
`37 C.F.R. § 42.100(b) (2018); see Changes to the Claim Construction
`
`Standard for Interpreting Claims in Trial Proceedings Before the Patent Trial
`
`and Appeal Board, 83 Fed. Reg. 51,340 (Oct. 11, 2018) (amending
`
`37 C.F.R. § 42.100(b) effective November 13, 2018). In applying a broadest
`
`reasonable construction, claim terms generally are given their ordinary and
`
`customary meaning, as would be understood by one of ordinary skill in the
`
`art in the context of the entire disclosure. See In re Translogic Tech., Inc.,
`
`504 F.3d 1249, 1257 (Fed. Cir. 2007). This presumption may be rebutted
`
`when a patentee, acting as a lexicographer, sets forth an alternate definition
`
`
`2 In this Decision, we cite Exhibit 1112, which is the English translation of
`Kim provided by Petitioner.
`
`
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`6
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`IPR2018-01335
`Patent 8,838,949 B2
`
`of a term in the specification with reasonable clarity, deliberateness, and
`
`precision. In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994).
`
`1. Image Header
`
`Petitioner argues the term “image header” means “a header associated
`
`with the entire image that specifies where the data segments are to be placed
`
`in the system memory.” Pet. 17 (citing Ex. 1101, 7:50–52, 8:18–21, 9:23–
`
`24, 10:6, claim 10; Ex. 1108, 3; Ex. 1102 ¶ 77). Patent Owner does not
`
`address Petitioner’s proposed construction, but Petitioner notes that Patent
`
`Owner agreed to this proposed construction in an investigation involving the
`
`’949 patent at the International Trade Commission (“ITC”).3 Pet. 17 (citing
`
`Ex. 1108, 3).
`
`For the purpose of deciding whether to institute inter partes review on
`
`the present record, we need not determine the full scope of this term. See
`
`Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013,
`
`1017 (Fed. Cir. 2017) (only those claim terms in controversy need to be
`
`construed, and only to the extent necessary to resolve the controversy).
`
`Rather, to determine whether Petitioner has made a sufficient unpatentability
`
`showing for purposes of institution, we need only determine whether the
`
`scope of this term encompasses elements found in the prior art.
`
`Nevertheless, to provide guidance to the parties during trial, we note that
`
`Petitioner’s proposed construction is problematic for at least three reasons.
`
`First, this definition does not explain what a “header” itself is or what data
`
`must be present for something to be considered a header, if any at all. The
`
`significance of this issue will become evident in the discussion below
`
`
`3 In re Certain Mobile Elec. Devices and Radio Frequency and Processing
`Components Thereof, Inv. No. 337-TA-1065.
`
`
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`7
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`IPR2018-01335
`Patent 8,838,949 B2
`
`concerning the teachings of the prior art. Second, Petitioner’s proposed
`
`construction recites “data segments,” suggesting that plural data segments
`
`are required, but the claims recite “at least one data segment” and, therefore,
`
`are met by only a single data segment. Third, requiring the image header to
`
`“specif[y] where the data segments are to be placed in the system memory”
`
`appears to narrow the term unduly. Claim 10, for example, recites
`
`“processing . . . the image header to determine at least one location within
`
`system memory to which the secondary processor is coupled to store each
`
`data segment.” The ’949 patent discloses that “[t]he image header includes
`
`information used to identify where the modem image executable data is to
`
`be eventually placed into the system memory of the secondary processor
`
`305.” Ex. 1101, 8:18–21. The ’949 patent further discloses the following:
`
`“In one aspect, the target locations are not predetermined, but rather are
`
`determined by software executing in the secondary processor as part of the
`
`scatter loading process. Information from the image header may be used to
`
`determine the target locations.” Ex. 1101, 8:36–40. The claims and the
`
`specification of the ’949 patent, therefore, contemplate image headers that
`
`provide information used to determine where to load data in memory, even if
`
`the image headers do not “specif[y] where the data segments are to be placed
`
`in the system memory.” Thus, the image header is perhaps better described
`
`as having information that can be used to determine the placement of the at
`
`least one data segment in the system memory.
`
`Based on the foregoing, we are not persuaded Petitioner’s proposed
`
`construction of “image header” is the broadest reasonable interpretation
`
`consistent with the specification of the ’949 patent. Petitioner’s proposed
`
`construction is merely one example of such an image header. See, e.g.,
`
`
`
`8
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`IPR2018-01335
`Patent 8,838,949 B2
`
`Ex. 1101, 7:50–52 (describing “one aspect” in which “[t]he image header
`
`also specifies the destination address of the image in target memory”).
`
`Thus, we do not adopt Petitioner’s proposed construction. For purposes of
`
`this Decision, however, we determine that Petitioner’s proposed construction
`
`falls within the broadest reasonable interpretation of “image header.”
`
`During the trial, the parties are encouraged to address this issue further if
`
`they deem it relevant to the disputed issues.
`
`2. Means-Plus-Function Limitations
`
`A petition for inter partes review must
`
`[p]rovide a statement of the precise relief requested for each
`claim challenged. The statement must identify . . . [h]ow the
`challenged claim is to be construed. Where the claim to be
`construed contains a means-plus-function or step-plus-function
`limitation as permitted under 35 U.S.C. 112(f), the construction
`of the claim must identify the specific portions of the
`specification that describe the structure, material, or acts
`corresponding to each claimed function . . . .
`
`37 C.F.R. § 42.104(b). Construing a means-plus-function limitation
`
`includes two steps: (1) identifying the claimed function, and (2) identifying
`
`the corresponding structure in the specification of the patent that performs
`
`the function. IPCom GmbH & Co. v. HTC Corp., 861 F.3d 1362, 1370 (Fed.
`
`Cir. 2017). Petitioner provides proposed constructions for limitations of
`
`independent claim 16 it contends are means-plus-function limitations, as set
`
`forth in the table below.
`
`
`
`9
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`IPR2018-01335
`Patent 8,838,949 B2
`
`
`Limitation
`
`means for receiving at a secondary
`processor, from a primary processor
`via an inter-chip communication bus,
`an image header for an executable
`software image for the secondary
`processor that is stored in memory
`coupled to the primary processor, the
`executable software image
`comprising the image header and at
`least one data segment, the image
`header and each data segment being
`received separately
`
`Petitioner’s Proposed
`Function and Structure
`Function: receiving at a
`secondary processor, from a
`primary processor via an inter-chip
`communication bus, an image
`header for an executable software
`image for the secondary processor
`that is stored in memory coupled to
`the primary processor
`
`Structure: secondary processor
`(e.g., 110, 210, 302) connected to a
`primary processor (e.g., 104, 204,
`301) via an inter-chip
`communication bus (e.g., 134, 234,
`310) for a USB-based High Speed
`Inter-Chip (HSIC) bus, a MIPI
`High Speed Synchronous Interface
`(HSI) bus, a Secure Digital I/O
`Interface (SDIO) bus, a Universal
`Asynchronous
`Receiver/Transmitter (UART) bus,
`a Serial Peripheral Interface (SPI)
`bus, or an Inter-Integrated Circuit
`(I2C) bus. Pet. 18–19 (citing
`Ex. 1101, 5:35–43, Fig. 3; Ex.
`1107, 17–18; Ex. 1102 ¶ 81).
`
`
`
`10
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`

`IPR2018-01335
`Patent 8,838,949 B2
`
`
`Limitation
`
`means for processing, by the
`secondary processor, the image
`header to determine at least one
`location within system memory to
`which the secondary processor is
`coupled to store each data segment
`
`means for receiving at the secondary
`processor, from the primary
`processor via the inter-chip
`communication bus, each data
`segment
`
`Petitioner’s Proposed
`Function and Structure
`Function: processing, by the
`secondary processor, the image
`header to determine at least one
`location within system memory to
`which the secondary processor is
`coupled to store each data segment
`
`Structure: a modem processor
`coupled to a system memory. Pet.
`19–20 (citing Ex. 1101, 3:9–12,
`4:58–5:43, 5:59–6:39, 7:60–10:44,
`8:50–56, 9:27–41, Figs. 1–3; Ex.
`1108, 4–5; Ex. 1102 ¶ 83).
`Function: receiving at the
`secondary processor, from the
`primary processor via the inter-
`chip communication bus, each data
`segment
`
`Structure: a secondary processor
`(e.g., 110, 210, 302) connected to a
`primary processor (e.g., 104, 204,
`301) via an inter-chip
`communication bus (e.g., 134, 234,
`310) for a USB-based High Speed
`Inter-Chip (HSIC) bus, a MIPI
`High Speed Synchronous Interface
`(HSI) bus, a Secure Digital I/O
`Interface (SDIO) bus, a Universal
`Asynchronous
`Receiver/Transmitter (UART) bus,
`a Serial Peripheral Interface (SPI)
`bus, or an Inter-Integrated Circuit
`(I2C) bus. Pet. 21 (citing Ex. 1101,
`5:35–43, Fig. 3; Ex. 1107, 19; Ex.
`1102 ¶ 85).
`
`
`
`11
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`IPR2018-01335
`Patent 8,838,949 B2
`
`
`Limitation
`
`means for scatter loading, by the
`secondary processor, each data
`segment directly to the determined at
`least one location within the system
`memory, and each data segment
`being scatter loaded based at least in
`part on the processed image header
`
`Petitioner’s Proposed
`Function and Structure
`Function: scatter loading, by the
`secondary processor, each data
`segment directly to the determined
`at least one location within the
`system memory, and each data
`segment being scatter loaded based
`at least in part on the processed
`image header
`
`Structure: a modem processor
`coupled to a system memory. Pet.
`22 (citing Ex. 1101, at [57], 1:24–
`33, 4:10–15, 4:58–5:43, 5:59–6:39,
`7:60–10:44, 8:21–30, 8:62–67,
`9:3–8, 9:16–56, 10:13–18, 10:27–
`32, Figs. 1–3; Ex. 1108, 6; Ex.
`1102 ¶ 87).
`
`Each of the limitations reproduced above recites “means” and further
`
`recites a function, thus creating a presumption that 35 U.S.C. § 112, ¶ 64
`
`applies. See 35 U.S.C. § 112, ¶ 6 (“An element in a claim for a combination
`
`may be expressed as a means or step for performing a specified function
`
`without the recital of structure, material, or acts in support thereof, and such
`
`claim shall be construed to cover the corresponding structure, material, or
`
`acts described in the specification and equivalents thereof.”); see also
`
`Williamson v. Citrix Online, LLC, 792 F.3d 1339, 1349 (Fed. Cir. 2015) (en
`
`banc in relevant part) (quoting Personalized Media Commc’ns, LLC v. Int’l
`
`
`4 Section 4(c) of the Leahy-Smith America Invents Act, Pub. L. No. 112-29,
`125 Stat. 284 (2011) (“AIA”), re-designated 35 U.S.C. § 112, ¶ 6 as
`35 U.S.C. § 112(f). Because the ’949 patent has a filing date prior to
`September 16, 2012, the effective date of § 4(c) of the AIA, we refer to the
`pre-AIA version of 35 U.S.C. § 112. See AIA § 4(e).
`
`
`
`12
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`IPR2018-01335
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`Trade Comm’n, 161 F.3d 696, 703 (Fed. Cir. 1998)) (holding that “use of
`
`the word ‘means’ creates a presumption that § 112, ¶ 6 applies”).
`
`We agree with Petitioner that these limitations are means-plus-
`
`function limitations subject to 35 U.S.C. § 112, ¶ 6. As for the first step in
`
`construing these means-plus-function limitations, we agree with Petitioner’s
`
`identification of the claimed functions. As for the second step, however, we
`
`have questions as to the sufficiency of Petitioner’s identified structures.
`
`Petitioner identifies “a modem processor coupled to a system memory” as
`
`the structure corresponding to the “means for processing . . . an image
`
`header” and the “means for scatter loading” limitations. Pet. 19, 22. The
`
`portions of the specification of the ’949 patent cited by Petitioner for the
`
`“means for processing . . . an image header” limitation do not appear to
`
`provide sufficient structure to perform the recited function. The first cited
`
`passage merely restates the function, and the second two passages do not
`
`even mention an “image header.” Ex. 1101, 3:9–12, 4:58–5:43, 5:59–6:39.
`
`Furthermore, claim 16 recites “means for processing, by the secondary
`
`processor” (emphasis added). The passage cited at column 8, lines 50
`
`through 56 states that the primary processor parses the image header. This
`
`disclosure, therefore, does not correspond to the claimed “means for
`
`processing, by the secondary processor.” The last cited passage (col. 9,
`
`ll. 27–41) states that the image header is processed but not how that
`
`processing is accomplished. Merely disclosing “a black box that performs a
`
`recited function” without disclosing “how it does so” is not sufficient.
`
`Blackboard, Inc. v. Desire2Learn, Inc., 574 F.3d 1371, 1383 (Fed. Cir.
`
`2009). Petitioner also cites a passage of almost three columns from the
`
`patent (col. 7, l. 60 – col. 10, l. 44), but Petitioner does not explain how this
`
`
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`discloses structure that performs the recited function, and we do not see
`
`sufficient disclosure in this section. See Pet. 19–20.
`
`As to the “means for scatter loading” limitation, the specification of
`
`the ’949 patent appears to identify scatter loader controller 304 as
`
`responsible for performing scatter loading.
`
`The image header is loaded from the primary processor
`301 to scatter loader controller 304 of secondary processor 302.
`That image header provides information as to where the data
`segments are to be located in the system memory 305. The
`scatter loader controller 304 accordingly transfers the image
`segments directly into their respective target locations in the
`secondary processor’s system memory 305. That is, once the
`secondary processor’s CPU processes the image header in its
`memory 305 and programs the scatter loader controller 304, the
`scatter loader controller 304 knows exactly where the image
`segments need to go within the secondary processor’s system
`memory 305, and thus the hardware scatter loader controller 304
`is then programmed accordingly to transfer the data segments
`directly into their target destinations. In the example of FIG. 3,
`the scatter loader controller 304 receives the image segments and
`scatters them to different locations in the system memory 305.
`In one aspect, the executable software image is loaded into the
`system memory of the secondary processor without an entire
`executable software image being stored in the hardware buffer of
`the secondary processor.
`
`Ex. 1101, 9:21–41 (emphasis added). This passage states that the secondary
`
`processor’s CPU programs the scatter loader, but it does not disclose how
`
`scatter loader controller 304 is programmed to perform the recited function
`
`of scatter loading. See Blackboard, 574 F.3d at 1383 (“The ACM is
`
`essentially a black box that performs a recited function. But how it does so
`
`is left undisclosed.”); ePlus, Inc. v. Lawson Software, Inc., 700 F.3d 509,
`
`518 (Fed. Cir. 2012) (holding that “black box” labeled “Purchase Orders”
`
`was insufficient structure to perform the “generate purchase orders”
`
`
`
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`function); Noah Sys., Inc. v. Intuit Inc., 675 F.3d 1302, 1317 (Fed. Cir.
`
`2012) (“[T]he disclosure must identify the method for performing the
`
`function, whether or not a skilled artisan might otherwise be able to glean
`
`such a method from other sources or from his own understanding.”).
`
`For purposes of determining whether to institute, we need not
`
`construe expressly these means-plus-function limitations because we
`
`determine that Petitioner has met the threshold for institution as to claims
`
`10–15, as discussed below. During the trial, the parties are encouraged to
`
`address the constructions of the means-plus-function limitations in claim 16.
`
`The parties also may wish to address the impact that a determination that the
`
`specification of the ’949 patent does not provide adequate corresponding
`
`structure for the recited functions should have on this proceeding and any
`
`final written decision.
`
`3. Remaining Terms
`
`For purposes of this Decision, we do not find it necessary to construe
`
`expressly any other claim terms. See, e.g., Nidec, 868 F.3d at 1017 (“[W]e
`
`need only construe terms ‘that are in controversy, and only to the extent
`
`necessary to resolve the controversy’ . . . .” (quoting Vivid Techs., Inc. v.
`
`Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999))).
`
`B. Principles of Law
`
`A patent claim is unpatentable under 35 U.S.C. § 103(a) if the
`
`differences between the claimed subject matter and the prior art are such that
`
`the subject matter, as a whole, would have been obvious at the time the
`
`invention was made to a person having ordinary skill in the art to which said
`
`subject matter pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`
`(2007). The question of obviousness is resolved on the basis of underlying
`
`
`
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`factual determinations including (1) the scope and content of the prior art;
`
`(2) any differences between the claimed subject matter and the prior art;
`
`(3) the level of ordinary skill in the art; and (4) any secondary
`
`considerations, if in evidence.5 Graham v. John Deere Co., 383 U.S. 1, 17–
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`18 (1966).
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`C. Alleged Obviousness over Bauer, Svensson, and Kim
`(Claims 10–15)
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`Petitioner asserts claims 10–15 of the ’949 patent are unpatentable
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`under 35 U.S.C. § 103 as obvious over the combined teachings of Bauer,
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`Svensson, and Kim. Pet. 29–67. For purposes of determining whether to
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`institute, we focus on Petitioner’s contentions with respect to independent
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`claim 10, and, in our analysis of claim 10, we address all of the arguments
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`made in the Preliminary Response.
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`1. Svensson
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`Svensson describes a multi-processor system in which data are sent
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`from a host processor to a client processor. Ex. 1110, at [57]. Figure 1 of
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`Svensson is reproduced below.
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`5 Patent Owner does not present arguments or evidence of such secondary
`considerations in the Preliminary Response.
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`Figure 1 depicts multi-processor system 100 having host processor 102 and
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`client processor 104. Ex. 1110, 3:49–50. Client processor 104 is the
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`processor for a digital signal processor (DSP) device. Ex. 1110, 3:54–58.
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`As Svensson explains, “[m]ost commercially available DSP devices include
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`on-chip memories, and as indicated in FIG. 1, the DSP includes ‘internal’
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`single-access RAM (SARAM) and dual-access RAM (DARAM) 108, as
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`well as an ‘external’ RAM (XRAM) 110.” Ex. 1110, 3:64–4:1. Svensson
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`explains that “XRAM 110 is invisible to, i.e., not accessible by, the CPU
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`102,” whereas CPU 102 can access “internal” SARAM and DARAM 108.
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`Ex. 1110, 4:5–8, 4:13–14. DSP processor 104 can access both RAMs 108
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`and 110. Ex. 1110, 4:7–8.
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`Because host processor 102 cannot access XRAM 110, Svensson
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`discloses a technique for sending data from host processor 102 to be stored
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`in XRAM 110. Ex. 1110, Fig. 2, 4:15–6:11, 7:7–8. Svensson’s Figure 2 is
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`reproduced below.
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`Figure 2 is a flow chart of Svensson’s bootloader operation. Ex. 1110, 3:34,
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`4:15–19. In step 212, a block of memory in “internal” memory 108 is
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`reserved as an intermediate storage area (ISA) for data that are being sent
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`from the host to the invisible memory of the client processor. Ex. 1110,
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`5:21–28. After the host transfers data to the ISA (step 216), the host tells the
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`client the ISA has been loaded and indicates whether more data are coming
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`(step 218). Ex. 1110, 5:53–63. The client then copies the data from the ISA
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`to its “invisible” memory (step 220) and responds to the host when copying
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`is finished (step 222). Ex. 1110, 5:63–6:3. “If there is more code and/or
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`data to load (Step 224), this cycle of copying and messaging (Steps 216-224)
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`can be repeated as many times as required.” Ex. 1110, 6:4–6.
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`2. Bauer
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`Bauer discloses the file format depicted in Figures 1A, 1B, and 1C,
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`which are reproduced below.
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`
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`Figure 1A shows the format for a data image, Figure 1B shows the header of
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`the data image, and Figure 1C shows the section information of the data
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`image. Ex. 1109 ¶¶ 21–23. As shown in Figure 1A, binary data image 100
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`has header 102, section information 104, and section data 106. Ex. 1109
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`¶ 32. Each section of data in section data 106 has a section information
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`entry in section information 104, two of which are depicted in Figure 1C as
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`entries 104-1 and 104-2. Ex. 1109 ¶ 34. Each section information entry
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`indicates the length (108) and load address (110) for its respective section
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`data. Ex. 1109 ¶ 34. Additional information about a section may be
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`included in extra information element 112. Ex. 1109 ¶ 34.
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`According to Bauer, “[h]aving all section information entries 104
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`collected together in the image 100 advantageously simplifies system
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`navigation through the image, and having all section data arranged in a
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`sequence makes it possible to optimize loading of the sections.” Ex. 1109
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`¶ 38. Bauer explains that “[t]here are many possible applications of this
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`format and its individually coded sections,” including “[o]bject code and
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`data . . . with a program loader reading the stored information and
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`processing stored sections accordingly.” Ex. 1109 ¶ 31. “One example of
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`such a program loader is described in U.S. patent application Ser. No.
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`11/040,798 filed on Jan. 22, 2005, by M. Svensson et al. for ‘Operating-
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`System-Friendly Bootloader.’” Ex. 1109 ¶ 31. This is the application that
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`issued as Svensson. Svensson’s Figure 1 depicts the same multi-processor
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`system as Bauer’s Figure 2, which Bauer says “can advantageously use a
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`binary image 100 having the format depicted in FIGS. 1A, 1B, 1C.”
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`Ex. 1109 ¶ 35; compare Ex. 1110, Fig. 1, with Ex. 1109, Fig. 2.
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`3. Kim
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`Kim discloses a system in which a system startup loader in a system
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`management processor provides program blocks to multiple other processors
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`in a system. Ex. 1112, 4:8–21, Fig. 1. Figure 3 of Kim is reproduced below.
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`Figure 3 is a flowchart showing a procedure for loading program blocks
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`from the system startup loader to other processors in the system. Ex. 1112,
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`5:9–11. In step S304, the booter in a processor requests program block
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`header information, which the system startup loader provides in step S305.
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`Ex. 1112, 5:18–21. When the header is received, the booter requests a
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`program block in step S307, which the system startup loader provides in step
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`S309. Ex. 1112, 5:21–24. If there are more blocks to be received, the
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`booter returns to step S304. Ex. 1112, 6:2–4.
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`4. Independent Claim 10
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`a. Overview of Petitioner’s Contentions
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`Independent claim 10 is directed to a method involving “a secondary
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`processor,” “a primary processor,” “an inter-chip communication bus,”
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`“memory coupled to the primary processor,” and “system memory to which
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`the secondary processor is coupled.” Figure 2 of Bauer is reproduced below.
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`
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`Figure 2 of Bauer depicts multi-processor system 200 having host
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`processor 202 and client processor 204. Ex. 1109 ¶ 35. In Figure 2, host
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`processor 202 is an advanced RISC (reduced instruction set computer)
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`machine (ARM) central processing unit (CPU), and client processor 204 is a
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`DSP CPU. Ex. 1109 ¶ 35.
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`In its obviousness contentions, Petitioner argues a person of ordinary
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`skill in the art would have been motivated to combine the teachings of Bauer
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`and Svensson because, among other reasons, Bauer expressly cites
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`Svensson’s program loader as an example of a program loader that can use
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`the file format disclosed in Bauer. Pet. 31 (citing Ex. 1109 ¶ 31; Ex. 1102
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`¶¶ 109–110); see Ex. 1109 ¶ 31 (“One example of such a program loader is
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`described in U.S. patent application Ser. No. 11/040,798 filed on Jan. 22,
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`2005, by M. Svensson et al. for ‘Operating-System-Friendly Bootloader.’”).
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`Based on the interrelatedness of the references, Petitioner refers to the
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`teachings of “Bauer and Svensson combined.” Pet. 31.
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`Referring to Bauer’s Figure 2, which depicts the same multi-processor
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`system as Svensson’s Figure 1, Petitioner contends the DSP device teaches
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`the claimed “secondary processor” and the ARM device teaches the claimed
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`“primary processor.” Pet. 32–33. Petitioner further argues Figure 2 of
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`Bauer and Figure 1 of Svensson show these two processors coupled by a bus
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`and that the combination of Bauer and Svensson, therefore, teaches “an
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`inter-chip communication bus.” P