Trials@uspto.gov
`571-272-7822
`
`Paper No. 9
`Entered: January 17, 2019
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`____________
`
`Case IPR2018-01404
`Patent No. 7,279,727 B2
`____________
`
`
`Before MATTHEW R. CLEMENTS, JEFFREY W. ABRAHAM, and
`SCOTT E. BAIN, Administrative Patent Judges.
`
`ABRAHAM, Administrative Patent Judge.
`
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314(a)
`
`
`
`
`
`
`
`571-272-7822
`
`Paper No. 9
`Entered: January 17, 2019
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`____________
`
`Case IPR2018-01404
`Patent No. 7,279,727 B2
`____________
`
`
`Before MATTHEW R. CLEMENTS, JEFFREY W. ABRAHAM, and
`SCOTT E. BAIN, Administrative Patent Judges.
`
`ABRAHAM, Administrative Patent Judge.
`
`
`
`
`
`DECISION
`Institution of Inter Partes Review
`35 U.S.C. § 314(a)
`
`
`
`
`
`
`
`
`IPR2018-01404
`Patent No. 7,279,727 B2
`
`
`
`
`I. INTRODUCTION
`Intel Corp. (“Petitioner”) filed a Petition requesting an inter partes
`review of claims 1, 10, and 11 of U.S. Patent No. 7,279,727 B2 (Ex. 1003,
`“the ’727 patent”). Paper 2 (“Pet.”). Godo Kaisha IP Bridge 1 (“Patent
`Owner”) filed a Preliminary Response. Paper 6 (“Prelim. Resp.”).
`To institute an inter partes review, we must determine that the
`information presented in the Petition shows “a reasonable likelihood that the
`petitioner would prevail with respect to at least 1 of the claims challenged in
`the petition.” 35 U.S.C. § 314(a). For the reasons set forth below, upon
`considering the Petition and evidence of record, we determine that the
`information presented in the Petition establishes a reasonable likelihood that
`Petitioner would prevail with respect to at least one of the challenged claims.
`On April 24, 2018, the Supreme Court held that a final written
`decision under 35 U.S.C. § 318(a) must decide the patentability of all claims
`challenged in the petition. SAS Inst., Inc. v. Iancu, 138 S. Ct. 1348 (2018).
`Accordingly, we institute inter partes review on all of the challenged claims
`based on all of the grounds identified in the Petition.
`Our findings of fact and conclusions discussed below are based on the
`evidentiary record developed thus far. This decision to institute trial is not a
`final decision as to the patentability of any challenged claim. Any final
`decision will be based on the full record developed during trial.
`
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`II. BACKGROUND
`A. Related Matters
`The parties indicate that the ’727 patent is at issue in Godo Kaisha IP
`Bridge 1 v. Intel Corp., Case No. 2:17-cv-676 (E.D. Tex. Sept. 29, 2017).
`Pet. 1; Paper 5, 2. Patent Owner also identifies IPR2018-01155, which
`involves related U.S. Patent No. 7,709,900 B2. Paper 5, 2.
`
`B. The ’727 Patent
`The ’727 Patent, titled “Semiconductor Device,” issued on October 9,
`2007. Ex. 1003, at [54], [45]. The object of the ’727 patent is “to provide a
`structure of a semiconductor device which can suppress variations in gate
`length caused by an optical proximity effect.” Id. at 2:58–61. In
`semiconductor fabrication, the optical proximity effect refers to “the
`influence of diffracted light[, which] causes a large error between the pattern
`dimension in the layout design and the actual pattern dimension on the
`semiconductor substrate.” Id. at 1:33–45.
`Figures 7A and 7B of the ’727 patent, reproduced below, illustrate the
`problem of the optical proximity effect in the prior art.
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`Figures 7A and 7B present “a plan view illustrating the design geometry of a
`known semiconductor device (e.g., standard cell) and a plan view illustrating
`the geometry of the known semiconductor device after fabricated,
`respectively.” Id. at 2:10–13. As shown in Figure 7, “a gate polysilicon
`film is provided across a P-type diffusion region and an N-type diffusion
`region which are surrounded with an element isolation region.” Id. at 2:14–
`17. The part of the film located on the isolation region forms gate
`interconnect G102, which includes contact pad G103 and contact C103 to
`connect gate interconnect G102 and an interconnect provided in an upper
`level. Id. at 2:23–28.
`Figure 7B shows the resulting device after subjecting the design in
`Figure 7A to a semiconductor device manufacturing process. Id. at 2:36–41.
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`The ’727 patent explains that the “the boundary between the gate
`interconnect part G102 and the contact pad G103 has a reflex angle rounded
`under the influence of the optical proximity effect when exposed to light.”
`Id. at 2:42–45. The optical proximity effect also causes an error with respect
`to the desired gate length. Id. at 2:45–49. According to the ’727 patent, it
`was “possible to suppress the error of the gate length caused by the optical
`proximity effect by keeping a sufficient distance between the contact pad
`G103 and the diffusion region. However, this increases the area of the
`semiconductor device, decreases integration density, and hence is not
`practical.” Id. at 2:49–54.
`The ’727 patent solved the optical proximity effect problem by using
`a gate conductor film having a constant dimension in the gate length
`direction, as shown in Figures 1A and 1B. Id. at 2:66–3:5.
`
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`Figures 1A and 1B are a plan view of the design geometry of a
`semiconductor device according to a first embodiment of the present
`invention, and a plan view of the geometry of the semiconductor device after
`fabrication, respectively. Id. at 3:50–54. Figure 1A illustrates a
`semiconductor design in which gate length direction “L” is constant along
`the entire gate conductor film G0, with no enlarged “contact pad” G103 in
`the element isolation region as was the case in the prior art design of Figure
`7A. Id. at 4:35–64. The resulting fabricated device, shown in Figure 1B,
`does not have a gate with rounded corners that overlap into the diffusion
`region, as in prior art Figure 7B, and variations in gate length are
`suppressed. Id. at 4:65–5:24.
`
`C. Challenged Claims
`Petitioner challenges claims 1, 10, and 11 of the ’727 patent.
`Independent claim 1 is reproduced below:
`1. A semiconductor device, comprising:
`a semiconductor substrate;
`a diffusion region which is formed in the semiconductor
`substrate and serves as a region for the formation of a [Metal-
`Insulator-Semiconductor (MIS)] transistor;
`an element isolation region surrounding the diffusion region;
`at least one gate conductor film which is formed across the
`diffusion region and the element isolation region, includes a
`gate electrode part located on the diffusion region and a gate
`interconnect part located on the element isolation region, and
`has a constant dimension in a gate length direction;
`an interlayer insulating film covering the gate electrode part;
`and
`a gate contact which passes through the interlayer insulating
`film, is connected to the gate interconnect part, and has a
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`dimension in the gate length direction larger than the gate
`interconnect part.
`Ex. 1003, 10:53–11:4.
`
`D. The Asserted Grounds
`Petitioner asserts the following grounds of unpatentability (Pet. 4):
`Reference(s)
`Basis
`Claim(s) Challenged
`Takeshi1 and Lyu2
`§ 103
`1
`
`Takeshi, Lyu, and Sawai3
`
`Maeda4 and Wieczorek5
`
`Maeda, Wieczorek, and Sawai
`
`§ 103
`
`§ 103
`
`§ 103
`
`10, 11
`
`1
`
`10, 11
`
`Chakihara6
`
`Petitioner also relies on the Declaration of Michael Watts, Ph.D.
`Ex. 1001.
`
`§ 103
`
`1
`
`
`
`
`1 JP-9-246541, published Sept. 19, 1997 (Ex. 1007 (certified translation);
`Ex. 1006 (original)).
`2 U.S. Patent No. 7,405,450 B2, issued July 29, 2008 (Ex. 1011).
`3 JP 2003-218117, published July 31, 2003 (Ex. 1014 (certified translation);
`Ex. 1013 (original)).
`4 JP S62-217635, published Sept. 25, 1987 (Ex. 1009 (certified translation);
`Ex. 1008 (original)).
`5 U.S. Patent No. 6,566,718 B2, issued May 20, 2003 (Ex. 1012).
`6 U.S. Patent No. 7,190,031 B2, issued Mar. 13, 2007 (Ex. 1010).
`
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`III. ANALYSIS
`A. Claim Construction
`In an inter partes review, claim terms in an unexpired patent are
`construed according to their broadest reasonable interpretation in light of the
`specification of the patent in which they appear. 37 C.F.R. § 42.100(b)
`(2016).7 A claim term, however, “will not receive its ordinary meaning if
`the patentee acted as his own lexicographer and clearly set forth a definition
`of the disputed claim term in either the specification or prosecution history.”
`CCS Fitness, Inc. v. Brunswick Corp., 288 F.3d 1359, 1366 (Fed. Cir. 2002).
`Although the patentee indeed is free to define the specific claim terms used
`to describe his or her invention, “this must be done with reasonable clarity,
`deliberateness, and precision.” In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir.
`1994).
`Both parties assert that no claim terms need explicit construction at
`this stage. Pet. 6; Prelim. Resp. 6. The parties’ unpatentability arguments,
`however, indicate that the primary dispute at this stage centers on a claim
`term, namely, “an element isolation region surrounding the diffusion
`region.” Ex. 1003, 10:58–59 (emphasis added); see, e.g., Pet. 24–26;
`Prelim. Resp. 8–15. We address this dispute in our analysis of Petitioner’s
`unpatentability contentions, below.
`
`
`7 The broadest reasonable construction standard applies to inter partes
`reviews filed before November 13, 2018. 77 Fed. Reg. 48727 (Aug. 14,
`2012) (codified at 37 C.F.R. § 42.100(b)), as amended at 81 Fed. Reg. 18766
`(Apr. 1, 2016); see also 83 Fed. Reg. 51340 (Oct. 11, 2018) (changing the
`standard for interpreting claims in inter partes reviews filed on or after
`November 13, 2018).
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`We determine that no other claim terms of the ’727 patent require
`express construction for purposes of this Decision. See Nidec Motor Corp.
`v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013, 1017 (Fed. Cir.
`2017) (citing Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803
`(Fed. Cir. 1999) (“[O]nly those terms need be construed that are in
`controversy, and only to the extent necessary to resolve the controversy.”)).
`
`B. Asserted Grounds of Unpatentability
`A claim is unpatentable under 35 U.S.C. § 103(a) if the differences
`between the claimed subject matter and the prior art are “such that the
`subject matter as a whole would have been obvious at the time the invention
`was made to a person having ordinary skill in the art to which said subject
`matter pertains.” We resolve the question of obviousness on the basis of
`underlying factual determinations, including: (1) the scope and content of
`the prior art; (2) any differences between the claimed subject matter and the
`prior art; (3) the level of skill in the art;8 and (4) objective evidence of
`nonobviousness, i.e., secondary considerations.9 See Graham v. John Deere
`Co., 383 U.S. 1, 17–18 (1966).
`
`
`8 Petitioner, relying on Dr. Watts’ testimony, contends that a person of
`ordinary skill in the art “would have had at least a B.S. degree in electrical
`engineering, chemistry, physics, chemical engineering, or materials science
`(or equivalent experience), and at least two or three years of experience with
`semiconductor processing, manufacturing and structures.” Pet. 17 (citing
`Ex. 1001 ¶¶ 60–63). Patent Owner does not dispute Petitioner’s proposed
`level of skill or offer its own proposal. Accordingly, for purposes of this
`Decision, we adopt Petitioner’s proposal.
`9 The current record does not include allegations or evidence of objective
`indicia of nonobviousness.
`
`9
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`1. Claim 1 – Obvious Over Takeshi and Lyu
`Petitioner contends that the subject matter of claim 1 would have been
`obvious in view of the combined teachings of Takeshi and Lyu. Pet. 22–41.
`
`a. Takeshi
`Takeshi is directed to a method of manufacturing a complementary
`metal-oxide-semiconductor (“CMOS”) such that “[i]t is possible to suppress
`the increase in the cell area and the increase in the number of steps . . . while
`preventing mutual diffusion of N type and [P] type impurities.” Ex. 1007,
`(57) [Objective], ¶¶ 1, 9. To achieve these objectives, Takeshi describes “a
`gate electrode pattern formed in a state of being physically continued to a
`region where a P-channel MOS transistor is to be formed and a region where
`an N-channel MOS transistor is to be formed . . . as compared with the
`conventional method of physically separating the P-type gate electrode and
`the N-type gate electrode.” Id. ¶ 12.
`
`b. Lyu
`Lyu is directed to “semiconductor devices and methods of fabricating
`semiconductor devices that include a plurality of isolation regions in a
`semiconductor substrate that define an active region.” Ex. 1011, 2:6–9.
`Lyu’s semiconductor devices also comprise a gate electrode provided on the
`active region, wherein a conductive layer is electrically connected to the gate
`electrode. Id. at 2:9–12.
`
`c. Analysis
`Petitioner asserts that Takeshi discloses a semiconductor device that
`comprises a semiconductor substrate, as claim 1 requires. Pet. 22 (citing
`Ex. 1007 ¶¶ 1, 2–5, 10, 11, 15, 30, 31, 50; Ex. 1001 ¶¶ 88–89). Claim 1 also
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`requires “a diffusion region which is formed in the semiconductor substrate
`and serves as a region for the formation of a MIS transistor.” Ex. 1003,
`10:55–57. Petitioner directs us to Takeshi’s statement that “a diffusion layer
`is formed in each of the semiconductor substrate surface layer portions,” and
`to “diffusion layers 11 and 12” in Figure 3. Pet. 23 (citing Ex. 1007, Claim
`1, Claim 2, ¶¶ 4, 10–11, 23–25, 40–42, 47–50). Petitioner also contends that
`“Takeshi describes diffusion regions as ‘impurity regions’ called ‘NMOS
`transistor’ and ‘PMOS transistor.’” Pet. 28 (citing Ex. 1007 ¶ 15; Ex. 1001
`¶ 97). To support its arguments, Petitioner provides two annotated
`Diagrams from Takeshi, which are reproduced below.
`
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`Diagrams 2A and 3A of Takashi show plan views of different steps in
`
`the process of making one of Takeshi’s semiconductor devices. In these
`figures, Petitioner highlights diffusion regions in green. Pet. 23.
`Petitioner further argues that Takeshi describes the formation of
`CMOS devices, which is one type of MIS transistor, and, therefore, a person
`of ordinary skill in the art would have understood that Takeshi’s diffusion
`region serves as a region for the formation of an MIS transistor. Id. at 24
`(citing Ex. 1007 ¶¶ 2–3, 14–16; Ex. 1001 ¶ 92).
`As to the claim 1 requirement of “an element isolation region
`surrounding the diffusion region” (Ex. 1003, 10:58–59), Petitioner directs us
`to Takeshi’s disclosure of element isolation film 2, which “is formed on the
`Si substrate 1 so as to surround the NMOS formation scheduled region 3 and
`the PMOS formation scheduled region 4.” Pet. 24 (quoting Ex. 1007 ¶ 15;
`citing Ex. 1007, Diagrams 1–4, ¶ 31; Ex. 1001 ¶¶ 93–94).
`Petitioner contends that Takeshi’s “gate electrode” corresponds to the
`gate conductor film recited in claim 1, and is formed between Takeshi’s
`diffusion regions and over the element isolation region. Pet. 28 (citing Ex.
`1007 ¶ 15). Petitioner thus contends that Takeshi’s gate electrode is
`“formed across the diffusion region and the element isolation region [and]
`includes a gate electrode part located on the diffusion region and a gate
`interconnect part located on the element isolation region,” as claim 1
`requires. Id. at 28–29 (citing Ex. 1007 ¶ 12 (disclosing “a gate electrode
`pattern formed in a state of being physically continued to a region where a
`P-channel MOS transistor is to be formed and a region where an N-channel
`MOS transistor is to be formed”), Claim 1, Claim 2, ¶¶ 2–4, 13, 18, 49–50;
`Ex. 1001 ¶ 97); Ex. 1003, 10:60–64.
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`Petitioner directs us to Takeshi Diagram 2, which depicts the gate
`electrode having a rectangular shape. Pet. 29–30. Based on this diagram,
`Petitioner argues that the gate electrode “has a constant dimension in a gate
`length direction” as recited in claim 1. Id.; Ex. 1003, 10:64–65.
`Claim 1 also recites “an interlayer insulating film covering the gate
`electrode part.” Ex. 1003, 10:66–67. With regard to this limitation,
`Petitioner directs us to Takeshi’s disclosure of “a second step of forming an
`interlayer insulating film on the semiconductor substrate so as to cover the
`gate electrode pattern.” Pet. 31 (citing Ex. 1007, Claim 1, Diagram 2; Ex.
`1001 ¶ 99).
`Petitioner argues that Takeshi, either alone or in combination with
`Lyu, teaches or suggests “a gate contact which passes through the interlayer
`insulating film, is connected to the gate interconnect part, and has a
`dimension in the gate length direction larger than the gate interconnect part.”
`Pet. 32–41; Ex. 1003, 11:1–4. In addition to directing us to various portions
`of the references that purportedly disclose this limitation, Petitioner argues
`Takeshi and Lyu are “in the same field,” that a person of ordinary skill in the
`art “would have naturally looked to Lyu’s contacts to increase performance,”
`and that a person of ordinary skill in the art “would also have understood
`that combining Takeshi and Lyu results in additional advantages, such as
`minimizing cracks in the silicide layer, as well as supporting the
`miniaturization of transistors.” Id. at 35–36 (citing Ex. 1001 ¶¶ 79, 83–86;
`Ex. 1007, Objective, ¶¶ 2–3, 7–9; Ex. 1011, 1:25–33, 1:58–2:2.).
`The only aspect of Petitioner’s evidence and arguments that Patent
`Owner challenges at this stage of the proceeding is Petitioner’s assertion that
`Takeshi teaches “an element isolation region surrounding the diffusion
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`region.” Prelim. Resp. 8. In this regard, Patent Owner argues that
`“[b]ecause Petitioner is unable to identify a ‘diffusion region’ in Takeshi that
`satisfies all requirements for the claimed ‘diffusion region,’ Petitioner points
`to different structures as the claimed ‘diffusion region’ for different
`limitations of the challenged claims.” Id. at 8–9. Specifically, Patent Owner
`notes that Petitioner identifies “diffusion layers 11 and 12” as the claimed
`“diffusion region which is formed in a semiconductor substrate,” but refers
`to “NMOS formation scheduled region 3 and the PMOS formation
`scheduled region 4” as the diffusion regions that the “element isolation
`region surround[s].” Id.
`We disagree that Petitioner points to different structures as the
`claimed diffusion region for different limitations of the challenged claims.
`In the Petition, Petitioner argues “Takeshi states that ‘a diffusion layer is
`formed in each of the semiconductor substrate surface layer portions . . . .’”
`Pet. 23 (emphasis omitted). Petitioner cites to Takeshi Claim 1 in support of
`this assertion. Id. Claim 1 states that “a diffusion layer is formed in each of
`the semiconductor substrate surface layer portions of the formation region of
`the P-channel MOS transistor and the formation region of the N-channel
`MOS transistor.” Ex. 1007, Claim 1 (emphasis added); see also id. ¶ 10
`(cited by Petitioner in addition to claim 1 and containing a similar
`disclosure). Petitioner also cites to Takeshi paragraph 47 to support its
`argument that Takeshi discloses a diffusion region which is formed in the
`semiconductor substrate. Pet. 23. Takeshi paragraph 47 refers to “NMOS
`formation scheduled region 3 and the PMOS formation scheduled region 4.”
`Ex. 1007 ¶ 47.
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`Thus, Petitioner cites to portions of Takeshi that (1) establish regions
`3 and 4 as scheduled transistor formation regions, and (2) indicate diffusion
`layers are formed in each substrate surface layer of these formation regions.
`Ex. 1007, Claim 1, ¶ 47; see also id. ¶ 15 (another portion of Takeshi
`defining regions 3 and 4 as NMOS formation and PMOS formation regions,
`respectively). This is consistent with Petitioner’s annotated version of
`Takeshi Diagram 2A, wherein Petitioner highlights regions 3 and 4 in green,
`indicating that these correspond to the claimed diffusion regions. In view of
`this, we disagree with Patent Owner’s contention that “there is no apparent
`relationship” between any of Petitioner’s citations and “the regions 3 and 4
`that Petitioner has highlighted in Figure 2.” Prelim. Resp. 10. The
`aforementioned evidence also undermines Patent Owner’s argument that
`“neither Petitioner nor Dr. Watts has attempted to show that the claimed
`‘diffusion region which is formed in the semiconductor substrate’ is
`anything other than the ‘diffusion layers 11 and 12’ shown in Figure 3(A) in
`Takeshi.” Id. at 11.
`Furthermore, Takeshi paragraph 15, cited by Petitioner in various
`places in the Petition, states that “the element isolation film 2 is formed on
`the Si substrate 1 so as to surround the NMOS formation scheduled region 3
`and the PMOS formation scheduled region 4.” Ex. 1007 ¶ 15; see also Pet.
`24 (citing Takeshi paragraph 15 as support for the argument that Takeshi’s
`diffusion region serves as a region for the formulation of a MIS transistor
`and is surrounded by an element isolation region). Patent Owner does not
`dispute that Takeshi discloses that element isolation layer 2 surrounds
`regions 3 and 4.
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`Thus, contrary to Patent Owner’s arguments (see, e.g., Prelim. Resp.
`8), we determine that based on the present record, Petitioner has identified a
`“diffusion region” in Takeshi that satisfies all requirements of the claimed
`“diffusion region.” As noted above, the remainder of Petitioner’s assertions
`that the subject matter of claim 1 would have been obvious to a person of
`ordinary skill in the art are unchallenged by Petitioner at this time.
`Accordingly, after reviewing the arguments and evidence presented
`by both parties, we determine that the current record establishes a reasonable
`likelihood that Petitioner would prevail on its assertion that claim 1 is
`unpatentable as obvious in view of Takeshi and Lyu.
`
`2. Claims 10 and 11 – Obvious Over Takeshi, Lyu, and Sawai
`Claims 10 and 11 depend directly or indirectly from claim 1. We
`have reviewed Petitioner’s arguments and evidence regarding these claims,
`which Patent Owner does not contest separately from the arguments
`regarding claim 1 at this stage. Pet. 42–48; Prelim. Resp. 34. We are
`persuaded, on this record, that Petitioner has demonstrated a reasonable
`likelihood that that it would prevail with respect to claims 10 and 11 as
`obvious over Takeshi, Lyu, and Sawai.
`3. Claim 1- Obvious over Maeda and Wieczorek
`Petitioner contends that the subject matter of claim 1 would have been
`obvious in view of the combined teachings of Maeda and Wieczorek. Pet.
`49–64.
`
`a. Maeda
`Maeda discloses a semiconductor design that includes a first wiring
`layer formed over a substrate with an insulating layer between them, a
`second wiring layer formed over the first wiring layer with an insulating
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`layer between them, and a contact hole, providing a contact between the first
`and second wiring layers, which is wider than the width of the first wiring
`layer. Ex. 1009, Fig. 1(A), 3:51–67.10 Maeda further discloses an N+-type
`source region and an N--type source region formed on opposite sides of a
`channel region, and a gate electrode formed over the channel region. Id. at
`3:1–12. A contact hole is formed on one edge of the gate electrode and is
`designed to be wider than the gate electrode. Id. at 3:17–25. According to
`Maeda, its invention allows a semiconductor device to “be miniaturized to
`enable increased levels of integration without producing shorting between
`the wiring and the semiconductor substrate, and that also reduces the contact
`resistance in wiring.” Id. at 3:39–47.
`
`b. Wieczorek
`Wieczorek is directed to “the formation of a gate electrode of a field
`effect transistor (FET) having a reduced signal propagation time at the gate
`electrode.” Ex. 1012, 1:9–11. The design of Wieczorek includes “shallow
`trench isolations” formed in a substrate, to “define an active region of [a]
`transistor.” Id. at 4:52–56, 5:6–10. Further, the active region includes a
`drain and a source region separated by a channel, and a gate electrode
`formed over and separated from the channel. Id. at 4:56–59. Wieczorek’s
`design also includes a “gate electrode contact of a highly conductive
`material that contacts the gate electrode and extends in the transistor width
`dimension at least along a portion of the channel.” Id. at Abstract.
`
`
`10 For Exhibit 1009, page numbers refer to those provided by Petitioner on
`the bottom left hand side of the page.
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`c. Analysis
`Petitioner directs us to teachings in Maeda and Wieczorek for each
`element of claim 1, and further relies on Dr. Watts’ testimony. Pet. 49–64;
`Ex. 1003 ¶¶ 122–157. Patent Owner does not dispute Petitioner’s
`contentions except for the claim 1 limitation requiring “an element isolation
`region surrounding the diffusion region.” Prelim. Resp. 15–30. As to the
`undisputed limitations, we have reviewed the arguments and evidence on
`this record, and we are persuaded that the evidence sufficiently supports
`finding that Maeda and Wieczorek teach or suggest each of the limitations.
`In support of its argument that Maeda discloses “an element isolation
`region surrounding the diffusion region,” Petitioner directs us to annotated
`versions of Maeda’s Figures 1(A) and 1(B), and their accompanying
`descriptions. Pet. 52. Petitioner’s annotated Figures 1(A) and 1(B) are
`reproduced below.11
`
`
`
`Figure 1(A) is a “pattern plan view diagram” of a MOS
`semiconductor, and Figure 1(B) is a “cross-sectional diagram [of the same
`semiconductor] along the channel region thereof.” Ex. 1009, 4:7–11. The
`
`
`11 Petitioner’s annotations are substantively identical to the original Maeda
`Figures 1(A) and 1(B), but with color shading added. Compare Pet. 52 with
`Ex. 1008, 4.
`
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`IPR2018-01404
`Patent No. 7,279,727 B2
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`figures together depict, among other elements, “P-type silicon substrate” 1,
`“field oxide film” 2, “N+-type source region 3,” and “N+-type drain region
`4.” Id. at 4:13–15. Petitioner contends the N+-type source and drain regions
`3 and 4 correspond to the claimed diffusion regions, that field oxide film 2
`corresponds to the claimed element isolation region, and that the two views
`shown in Maeda Figures 1(A) and 1(B) together depict an element isolation
`region (purple-shaded annotations) surrounding the diffusion region (green-
`shaded annotations), as recited in claim 1. Pet. 51–52. Petitioner further
`argues Maeda teaches that its diffusion regions are “encompassed by [the]
`field oxide film.” Id. at 52 (citing Ex. 1009, 3:4–8).
`Petitioner also contends that even if Maeda is found not to expressly
`disclose this limitation, one of ordinary skill in the art would have “found it
`obvious to surround the region 3 and 4 with field oxide film 2 in order to
`electrically isolate Maeda’s transistor.” Id. (emphasis omitted). Citing the
`testimony of Dr. Watts, Petitioner contends a person of ordinary skill in the
`art would have “known that transistors are generally electrically isolated
`from other transistors, which is fundamental to the creation of functioning
`transistor devices.” Id. (citing Ex. 1001 ¶¶ 135–136).
`As another alternative argument, Petitioner contends that the subject
`matter of claim 1 would have been obvious in view of the combined
`teachings of Maeda and Wieczorek, which, according to Petitioner, discloses
`shallow trench isolations that define an active region of a transistor. Id. at
`52–53 (citing Ex. 1012, 4:52–56). Petitioner explains why a person of
`ordinary skill in the art “would have been motivated to combine the isolation
`region of Wieczorek with Maeda’s system.” Id. at 53–54 (citing Ex. 1001
`¶¶ 135–136; Ex. 1009, 3:39–47; Ex. 1012, 1:17–24, 3:22–32).
`
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`Patent Owner contends that Petitioner’s reliance on the two figures in
`
`Maeda constitutes two different “approaches” to mapping the “diffusion
`region” claim limitation, and that neither approach discloses an element
`isolation region surrounding the diffusion region. Prelim. Resp. 15–16.
`First, Patent Owner contends annotated Figure 1(B) illustrates that the
`alleged diffusion area (in green) and the alleged element isolation region (in
`purple) “are formed in the same area,” and the element isolation region
`cannot surround the diffusion region “[b]ecause the field oxide 2 does not
`extend beyond the diffusion region as defined by Petitioner.” Id. at 17.
`Second, Patent Owner contends Figure 1(A) shows only an isolation region
`(in purple) on “both sides” of an alleged diffusion region (in green), but the
`isolation region “does not exist in the direction perpendicular to the direction
`in which the gate electrode 6 extends (i.e., above and below the active region
`as shown in Figure 1(A)).” Id. at 17–18.
`
` We are persuaded by Petitioner’s showing on this record. First, we
`do not agree with Patent Owner’s assertion that Petitioner describes two
`alternative “approaches.” Rather, Petitioner relies on two different
`viewpoints of the same semiconductor embodiment, as depicted in Maeda
`Figures 1(A) and 1(B). Maeda describes Figure 1(A) as a pattern plan view
`diagram (partial top-down view) of a “MOS semiconductor device,” and
`Figure 1(B) as a cross-sectional diagram (partial side-view) “along the
`channel region thereof,” respectively. Ex. 1009, 4:7–11 (emphasis added).
`“Thereof” logically refers to the same semiconductor.
`
`Second, Petitioner contends that Maeda’s N+-type source region 3 and
`an N+-type drain region 4 comprise diffusion regions. Patent Owner does
`not offer any evidence to challenge Petitioner’s identification of regions 3
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`IPR2018-01404
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`and 4 as diffusion regions, but rather disputes only Petitioner’s assertion that
`Maeda discloses that the element isolation region surrounds the diffusion
`regions. Prelim. Resp. 17. Maeda, however, explains that regions 3 and 4
`are part of the “circuit element region,” and that the circuit element region is
`“encompassed by” the field oxide film. Ex. 1009, 3:1–8. 12 Dr. Watts’
`testimony equates “encompassed” with “surrounded” in the context of
`semiconductor design, and Patent Owner offers no evidence in rebuttal. Ex.
`1001 ¶ 134; see also Oxford English Dictionary Online,
`http://www.oed.com/search?searchType=dictionary&q
`=surround&_searchBtn=Search (last visited January 10, 2019) (“surround, v
`. . . [t]o enclose, encompass . . . .”). Instead, Patent Owner selectively cites
`to Maeda’s disclosure at page 3, column A, lines 5–8, and argues that Maeda
`“says nothing about the location of the field oxide film 2 in relation to region
`3 and 4.” Prelim. Resp. 18–19. In doing so, however, Patent Owner ignores
`the previous sentence in Maeda, which, as noted above, explains that regions
`3 and 4 are part of the circuit element region encompassed by the field oxide
`film.
`Finally, the ’727 patent itself describes numerous “plan view[s]” in
`which diffusion regions are “surrounded with an element isolation region.”
`Ex. 1003, 2:14–19, 4:35–39, 6:35–38 (emphasis added). The corresponding
`figures in the ’727 patent depicting these plan views are similar to Maeda’s
`depictions of a field oxide film encompassing an active region, i.e., none of
`the figures in the ’727 patent illustrate semiconductor elements
`
`12 Although this passage in Maeda is describing Figures 3(A) and 3(B),
`Maeda discloses the relevant parts “are identical to those” in Figures 1(A)
`and 1(B). Ex. 1009, 4:18–20.
`
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`“surrounding” other elements any differently from Maeda’s depiction of
`semiconductor elements “encompassed by” other elements. See Ex. 1003,
`Figs. 1A, 1B, 3A, 3B, 7A, 7B. Moreover, the ’727 patent depicts a
`semiconductor as elements layered,
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