Trials@uspto.gov
`571-272-7822
`
`PUBLIC VERSION
`
`Paper 50
`Date: March 12, 2020
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC.,
`Petitioner
`
`v.
`
`QUALCOMM INC.,
`Patent Owner.
`____________
`
`IPR2018-01460
`Patent 9,024,418 B2
`____________
`
`Before MICHELLE N. WORMMEESTER, AMANDA F. WIEKER,
`and AARON W. MOORE, Administrative Patent Judges.
`
`MOORE, Administrative Patent Judge.
`
`JUDGMENT
`FINAL WRITTEN DECISION
`Determining Some Challenged Claims Unpatentable
`35 U.S.C. § 318(a)
`
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`IPR2018-01460
`Patent 9,024,418 B2
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`PUBLIC VERSION
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`I.
`
`II.
`
`2.
`3.
`4.
`
`TABLE OF CONTENTS
`INTRODUCTION ................................................................................ 1
`A.
`Background ................................................................................ 1
`B.
`Related Matters .......................................................................... 1
`C.
`The ’418 Patent .......................................................................... 2
`D.
`The Claimed Subject Matter ...................................................... 3
`E.
`Evidence Relied Upon ................................................................ 5
`1.
`Rashed .............................................................................. 5
`2.
`Nauta ................................................................................ 7
`Grounds of Unpatentability ........................................................ 7
`F.
`ANALYSIS .......................................................................................... 7
`A.
`Level of Ordinary Skill in the Art .............................................. 7
`B.
`Claim Construction .................................................................... 8
`1.
`“means for coupling the gate-directed
`local interconnect to the third gate layer” ........................ 9
`“configured to” and “forming . . . to” ............................ 10
`“diffusion-directed local interconnect” ......................... 10
`“first gate layer for the second transistor
`to a power supply node” ................................................ 11
`Antedating Rashed and Lu ....................................................... 12
`1.
`Sufficiency of Patent Owner’s
`Conception Evidence ..................................................... 12
`Conceived Subject Matter .............................................. 17
`2.
`Reduction to Practice ..................................................... 18
`3.
`4. Word Limit..................................................................... 23
`5.
`Conclusion Regarding Antedating ................................. 24
`Patentability of Claims 3, 9, 10, 14, and 19 ............................. 25
`1.
`The Independent Claims ................................................ 26
`a.
`“[a] circuit comprising” ....................................... 26
`
`C.
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`D.
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`b.
`
`“a first gate layer arranged according
`to a gate layer pitch between a second
`gate layer and a third gate layer”; “a first
`gate-directed local interconnect arranged
`between the first gate layer and the second
`gate layer”; and “a second gate-directed
`local interconnect arranged between the
`first gate layer and the third gate layer” .............. 27
`“a diffusion-directed local interconnect
`layer configured to couple the first gate
`layer to one of the first and second
`gate-directed local interconnects” ....................... 28
`“wherein the first gate-directed local
`interconnect, the second gate-directed
`local interconnect, and the diffusion-directed
`local interconnect are all located between a
`lower-most metal layer and a
`semiconductor substrate for the circuit” .............. 31
`Claim 3 ........................................................................... 31
`Claim 9 ........................................................................... 32
`Claim 10 ......................................................................... 32
`Claim 14 ......................................................................... 33
`Claim 19 ......................................................................... 34
`Conclusion on the Patentability of
`Claims 3, 9, 10, 14, and 19 ............................................ 35
`E. Motions to Seal ........................................................................ 35
`III. CONCLUSION .................................................................................. 39
`IV. ORDER ............................................................................................... 40
`
`c.
`
`d.
`
`2.
`3.
`4.
`5.
`6.
`7.
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`IPR2018-01460
`Patent 9,024,418 B2
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`I.
`
`INTRODUCTION
`
`A.
`
`Background
`Apple Inc. (“Petitioner”) filed a Petition for inter partes review of
`claims 1–5, 8–10, and 12–20 of U.S. Patent No. 9,024,418 B2 (Ex. 1001,
`“the ’418 patent”). Paper 2 (“Pet.”). Qualcomm Inc. (“Patent Owner”) filed
`a Preliminary Response. Paper 6 (“Prelim. Resp.”).
`On March 15, 2019, we instituted an inter partes review of claims 1–
`5, 8–10, and 12–20. Paper 7 (“Inst. Dec.”) 20. Patent Owner then filed a
`Patent Owner Response (Paper 20, “PO Resp.”), Petitioner filed a Reply
`(Paper 36, “Pet. Reply”), and Patent Owner filed a Sur-Reply (Paper 39,
`“PO Sur-Reply”).
`An oral hearing was held on December 12, 2019, and a transcript of
`the hearing is included in the record. Papers 46, 47 (“Tr.”).
`The Board has jurisdiction under 35 U.S.C. § 6. This Final Written
`Decision is issued pursuant to 35 U.S.C. § 318(a) and 37 C.F.R. § 42.73.
`For the reasons that follow, we determine that Petitioner has shown by a
`preponderance of the evidence that claims 3, 9, 10, and 14 of the ’418 patent
`are unpatentable, and that Petitioner has not shown that claims 1, 2, 4, 5, 8,
`12, 13, 15–19, and 20 are unpatentable.
`
`B.
`
`Related Matters
`The ’418 patent was at issue in Qualcomm Incorporated v. Apple
`Incorporated, Civil Action No. 3:17-CV-02402 (S.D. Cal.), when the
`Petition was filed, but that litigation has since been dismissed. See Pet. 1;
`Petitioner’s Updated Mandatory Notices (Paper 16) 1.
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`C.
`
`The ’418 Patent
`The ’418 patent concerns “[a] local interconnect structure . . . that
`includes a gate-directed local interconnect coupled to an adjacent gate layer
`through a diffusion-directed local interconnect.” Ex. 1001, Abstract.
`The claimed structure can be explained with reference to Figure 4A,
`annotated with colors below:
`
`Figure 4A shows “the layout for a pair of transistors in a continuous
`diffusion region including a blocking transistor.” Ex. 1001, 3:9–10.
`This embodiment1 includes continuous diffusion layer 400, which
`forms the basis for two transistors. The transistors consist of gate layers 410
`and 415, shown in green, and the associated source and sink regions in the
`continuous diffusion layer. An additional gate layer 430, shown in orange,
`operates as a blocking transistor. The source region for the right transistor is
`
`1 See Ex. 1001, 5:66–7:3.
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`provided with voltage by local interconnect 435, shown in yellow, which is
`biased by via V0. Local interconnect 445 couples interconnect 435 and gate
`layer 430. The gate layers and interconnect 435 are “gate directed,” which
`in this context means that their long dimensions are perpendicular to the
`length of the continuous diffusion layer; the local interconnect 445 is
`“diffusion directed,” which in this context means that its long dimension is
`parallel to the length of the continuous diffusion layer.
`The ’418 patent explains that because “[v]ias require a certain
`separation between them . . . the square-shaped local interconnect 460 of the
`prior art”––shown in dashed outline in Fig 4A––“had to be displaced
`vertically from via V0 to accommodate the via pitch,” and that the ’418
`patent’s “diffusion-directed local interconnect 445 eliminates the need for
`such a vertically-displaced coupling to gate layer 425” and thus “has an
`advantageously reduced cell height 404 for transistors 405 and 420 as
`compared to conventional cell height 403, which enhances density.”
`Ex. 1001, 6:60–7:3.
`
`D.
`
`The Claimed Subject Matter
`Independent claims 1, 12, and 17, reproduced below, illustrate the
`subject matter addressed in this proceeding. Claim 1 is directed to a circuit,
`claim 12 is directed to a method corresponding to the circuit of claim 1, and
`claim 17 is directed to a similar circuit, but drafted using means-plus-
`function terminology:
`
`1. A circuit comprising:
`a first gate layer arranged according to a gate layer pitch
`between a second gate layer and a third gate layer;
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`a first gate-directed local interconnect arranged between the
`first gate layer and the second gate layer;
`a second gate-directed local interconnect arranged between
`the first gate layer and the third gate layer; and
`a diffusion-directed local interconnect layer configured to
`couple the first gate layer to one of the first and second gate-
`directed local interconnects, wherein the first gate-directed
`local interconnect, the second gate-directed local
`interconnect, and the diffusion-directed local interconnect
`are all located between a lower-most metal layer and a
`semiconductor substrate for the circuit.
`12. A method, comprising:
`forming a first gate layer over a semiconductor substrate
`according to a gate layer pitch between adjacent second and
`third gate layers;
`forming a first gate-directed local interconnect between the
`first gate layer and the second gate layer;
`forming a second gate-directed local interconnect between
`the first gate layer and the third gate layer; and
`forming a diffusion-directed local interconnect to couple one
`of the first and second gate-connected local interconnects to
`the first gate layer, wherein the first gate-directed local
`interconnect, the second gate-directed local interconnect,
`and the diffusion-directed local interconnect are all located
`between the semiconductor substrate and an adjacent lower-
`most metal layer.
`17. A circuit comprising:
`a continuous diffusion region within a semiconductor
`substrate;
`a pair of gate layers configured to form gates for a pair of
`transistors having source/drain terminals in the continuous
`diffusion region;
`a third gate layer arranged between the pair of gate layers to
`form a gate for a blocking transistor;
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`a gate-directed local interconnect configured to couple to a
`drain/source terminal for a transistor in the pair of
`transistors; and
`means for coupling the gate-directed local interconnect to
`the third gate layer, wherein the gate-directed local
`interconnect and the means are both located between the
`semiconductor substrate and an adjacent lower-most metal
`layer.
`Ex. 1001, 9:6–19, 10:5–18, 10:38–52.
`
`E.
`
`Evidence Relied Upon
`Petitioner relies on the following references:
`
`Reference
`Rashed US 8,618,607 B2
`Lu
`US 9,123,565 B2
`Nauta
`Bram Nauta, A CMOS Transconductance-C
`Filter Technique For Very High Frequencies,
`IEEE Journal of Solid-State Circuits, Vol. 27,
`Issue 2 (Feb 1992)
`
`Exhibit
`1005
`1006
`1007
`
`Petitioner also relies on a Declaration of David Kuan-Yu Liu, filed as
`Exhibit 1003 (“Liu Decl.”). Patent Owner relies on a Declaration of
`Dr. Pradeep Lall, filed as Exhibit 2002 (“Lall Decl.”).
`
`Rashed
`1.
`Rashed describes “semiconductor devices formed in and above a
`continuous active region and a conductive isolating structure formed above
`the active region between the devices.” Ex. 1005, 1:13–15.
`One example is shown in Figure 4A, which is reproduced below. As
`shown, the source regions of adjacent transistors are coupled to power
`rail 140H by conductive structures 144 (in yellow). See Ex. 1001, 6:21–36.
`
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`Isolating electrode 150PG (in orange) is positioned between adjacent source
`regions of the continuous active region, and is also connected to the power
`rail. See id., 5:17–20, 6:21–36. Gate structures 130 (in green) are formed
`across the active region between the source regions and corresponding drain
`regions. See id. 4:60–66.
`
`Figure 4A of Rashed is a schematic depiction of an exemplary
`semiconductor device. See Ex. 1001, 3:29–31.
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`Nauta
`2.
`Nauta is an article describing “CMOS circuits for integrated analog
`filters at very high frequencies.” Ex. 1007, Abstract. In pertinent part, it
`describes a common-mode voltage inverter circuit, shown in Fig. 2(b), in
`which the gates of both the PFET and NFET of the inverter are tied to the
`drains of both the PFET and NFET. See Ex. 1003 (Liu Decl.) pp. 56–58.
`
`F.
`
`Grounds of Unpatentability
`This trial was instituted on the following grounds:
`
`Reference(s)
`Rashed
`Rashed
`Rashed, Lu
`Rashed, Nauta
`
`35 U.S.C. § Claim(s) Challenged
`102
`1–3, 5, 8, 9, 12–14, 16–19
`103
`1–3, 5, 8, 9, 12–14, 16–19
`103
`4, 15, 20
`103
`10
`
`II. ANALYSIS
`
`We discuss below the level of skill in the art, claim construction,
`antedating Rashed and Lu, the patentability of the present claims.
`
`A.
`
`Level of Ordinary Skill in the Art
`Petitioner asserts that a person of ordinary skill in the art “would have
`had a Master’s of Science Degree (or a similar technical Master’s Degree, or
`higher degree) in an academic area emphasizing electrical engineering or
`computer engineering with a concentration in semiconductors or,
`alternatively, a Bachelors Degree (or higher degree) in an academic area
`emphasizing electrical or computer engineering and having two or more
`years of experience in integrated circuit design and/or semiconductor
`
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`processing.” Pet. 10–11. Petitioner adds that “[a]dditional education in a
`relevant field, such as computer engineering, or electrical engineering, or
`industry experience may compensate for a deficit in one of the other aspects
`of the requirements stated above.” Id. at 11.
`Patent Owner asserts that a person of ordinary skill in the art “would
`have had (a) a Bachelor’s of science degree in an engineering discipline or
`physics, or a closely-related field, and at least two years of work or research
`experience in the field of semiconductor design or fabrication, or (b) a
`Master’s of science degree in an engineering discipline or physics, or a
`closely related field, and at least one year of work or research experience in
`that same field.” PO Resp. 5 (citing Ex. 2002 ¶¶ 33–36).
`Although the parties do not agree on the correct formulation, neither
`argues why theirs is superior or that the selection of one or the other makes a
`difference in the outcome of this case. Under these circumstances, we adopt
`Petitioner’s characterization of the level of ordinary skill in the art, which we
`find to be generally consistent with the disclosures of the patent and the cited
`prior art.
`
`B.
`
`Claim Construction
`In inter partes reviews filed before November 13, 2018, such as this
`one, claims of an unexpired patent are interpreted according to their broadest
`reasonable construction in light of the specification of the patent in which
`they appear. See 37 C.F.R. § 42.100(b) (2017); Cuozzo Speed Techs., LLC
`v. Lee, 136 S. Ct. 2131, 2142–46 (2016); 83 Fed. Reg. 51,340. Under that
`standard, claim terms are generally given their ordinary and customary
`meaning, as would have been understood by one of ordinary skill in the art
`in the context of the entire disclosure. See In re Translogic Tech., Inc.,
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`504 F.3d 1249, 1257 (Fed. Cir. 2007). We address below the terms that at
`least one party identified as requiring construction.
`
`1.
`
`“means for coupling the gate-directed local
`interconnect to the third gate layer”
`Claim 17 recites “means for coupling the gate-directed local
`interconnect to the third gate layer, wherein the gate-directed local
`interconnect and the means are both located between the semiconductor
`substrate and an adjacent lower-most metal layer.” The Petition argued that
`“[t]he ‘means’ in ‘means for coupling’ encompasses a ‘diffusion-directed
`local interconnect.’” Pet. 13 (citing Ex. 1001, 5:62–64, 6:36–38, 7:9–12;
`Figs. 4A, 4B, 5A, 5B).
`Patent Owner asserts that “[i]n the co-pending litigation, Petitioner
`agreed to a proper identification of corresponding structure as: ‘a diffusion-
`directed local interconnect as described at 7:8–12, Fig. 4A, 3:9–14, Fig. 4B,
`3:15–19, 7:12–16, 5:62–64, 6:36–39, 8:9–11, 2:48–52, Figs. 5A, 5B, 6A,
`7A, or 7B, and equivalents thereof.’” PO Resp. 6 (citing Ex. 2001, 26–28).
`Patent Owner argues that “[f]or each corresponding structure, the diffusion-
`directed local interconnect—and the diffusion-directed local interconnect
`alone—performs the claimed function” and that “[n]one of the diffusion-
`directed local interconnects rely upon other structures, for example an
`intermediate connection, to complete the physical connection between the
`gate-directed local interconnect or gate layer.” Id. at 6–7 (citing Ex. 1002
`¶ 42).
`Petitioner’s Reply does not address this issue, and we agree with
`Patent Owner that the corresponding structure is a diffusion-directed local
`interconnect as described in the ’418 patent at 7:8–12, 3:9–14, 3:15–19,
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`7:12–16, 5:62–64, 6:36–39, 8:9–11, 2:48–52 and shown in Figs. 4A, 4B, 5A,
`5B, 6A, 7A, and 7B, as well as equivalents thereof. We note that neither
`party has addressed the scope of the “equivalents thereof.”
`
`“configured to” and “forming . . . to”
`2.
`Patent Owner argues that “the phrase ‘configured to’ in claim 1
`should be construed as ‘requiring structure designed to or configured to
`accomplish the specified objective, not simply that they can be made to
`serve that purpose.’” PO Resp. 7. According to Patent Owner, the Federal
`Circuit has explained that “configured to” requires that the claimed
`structures “are designed or configured to accomplish the specified objective,
`not simply that they can be made to serve that purpose.” PO Resp. 8 (citing
`Aspex Eyewear, Inc. v. Marchon Eyewear, Inc., 672 F.3d 1349 (Fed. Cir.
`2012)). Patent Owner further argues that, for similar reasons, “the ‘forming
`. . . to’ language of Claim 12 should be given the same interpretation.” Id.
`Petitioner does not address this issue, and we agree with Patent Owner
`that, on this record, “configured to” and “formed to” mean that the structure
`is designed or constructed to accomplish the specified objective. Cf. In re
`Giannelli, 739 F.3d 1375, 1379 (Fed. Cir. 2014) (distinguishing between
`“configured to” and “capable of” or “suitable for”). As explained below,
`however, we do not agree with Patent Owner that this interpretation
`distinguishes the claims over Rashed.
`
`“diffusion-directed local interconnect”
`3.
`Patent Owner contends that “[i]n the litigation, Patent Owner and
`Petitioner agreed that [‘diffusion-directed local interconnect’] means: ‘a
`local interconnect that has a polygonal footprint with a longitudinal axis that
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`is parallel to the longitudinal axes of the polygonal footprints of the
`diffusion regions.’” PO Resp. 10 (citing Ex. 2001, 21, 31).
`Petitioner does not respond to Patent Owner’s argument, and, finding
`Patent Owner’s proposed construction consistent with the definition in the
`Specification (see Ex. 1001, 4:39–43), we adopt it.
`
`4.
`
`“first gate layer for the second
`transistor to a power supply node”
`Patent Owner argues that claim 5 “includes an obvious typographical
`error in the phrase ‘first gate layer for the second transistor’ and would be
`readily understood by a POSITA as ‘first gate layer for the blocking
`transistor.’” PO Resp. 10 (citing Ex. 2002 ¶ 43). Patent Owner asserts that
`claim 2, “from which claim 5 depends, provides antecedent basis for claim 5
`and states that ‘the first gate layer comprises a gate for a blocking transistor’
`and “also recites an ‘adjacent second transistor,’ that is therefore not the
`same as the ‘blocking transistor.’” Id. Petitioner responds that “a Patent
`Owner Response is not the proper vehicle for such a corrective amendment,”
`which should instead be pursued in a Motion to Amend. Pet. Reply 26.
`Given that the parties both acknowledge the claim is defective as
`written,2 that Patent Owner’s proposed “construction” reflects a change
`more appropriately pursued by other means, such as a certificate of
`correction or motion to amend, and that neither party offers thorough
`analysis or argument as to how or why this claim should, or should not, be
`
`2 See, e.g., Pet. 39–40 (“[T]he phrase ‘first gate layer for the second
`transistor,’ in claim 5 is inconsistent with claim 2, and therefore should not
`be given patentable weight.”); PO Resp. 10 (acknowledging the “obvious
`typographical error”).
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`construed as Patent Owner proposes, we conclude that we are not able to
`construe claim 5 on this record. We further determine that “the proper
`course for [us] to follow” under these circumstances is to “conclude that [we
`cannot] reach a decision on the merits with respect to whether petitioner had
`established the unpatentability” of claim 5. Samsung Elecs. Am., Inc. v.
`Prisua Engr. Corp., 948 F.3d 1342, 1353 (Fed. Cir. 2020); see In re Steele,
`305 F.2d 859, 862 (Cust. & Pat. App. 1962) (explaining that prior art
`rejections should not be based on “speculation as to meaning of the terms
`employed and assumptions as to the scope of such claims”). Petitioner,
`therefore, has not met its burden to demonstrate, by a preponderance of the
`evidence, that claim 5 unpatentable.
`
`C.
`
`Antedating Rashed and Lu
`Patent Owner argues that “[t]he inventors’ invention of [claims 1, 2, 4,
`5, 8, 12, 13, 15–18, and 20] antedates both Rashed and Lu.” PO Resp. 11.3
`In particular, Patent Owner argues that the inventors conceived of the
`subject matter of these claims “no later than January 17, 2012” and that they
`“were reduced to practice no later than June 28, 2012 through fabrication
`and testing of a test chip embodying the [claimed subject matter].” Id.
`
`1.
`
`Sufficiency of Patent Owner’s
`Conception Evidence
`An inventor can swear behind a reference by proving conception of
`the invention before the effective filing date of the reference and diligent
`
`3 Patent Owner does not seek to antedate challenged claims 3, 9, 10, 14, and
`19, and we consider patentability of those claims in light of Rashed and Lu
`in Section II.D. Due to the claim construction problem, we do not consider
`whether claim 5 can antedate the references.
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`reduction of the invention to practice after that date. See Apator Miitors ApS
`v. Kamstrup A/S, 887 F.3d 1293, 1295 (Fed. Cir. 2018) (citing Perfect
`Surgical Techniques, Inc. v. Olympus Am., Inc., 841 F.3d 1004, 1007 (Fed.
`Cir. 2016)). “[W]hen a party seeks to prove conception through an
`inventor’s testimony,” however, “the party must proffer evidence, ‘in
`addition to [the inventor’s] own statements and documents,’ corroborating
`the inventor’s testimony.” Apator Miitors, 887 F.3d at 1295 (quoting
`Mahurkar v. C.R. Bard, Inc., 79 F.3d 1572, 1577 (Fed. Cir. 1996)).
`Patent Owner offers testimony by “[i]nventors Giridhar Nallapati and
`John Zhu . . . that by January 17, 2012, the inventors had a definite and
`permanent idea of the complete and operative invention disclosed in the
`’418 Patent.” PO Resp. 12 (citing Ex. 2060 (Nallapati Declaration) ¶¶ 2–3;
`Ex. 2061 (Zhu Declaration) ¶¶ 2–3).
`Patent Owner further argues that the inventor testimony “is
`corroborated by a January 17, 2012 GDS file,” named “qptc20_1t_top_
`fill_no215_20120117.gds.gz,” corresponding to “a test chip known as
`QPTC20_1T, which contains a test device known as ‘Device Under Test 16’
`(‘DUT 16’) embodying the invention disclosed in the ’418 Patent.” PO
`Resp. 12 (citing Ex. 2060 ¶¶ 4, 77–107; Ex. 2061 ¶¶ 4, 41–71; Ex. 2002
`(Lall Decl.) ¶¶ 44–67). Patent Owner contends that “DUT 16 contains
`multiple repetitions of structures known internally as ‘MP over OD’ or
`‘Continuous OD’” and that “DUT 16 embodies all elements” of the subject
`claims. PO Resp. 12.
`According to Patent Owner, “[t]he date of the GDS file
`‘qptc20_1t_top_fill_no215_20120117.gds.gz’ is verified in four ways”: (1)
`“multiple declarants testify that the file name itself—here ‘20120117’—
`
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`indicates the finalization date of the file based on Qualcomm’s naming
`convention practice,” (2) “page 1 of [Ex. 2005] and page 1 of [Ex. 2006] are
`screenshots that show the Qualcomm file server where the file is stored
`showing the last modified date as 9 am January 18, 2012,” (3) Ex. 2010 “is a
`contemporaneous e-mail from the project lead Dr. Frank (Bin) Yang stating
`‘the final version QTC20_1T taped out to TSMC has been completed on
`Tuesday, Jan. 17th 2012,’ which Dr. Yang testifies is accurate and refers to
`[the] GDS file,” and (4) Ex. 2007 is “screenshots showing submission of the
`same file through Qualcomm’s Tapeout Manager Program with a date stamp
`of January 17, 2012.” PO Resp. 12–13 (citing Ex. 2060 ¶¶ 7, 112; Ex. 2061,
`¶¶ 7, 76; Ex. 2062, ¶¶ 7–9, 58–62; Ex. 2010, 1–2; Ex. 2007, 1, 8).
`Petitioner argues that Patent Owner “relies on uncorroborated
`testimony from the inventors of the ’418 patent . . . to support its allegation
`that the [claimed subject matter was] conceived prior to the effective dates
`of Rashed and Lu,” that “such uncorroborated inventor testimony is
`insufficient to show conception,” and that “thus [Patent Owner]’s argument
`fails.” Pet. Reply 6.
`Petitioner also argues that Patent Owner “fails to identify any
`evidence to corroborate that Nallapati and Zhu alone were, in fact, the
`individuals that conceived of the alleged invention.” Id. at 7 (emphasis
`omitted). Petitioner contends that Patent Owner “does not allege that any
`information in the ‘January 17, 2012 GDS file,’ or any other evidence of
`record in the present proceeding, shows that Nallapati and Zhu were the
`individuals that conceived of the subject matter in the January 17, 2012 GDS
`file.” Id. at 8 (emphasis omitted).
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`Petitioner further argues that “[t]he screenshots in Ex. 2006, which
`were created by Dr. Zhu, are uncorroborated inventor testimony, and are
`thus insufficient to support a showing of conception.” Pet. Reply 9.
`Petitioner argues that “[b]y selecting which layers were visible and invisible
`[in the screenshots], Dr. Zhu effectively provides testimony directing
`viewers to key features from the GDS file” and “[t]hus, the screenshots in
`Ex. 2006, which were created by Dr. Zhu, an inventor, specifically for the
`purposes of Qualcomm’s swear-behind argument, should be treated as
`inventor testimony.” Id. at 10.
`We are not persuaded by Petitioner’s arguments. The “rule of reason”
`analysis applied to corroboration “requires an evaluation of all pertinent
`evidence when determining the credibility of an inventor’s testimony” and,
`notably, “it is not necessary to produce an actual over-the-shoulder
`observer” and “sufficient circumstantial evidence of an independent nature
`can satisfy the corroboration requirement.” Cooper v. Goldfarb, 154 F.3d
`1321, 1330 (Fed. Cir. 1998).
`We find that the testimony of the two inventors is not
`“uncorroborated” because (a) the file provides corroboration of the
`testimony, (b) the file is dated and the date is corroborated in multiple ways,
`(c) the inventors’ testimony is confirmed by Dr. Yang, who is not an
`inventor, and the screenshots from the tapeout system, and (d) the testimony
`and documents are further verified Dr. Ranganathan, who also is not an
`inventor.
`It is true, as Patent Owner observes, that we have only the testimony
`of the inventors that it was they who actually conceived of the inventive
`structures, but such is frequently the case. The law does not require
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`independent, conclusive proof that the inventor is the one who had the
`mental spark of invention; rather, what is needed is “only that the
`corroborative evidence, including circumstantial evidence, support the
`credibility of the inventors’ story.” E.I. du Pont De Nemours & Co. v.
`Unifrax I LLC, 921 F.3d 1060, 1077 (Fed. Cir. 2019) (citing NFC Tech.,
`LLC v. Matal, 871 F.3d 1367, 1371 (Fed. Cir. 2017)). The cases do not
`require “that evidence have a source independent of the inventors on every
`aspect of conception and reduction to practice” as “such a standard [would
`be] the antithesis of the rule of reason.” E.I. du Pont De Nemours, 921 F.3d
`at 1077 (quoting Cooper, 154 F.3d at 1331); see NFC Tech., 871 F.3d at
`1372 (“[A]n inventor’s conception can be corroborated even though ‘no one
`piece of evidence in and of itself’ establishes that fact,” and “even through
`circumstantial evidence,” because “[a]t bottom, the goal of the analysis is to
`determine ‘whether the inventor’s story is credible.’”) (citations omitted).
`We find that the evidence offered by Patent Owner, as described
`above and in the declarations of non-inventors Yang and Ranganathan, is
`sufficient to support the inventor’s story of conception when viewed as a
`whole, and through the rule of reason lens.
`We also do not agree with Petitioner that the screenshots are “inventor
`testimony.” The screenshots are simply views of the large, complex GDS
`file that remove extraneous structures so that those corresponding to the
`claims can be viewed clearly. We see no practical difference between
`inventor Zhu removing irrelevant elements from the view of the file and an
`inventor directing one to a specific notebook, page, or other material. The
`evidence is the rendering showing the presence of the relevant structures in
`the file, which is not testimony. We also note that Petitioner received a copy
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`of the file, without any extraneous structures having been removed, and also
`had the opportunity to depose Mr. Zhu and reveal any errors in turning the
`GDS file into more accessible screenshots. See Tr. 40:6–7.
`As we are not persuaded by Petitioner’s argument that Patent Owner
`relies only on uncorroborated inventor testimony, we turn to whether the
`evidence reflects invention of the subject matter of claims 1, 2, 4, 8, 12, 13,
`15–18, and 20.
`
`Conceived Subject Matter
`2.
`Patent Owner explains that Ex. 2006 “contains screenshots taken by
`inventor Zhu of portions of ‘qptc20_1t_top_fill_no215_20120117.gds.gz’
`viewed in a GDS viewer” and that Ex. 2016B “contains images taken with a
`Transmission Electron Microscope (‘TEM’) showing cross-sections of the
`DUT 16 structure as fabricated in accordance with the GDS file.” PO
`Resp. 13–14 (citing Ex. 2061 ¶ 7; Ex. 2063 ¶ 8). According to Patent
`Owner, “as illustrated by [Ex. 2006] and [Ex. 2016B], the DUT 16 structure
`as specified in the January 17, 2012 GDS file for QPTC20_1T embodies all
`[of the subject] claims.” Id. at 14. The Patent Owner Response details how
`the structures in DUT 16 meet the limitations of claims 1, 2, 4, 8, 12, 13, 15–
`18, and 20. See PO Resp. 13–32; see also Ex. 2006 (GDS screenshots);
`Ex. 2016B (TEM images); Ex. 2002 (Lall Decl.) ¶¶ 44–67; Ex. 2060
`(Nallapati Declaration) ¶¶ 74–108; Ex. 2061 (Zhu Declaration) ¶¶ 38–72.
`We have reviewed and are persuaded by that analysis with respect to
`claims 1, 2, 4, 8, 12, 13, 15–18, and 20, which Petitioner does not dispute.
`Petitioner does dispute the analysis for claims 5 and 16, arguing that
`although Patent Owner “alleges that metal layer 2 is one of the layers that
`extends into the Vdd / Ground regions shown in teal on the far right on the
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`view above,” Petitioner’s “investigation of the January 17, 2012 GDS file
`reveals that this is not the case, and that metal layer 2 in fact does not contact
`these Vdd / Ground regions.” Pet. Reply 17. However, due to the claim
`construction problem, Petitioner is not able to prove claim 5 unpatentable
`(see Section II.B.4) and, as Patent Owner observes, “[c]laim 16 does not
`re