Trials@uspto.gov
`571-272-7822
`
`Paper No. 78
`Date: April 30, 2020
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICROSOFT CORPORATION,
`Petitioner,
`v.
`FG SRC LLC,
`Patent Owner.
`
`IPR2018-01600
`Patent 6,247,110 B1
`
`
`
`
`
`
`
`
`
`Before KALYAN K. DESHPANDE, JUSTIN T. ARBES, and
`CHRISTA P. ZADO, Administrative Patent Judges.
`ZADO, Administrative Patent Judge.
`
`
`
`
`
`JUDGMENT
`Final Written Decision
`Determining All Challenged Claims Unpatentable
`35 U.S.C. § 318(a)
`
`
`
`
`
`

`

`IPR2018-01600
`Patent 6,247,110 B1
`
`INTRODUCTION
`I.
`We have authority to hear this inter partes review under 35 U.S.C.
`§ 6. This Final Written Decision issues pursuant to 35 U.S.C. § 318(a) and
`37 C.F.R. § 42.73. For the reasons discussed herein, we determine that
`Microsoft Corporation (“Petitioner”)1 has shown, by a preponderance of the
`evidence, that claims 11, 12, 15, and 18–21 (“challenged claims”) of
`U.S. Patent No. 6,247,110 B1 (Ex. 1001, “the ’110 patent”) are
`unpatentable. See 35 U.S.C. § 316(e) (2012); 37 C.F.R. § 42.1(d) (2017).
`Procedural History
`A.
`Petitioner filed a Petition for inter partes review of claims 1–7, 11, 12,
`15, and 18–21 of the ’110 patent. Paper 1 (“Pet.” or “Petition”). FG SRC
`LLC, (Patent Owner”)2 subsequently filed a Preliminary Response.
`Paper 14 (“Prelim. Resp.”). On February 19, 2019, the Board entered a
`decision instituting an inter partes review of all claims and all grounds
`presented in the Petition. Paper 20 (“Institution Decision” or “Inst. Dec.”).
`After institution, Patent Owner filed a Response to the Petition.
`Paper 37 (“Response” or “PO Resp.”). In the Response, Patent Owner states
`that it “surrenders challenged claims . . . 1–7 of the ’110 Patent.” PO
`Resp. 4. In addition, on February 11, 2020, Patent Owner filed a statutory
`disclaimer of claims 1–7 of the ’110 patent. Paper 75 (Notice of statutory
`disclaimer); Ex. 2170 (statutory disclaimer). Accordingly, claims 1–7 have
`
`
`1 Petitioner identifies only itself as a real party-in-interest to the Petition.
`Pet. 2.
`2 Saint Regis Mohawk Tribe, originally named as Patent Owner, assigned
`the ’110 patent to DirectStream, LLC on May 21, 2019. Paper 26, 1.
`DirectStream, LLC assigned the ’110 patent to FG SRC LLC on January 22,
`2020. Paper 72, 1. Patent Owner identifies only itself as a real party-in-
`interest to this proceeding. Id.
`
`2
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`IPR2018-01600
`Patent 6,247,110 B1
`been removed from this proceeding. Petitioner filed a Reply to Patent
`Owner’s Response. Paper 55 (“Reply”). Thereafter, Patent Owner filed a
`Sur-Reply to Petitioner’s Reply to Patent Owner’s Response. Paper 61
`(“Sur-Reply”).
`An oral hearing was held on February 3, 2019. A transcript of the
`hearing is included in the record. Paper 77 (“Tr.”).
`Related Matters
`B.
`The parties advise that the ’110 patent has been subject to, or relates
`to, the following district court proceedings: SRC Labs, LLC et al. v.
`Microsoft Corp., 2:18-cv-00321 (W.D. Wash.); and SRC Labs, LLC et al. v.
`Microsoft Corp., 1:17-cv-01172 (E.D. Va.). Pet. 3; Paper 4, 1. Patent
`Owner further advises the following proceeding may affect or be affected by
`this proceeding: SRC Labs, LLC and Saint Regis Mohawk Tribe v. Amazon
`Web Services, Inc. et al., 2:18-cv-00317 (W.D. Wash.). Paper 72, 1. Also,
`the following proceedings before the Board involve Petitioner and Patent
`Owner: IPR2018-01594, IPR2018-01599, IPR2018-01601, IPR2018-01604,
`and IPR2018-01605.
`
`The ’110 Patent
`C.
`The ’110 patent relates generally to a multiprocessor computer
`architecture incorporating multiple programmable memory algorithm
`processors (“MAP”) in a memory subsystem, wherein the MAP may
`comprise one or more field programmable gate arrays (“FPGAs”).
`Ex. 1001, code (57).
`The specification of the ’110 patent (“Specification”) describes
`general purpose computers, stating that they are flexible in that they can
`handle a variety of functions, but are slower than they would be if they were
`designed to handle only one particular function:
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`IPR2018-01600
`Patent 6,247,110 B1
`All general purpose computers are based on circuits that
`have some form of processing element. These may take
`the form of microprocessor chips or could be a collection
`of smaller chips coupled together to form a processor. In
`any case, these processors are designed to execute
`programs that are defined by a set of program steps. The
`fact that these steps, or commands, can be rearranged to
`create different end results using the same computer
`hardware
`is key
`to
`the computer's
`flexibility.
`Unfortunately, this flexibility dictates that the hardware
`then be designed to handle a variety of possible functions,
`which results in generally slower operation than would be
`the case were it able to be designed to handle only one
`particular function. On the other hand, a single function
`computer
`is
`inherently not a particularly versatile
`computer.
`Ex. 1001, 1:22–36. The Specification states, however, that several groups
`had begun experimenting with creating a processor out of electrically
`reconfigurable circuits. Id. at 1:37–39. According to the Specification, this
`would allow the processor to be configured to execute particular functions
`more quickly than a processor of a general purpose computer, thereby
`accelerating application program execution speeds. Id. at 1:39–47. The
`Specification states, however, that certain functions cannot be implemented
`well in a system comprising reconfigurable processors due to limitations on
`the circuit densities that can be achieved. Id. In addition, systems including
`such reconfigurable processors intended for the processors to operate alone,
`which would present problems in systems involving program applications
`that use several processors to solve a single problem. Id. at 1:47–51.
`To address these issues, the Specification states that the inventors
`“developed a Memory Algorithm Processor (‘MAP’) multiprocessor
`computer architecture that utilizes very high performance microprocessors in
`conjunction with user reconfigurable hardware elements.” Id. at 1:61–64.
`
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`IPR2018-01600
`Patent 6,247,110 B1
`In a preferred embodiment, the MAP may comprise a Field Programmable
`Gate Array (“FPGA”). Id. at 2:2–5. The Specification discloses,
`particularly, a computer system including a microprocessor and one or more
`FPGAs:
`Particularly disclosed herein is the utilization of one or
`more FPGAs to perform user defined algorithms in
`conjunction with,
`and
`tightly
`coupled
`to,
`a
`microprocessor. More particularly, in a multi-processor
`computer system, the FPGAs are globally accessible by all
`of the system processors for the purpose of executing user
`definable algorithms.
` Id. at 2:6–11 (emphasis added). However, the Specification also discloses,
`broadly, a computer including a data processor and a MAP
`Broadly, what is disclosed herein is a computer including
`at least one data processor for operating on user data in
`accordance with program instructions. The computer
`includes at least one memory array presenting a data and
`address bus and comprises a memory algorithm processor
`associated with the memory array and coupled to the data
`and address buses. The memory algorithm processor is
`configurable to perform at least one identified algorithm
`on an operand received from a write operation to the
`memory array.
`Id. at 2:37–46 (emphasis added).
`Figure 3 of the ’110 patent is reproduced below.
`
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`IPR2018-01600
`Patent 6,247,110 B1
`
`
`
`Figure 3 is a functional block diagram of a memory bank for an
`individual MAP of Figure 2
`Figure 3 illustrates a preferred representation of memory bank 120 in MAP
`system computer architecture 100 that includes representative MAP 112. Id.
`at 3:54–58. Memory bank 120 includes bank control logic block 122
`bi-directionally coupled to system trunk line bus 124 and to bi-directional
`data bus 126 and address bus 128. Buses 126 and 128 are coupled to
`memory array 130 and MAP assembly 112. MAP assembly 112 contains
`control block 132 and reconfigurable user FPGA 134, which are coupled to
`each other via signal lines 136. The Specification explains that bank control
`logic block 122 supplies an address on address bus 128 for accessing data at
`specified locations within memory array 130. Id. at 3:61–65. The
`Specification states that computer architecture 100 comprises multiple
`processors that use “uniform memory access across common shared memory
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`IPR2018-01600
`Patent 6,247,110 B1
`with one or more MAPs 112 located in the memory subsystem, or memory
`space.” Id. at 4:8–14.
`According to the Specification, by placing MAP 112 in the memory
`subsystem, or memory space, MAP 112 can be accessed readily though the
`use of memory read and write commands, in contrast with conventional
`implementations that propose placement of reconfigurable logic in or near
`the processor such that only one processor has rapid access to the logic. Id.
`at 4:36–39. In a conventional system, reconfigurable logic must be placed
`near every processor in a multiprocessor system, which increases overall
`system cost, according to the Specification. Id. at 4:39–41.
`Illustrative Claim
`D.
`Of the challenged claims, claim 11 is independent. Claim 11,
`reproduced below with labeled limitations, is illustrative.
`11. [a] a multiprocessor computer system comprising:
`[b] a plurality of data processors for executing at least one
`application program by operating on user data in
`accordance with program instructions;
`[c] a memory bank having a data bus and an address bus
`connected to said plurality of data processors;
`[d] a plurality of reconfigurable memory algorithm
`processors within said memory bank at plurality of
`individual memory addressable memory locations;
`[e] means coupling said plurality of individual memory
`algorithm processors to said data bus and to said address
`bus;
`[f] said plurality of reconfigurable memory algorithm
`processors being individually memory addressable by all
`of said plurality of data processors; and
`[g] said plurality of memory algorithm processors being
`individually configurable
`to perform an
`identified
`algorithm on an operand that is received from a write
`
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`IPR2018-01600
`Patent 6,247,110 B1
`operation by one of said plurality of data processors to said
`memory bank as said at least one of said plurality of data
`processors executes said at least one application program.
`Ex. 1001, 7:59–8:13 (letters and brackets added).
`Prior Art and Asserted Grounds of Unpatentability
`E.
`Petitioner raises the following challenges to claims 11, 12, 15, and
`18–21. Pet. 3–4.
`Claim(s) Challenged
`11, 12, 18–21
`11, 12, 15, 18–21
`11, 12, 15, 18–21
`15
`15
`11, 12, 15, 18–21
`11, 12, 15, 18–21
`15
`
`Reference(s)/Basis
`Halverson3
`Halverson
`Halverson, Splash24
`Halverson, Collins5
`Halverson, Collins, Splash2
`Halverson, Parkin6
`Halverson, Parkin, Splash2
`Halverson, Collins, Parkin
`
`35 U.S.C. §
`102(b)
`103(a)
`103(a)
`103(a)
`103(a)
`103(a)
`103(a)
`103(a)
`
`
`Petitioner relies on the declaration of Stephen Trimberger, Ph.D.,
`Ex. 1003, to support its contentions.
`II. ANALYSIS
`A. Motions to Exclude
`The party moving to exclude evidence bears the burden of proof to
`establish that it is entitled to the relief requested—namely, that the material
`
`
`3 Richard Peyton Halverson, Jr., Ph.D., “The Functional Memory Approach
`to the Design of Custom Computing Machines,” Ph.D. diss., University of
`Hawaii, 1994. Ex. 1005 (“Halverson”).
`4 Duncan A. Buell, Jeffrey M. Arnold, & Walter J. Kleinfelder, SPLASH2:
`FPGAS IN A CUSTOM COMPUTING MACHINE (1996). Ex. 1006 (“Splash2”).
`5 U.S. Patent 5,671,355, filed Sep. 13, 1996 and issued Sep. 23, 1997.
`Ex. 1007 (“Collins”).
`6 U.S. Patent 4,073,005, filed Jan 21, 1974 and issued Feb. 7, 1978.
`Ex. 1017 (“Parkin”).
`
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`IPR2018-01600
`Patent 6,247,110 B1
`sought to be excluded is inadmissible under the Federal Rules of Evidence.
`See 37 C.F.R. §§ 42.20(c), 42.62(a). For the reasons discussed below,
`Petitioner’s Motion is denied-in-part and dismissed-in-part, and Patent
`Owner’s Motion is denied-in-part and dismissed-in-part.
`Petitioner’s Motion to Exclude
`1.
`Exhibits 2077 and 2096
`a)
`Petitioner moves to exclude the declaration of one of the named
`inventors of the ’110 patent, Jon Huppenthal (Exhibit 2077), “in its entirety
`as not being relevant to any issue on which trial has been instituted, and for
`lacking foundation, containing hearsay, and/or causing undue prejudice.”
`Paper 62 (“Pet. Mot.”), 3–6. Petitioner additionally moves to exclude
`portions of “Mr. Huppenthal’s declaration (Ex. 2077 ¶¶ 80, 82–86) due to
`his refusal to answer questions concerning those portions of the declaration.”
`Id. at 1–3 (citing Paper 50, 7–8).
`Petitioner also moves to exclude a transcript (Exhibit 2096) of a
`deposition of Petitioner’s declarant, Scott Hauck, Ph.D., from a different
`inter partes review (IPR2018-01604) as “not being relevant to any issue on
`which trial has been instituted, for containing hearsay, and/or causing undue
`prejudice.” Id. at 6. Petitioner argues that allowing the transcript in the
`record would be “highly prejudicial as it presents itself with the indicia of
`expert testimony while being totally devoid from the necessary context of
`the matter from which it originates.” Id. Patent Owner’s declarant, Houman
`Homayoun, Ph.D, relies in his declaration on portions of Dr. Hauck’s
`deposition transcript (Ex. 2104 ¶¶ 154–160). Paper 65 (“PO Opp. Mot.”), 7.
`Petitioner’s Motion is dismissed as moot, as we do not rely on the
`material Petitioner seeks to exclude in a manner adverse to Petitioner in this
`Decision. As explained below, even if the testimony is considered, we are
`
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`IPR2018-01600
`Patent 6,247,110 B1
`not persuaded by Patent Owner’s arguments regarding the state of the art or
`alleged nonobviousness of the challenged claims, and Patent Owner has not
`shown proof of secondary considerations that would support a conclusion of
`nonobviousness. See infra Sections II.C–II.D.
`Exhibits 2063, 2065, 2067, 2069, 2071–2073, 2076, 2082–2088, 2090,
`b)
`2094, 2095, 2097–2103, 2105–2147, 2149, and 2162–2165
`Petitioner moves to exclude Exhibits 2063, 2065, 2067, 2069, 2071–
`2073, 2076, 2082–2088, 2090, 2094, 2095, 2097–2103, 2105–2147, 2149,
`and 2162–2165 as “not being relevant to any issues on which trial has been
`instituted, lacking foundation, and/or causing undue prejudice” because the
`exhibits were not discussed substantively and/or cited in Patent Owner’s
`Response and Sur-Reply. Pet. Mot. 7–8. Petitioner’s Motion is dismissed as
`moot, as we do not rely on the exhibits in a manner adverse to Petitioner in
`this Decision. We note that in evaluating Petitioner’s asserted grounds of
`unpatentability, we consider only substantive arguments made by the parties
`in their papers during trial (i.e., the Petition, Response, Reply, and
`Sur-Reply). To the extent a document is filed in the record but never
`discussed in a paper, there is no substantive argument pertaining to that
`document to consider.
`
`Exhibits 2089 and 2090
`c)
`Petitioner moves to exclude Exhibits 2089 and 2090 as cumulative of
`other exhibits on the grounds that they appear to be duplicates of
`Exhibits 2079 and 2080, respectively. Pet. Mot. 8. Petitioner’s Motion is
`dismissed as moot, as we do not rely on the exhibits in a manner adverse to
`Petitioner in this Decision.
`
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`IPR2018-01600
`Patent 6,247,110 B1
`
`Exhibits 2069 and 2076
`d)
`Petitioner moves to exclude Exhibits 2069 and 2076 as “not being
`relevant to any issues on which trial has been instituted.” Pet. Mot. 8.
`Petitioner explains these exhibits are publications that were introduced
`during cross-examination of Petitioner’s declarant, and argues they are
`irrelevant because they were not discussed or cited in Patent Owner’s
`Response or Sur-Reply. Id. at 8–9. Petitioner’s Motion is dismissed as
`moot, as we do not rely on the exhibits in a manner adverse to Petitioner in
`this Decision.
`
`Exhibits 2104 and 2148
`e)
`Petitioner moves to exclude paragraphs 40 and 133 of the declaration
`of Patent Owner’s declarant, Dr. Homayoun, (Exhibit 2104) which refer to
`Exhibits 2084 and 2077. Pet. Mot. 9. Petitioner also moves to exclude
`paragraphs 14, 156, 283, and 284 of the declaration of Patent Owner’s
`declarant, Steven Guccione, Ph.D. (Exhibit 2148), which refer to Exhibits
`2077 and 2095. Id. Because we do not exclude the exhibits to which
`Dr. Homayoun and Dr. Guccione refer in their declarations, and do not rely
`on the paragraphs Petitioner seeks to exclude in a manner adverse to
`Petitioner in this Decision, we dismiss as moot Petitioner’s Motion with
`respect to Exhibits 2104 and 2148.
`Patent Owner Response
`f)
`Petitioner moves to exclude portions of Patent Owner’s Response
`referring to exhibits that Petitioner seeks to exclude. Pet. Mot. 10. Patent
`Owner’s Response is a paper with attorney arguments, not evidence that
`
`11
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`IPR2018-01600
`Patent 6,247,110 B1
`may be excluded.7 Further, we do not exclude any of the exhibits referred to
`in the identified portions of the Response. Petitioner’s Motion is denied as
`to Patent Owner’s Response.
`Patent Owner’s Motion to Exclude
`2.
`a)
`Exhibits 1028, 1029, and 1030
`Patent Owner moves to exclude Exhibits 1028 and 1029 as
`unauthenticated under Federal Rule of Evidence 901. Paper 63 (“PO Mot.”),
`4–5. Patent Owner further moves to exclude exhibits 1028, 1029, and 1030
`as inadmissible hearsay under Federal Rule of Evidence 802, asserting
`Petitioner’s Reply cites to these documents to prove the truth of the technical
`matters disclosed therein. Id. at 5–6. Exhibits 1028 and 1029 are technical
`publications and Exhibit 1030 is a United States patent.
`Petitioner submits Exhibits 1028 and 1029 are self-authenticating
`under Federal Rule of Evidence 902(6) and/or 902(7) because “each contain
`an IEEE trade inscription, copyright symbol, and [International Standard
`Book Number (ISBN)].” Paper 64 (“Pet. Opp. Mot.”), 2–4 (citing Ericsson
`Inc. v. Intellectual Ventures I LLC, IPR2014-00527, Paper 41 at 12 (PTAB
`May 18, 2015) (IEEE publication authenticated under Fed. R. Evid.
`901(b)(4)); Liberty Mut. Ins. Co. v. Progressive Casualty Ins. Co.,
`CBM2012-00010, Paper 59 at 37 (PTAB Feb. 24, 2014) (IEEE article self-
`authenticated under Fed. R. Evid. 902(6)); ACCO Brands, Inc. v. PC
`Guardian Anti-Theft Prods., 592 F. Supp. 2d 1208, 1219 (N.D. Cal. 2008)
`(Macintosh Portable computers self-authenticated under Fed. R. Evid.
`
`
`7 Petitioner did not seek authorization to file a motion to strike Patent
`Owner’s Response. See Patent Trial and Appeal Board Consolidated Trial
`Practice Guide (Nov. 2019), 80–81, available at https://www.uspto.gov/
`TrialPracticeGuideConsolidated (“Trial Practice Guide”).
`
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`IPR2018-01600
`Patent 6,247,110 B1
`902(7) “because they are inscribed with the Macintosh Portable trade
`name”)). Petitioner also argues Exhibits 1028 and 1029 are authentic under
`Federal Rule of Evidence 901(b)(4) based on the totality of the
`circumstances, namely that the papers are consistent with other papers
`published by the IEEE and nothing suggests they are not what they purport
`to be. Id. at 3–4. Petitioner also argues the exhibits are authentic as ancient
`documents under Federal Rule of Evidence 901(b)(8). Id. at 4–5.
`Specifically, each exhibit is over 20 years old and meets the requirements of
`Federal Rule of Evidence 901(b)(8). Id.
`We agree with Petitioner that Exhibits 1028 and 1029 are
`self-authenticating under Federal Rules of Evidence 902(6) and 902(7), and
`that Exhibits 1028 and 1029 are ancient documents under Federal Rule of
`Evidence 901(b)(8) for the reasons stated by Petitioner. Pet. Opp. Mot. 2–5.
`As to Patent Owner’s assertion that Exhibits 1028, 1029, and 1030 are
`inadmissible hearsay, Petitioner responds that these exhibits are not offered
`for the truth of the matters asserted, but rather are offered to show the
`understanding of a person of ordinary skill in the art. Pet. Opp. Mot. 5–6.
`Patent Owner does not identify any particular “statement” in any of the
`exhibits that is being offered “to prove the truth of the matter asserted in the
`statement,” PO Mot. 5–6, and thus fails to meet its burden to prove
`inadmissibility as hearsay. See Fed. R. Evid. 801(c); 37 C.F.R. § 42.20(c).
`Accordingly, we deny Patent Owner’s Motion to Exclude Exhibits
`1028, 1029, and 1030.
`
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`IPR2018-01600
`Patent 6,247,110 B1
`Exhibit 10278, 106:7–110:25
`b)
`Patent Owner moves to exclude testimony from the deposition of one
`of the inventors of the ’110 patent, Mr. Huppenthal (Ex. 1027, 106:7–
`110:25), under Federal Rules of Evidence 401, 402, and 403, on the basis of
`“form” objections stated at the following pages and line numbers of the
`deposition transcript: 104:20, 104:25, 105:5, 105:10, 105:20, 106:17,
`107:13, 107:20, 108:19, and 109:6. PO Mot. 6–7. A motion to exclude
`“must identify the objections in the record in order and must explain the
`objections.” 37 C.F.R. § 42.64(c) (emphasis added). Patent Owner does not
`explain sufficiently its objections in the Motion to Exclude. Patent Owner
`vaguely asserts the deposing attorney’s questions were “vague and
`ambiguous because counsel introduces confusion regarding which particular
`computer system(s) he [was] asking about,” and “[t]he questions are also
`confusing because counsel does not specify any particular computer system
`or any particular patent claim in question.” PO Mot. 6. Patent Owner also
`asserts the questions are objectionable because they are tied to the scope of
`the patent claims, whereas Mr. Huppenthal was offered as a fact witness
`only. Id. at 6–7. Petitioner responds that the questions were neither vague
`nor confusing, and Mr. Huppenthal’s responses demonstrate he understood
`which computer systems and/or patent claim to which each question
`referred. Pet. Opp. Mot. 8–11. Petitioner responds further that questions
`about the challenged patent referred to statements in Mr. Huppenthal’s
`declaration about the patent, and therefore were within the scope of his
`declaration. Id. at 10–12.
`
`
`8 Patent Owner erroneously refers to Exhibit 1026, rather than to Exhibit
`1027.
`
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`IPR2018-01600
`Patent 6,247,110 B1
`Patent Owner’s Motion is dismissed as moot, as we do not rely on
`Exhibit 1027, 106:7–110:25, in a manner adverse to Patent Owner in this
`Decision.
`
`Exhibit 1032, 10:3–20:4
`c)
`Patent Owner moves to exclude testimony from Mr. Huppenthal’s
`second deposition (Exhibit 1032, 10:3–20:4) as not relevant under Federal
`Rules of Evidence 401, 402, and 403. PO Mot. 7–8. Patent Owner submits
`Petitioner relies on this testimony in the Reply to support its arguments
`regarding construction of the claim term “means coupling said plurality of
`individual memory algorithm processors to said data bus and to said address
`bus.” Id. According to Patent Owner, the questions posed to Mr.
`Huppenthal are objectionable because they were not “tied in any way to the
`disclosures of the patent specification,” and instead related to potentially
`undisclosed and/or proprietary implementation details of real-world
`production systems. Id. Petitioner responds that Patent Owner has failed to
`meet its burden to show the testimony it seeks to exclude is irrelevant,
`because the testimony relates directly to statements Mr. Huppenthal makes
`in his declaration. Pet. Opp. Mot. 11–12. According to Petitioner, the line
`of questioning to which Patent Owner objects relates specifically to the
`statement in Mr. Huppenthal’s declaration that “[w]ith the exception of some
`of the technology described in Patent 6076152 [the parent of the ’110
`patent], none of this new technology existed in the prototype system
`delivered to [] ORNL,” for which Mr. Huppenthal was asked “[w]hen you
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`IPR2018-01600
`Patent 6,247,110 B1
`say ‘some of the technology’ there, what technology are you referring to?”
`Ex. 1032, 5:8–6:5; Ex. 2077 ¶ 80.9
`Patent Owner’s Motion is dismissed as moot, as we do not rely on
`Exhibit 1032, 10:3–20:4, in a manner adverse to Patent Owner in this
`Decision. See infra Sec. II.C.5 (construction of the “means coupling” claim
`limitation).
`
`Exhibit 1033, 28:14–30:3
`d)
`Patent Owner moves to exclude deposition testimony from
`Dr. Homayoun (Exhibit 1033, 28:14–20:4) taken in a different inter partes
`review proceeding that Patent Owner asserts is not relevant because it
`involves a patent with a priority date different from that of the ’110 patent.
`PO Mot. 8–9. Patent Owner’s Motion is dismissed as moot, as we do not
`rely on Exhibit 1033, 28:14–20:4, in a manner adverse to Patent Owner in
`this Decision.
`
`Exhibits 1031 and 1035
`e)
`Patent Owner moves to exclude Exhibits 1031 and 1035 under Federal
`Rules of Evidence 401 and 402 on the grounds that they are not cited in any
`paper submitted by Petitioner or any declaration in this proceeding. PO
`Mot. 8–9. Patent Owner’s Motion is dismissed as moot, as we do not rely
`on the exhibits in a manner adverse to Patent Owner in this Decision. We
`note that in evaluating Petitioner’s asserted grounds of unpatentability, we
`consider only substantive arguments made by the parties in their papers
`
`
`9 Patent Owner submitted Mr. Huppenthal’s declaration as an exhibit in
`several related IPRs, not always as the same exhibit number. During the
`deposition, Petitioner’s counsel referred to Exhibit 2080—the exhibit
`number for Mr. Huppenthal’s declaration in a different IPR—which
`corresponds to Exhibit 2077 in this proceeding.
`
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`IPR2018-01600
`Patent 6,247,110 B1
`during trial (i.e., the Petition, Response, Reply, and Sur-Reply). To the
`extent a document is filed in the record but never discussed in a paper, there
`is no substantive argument pertaining to that document to consider.
`Exhibits 1032, 1033, 1034, 1035, and 1036
`f)
`Exhibits 1032, 1033, 1034, 1035, and 1036 each are deposition
`transcripts for declarants in this proceeding, including Mr. Huppenthal,
`Dr. Homayoun, and Dr. Guccione. Patent Owner moves to exclude “any
`uncited portion of each deposition testimony” under Federal Rule of
`Evidence 401, 402, and 403 on the grounds that Petitioner has failed to show
`that this testimony is relevant. PO Mot. 9. Patent Owner does not identify
`any specific testimony, and thus fails to meet its burden to show it is entitled
`to the relief it seeks. See 37 C.F.R. § 42.20(c). Furthermore, we note that
`broadly excluding all uncited testimony is unwarranted. For example,
`uncited testimony surrounding cited testimony may be considered to provide
`context for the cited testimony. Accordingly, we deny Patent Owner’s
`Motion as to these exhibits.
`Level of Ordinary Skill in the Art
`B.
`Petitioner asserts that a person of ordinary skill in the art in the field
`of the ’110 patent in the relevant time frame (1997) would have been a
`person with a Bachelor’s degree in electrical engineering, computer
`engineering, computer science, or in a related field, and would have had four
`years of experience with the design or use of FPGA based systems. Pet. 4.
`Petitioner asserts that, in the alternative, such a person would have had an
`advanced degree in one of those fields and two years of related experience.
`Id. at 4–5. Moreover, such a person, according to Petitioner, would have
`been knowledgeable about computer architectures and how FPGAs could be
`included in them. Id. at 5. Such a person also would have been
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`Patent 6,247,110 B1
`knowledgeable about software algorithms that could be implemented on
`FPGAs and how to configure FPGAs to carry out such implementation. Id.
`(citing Ex. 1003 ¶¶ 39–40).
`Patent Owner disputes Petitioner’s assessment of the level or ordinary
`skill in the art, but does not provide a proposed level of ordinary skill in the
`art that we should apply in this proceeding.10 PO Resp. 34–36. Patent
`Owner contends Petitioner’s assessment is incorrect because a person of
`ordinary skill in the art would not have had the detailed FPGA knowledge
`assumed by Petitioner’s definition. Id. Patent Owner further contends the
`technical problem the ’110 patent sought to address is in the field of High
`Performance Computing (“HPC”). Id. at 4–25. Concatenating the
`experience Petitioner argues an artisan would have had with Patent Owner’s
`assessment of the technical field, Patent Owner argues the result would have
`been a “mythical person” knowledgeable about both FPGAs and High
`Performance Computing. Id. at 34–36. According to Patent Owner, it
`would have been rare to find a person knowledgeable in both disciplines,
`and that any such person would have had more education and experience
`than that proposed by Petitioner. Id.
`Patent Owner’s assertions are unavailing. First, Patent Owner relies
`on the Declaration of Dr. Guccione to support its assertion that there were
`few engineers at the time of the ’110 patent who knew how to program
`
`
`10 Patent Owner’s declarant, Dr. Homayoun, agrees with “the level of
`education and skill” that a person of ordinary skill in the art would have
`according to Petitioner. See Ex. 2048 ¶ 17; Ex. 2104 ¶ 123. Dr. Homayoun
`also testifies that a person of ordinary skill in the art would have had
`knowledge of “the unique problems involved with designing reconfigurable
`computer systems and programming FPGAs and FPGA based systems.” Ex.
`2048 ¶ 17.
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`Patent 6,247,110 B1
`FPGAs to run software algorithms. PO Resp. 34–35 (citing Ex. 2148 ¶¶ 87,
`196–201). Dr. Guccione testifies, for example, that implementing
`algorithms in FPGAs (i.e., hardware) is more complex than implementing
`algorithms in software, and therefore requires a different skillset. Ex. 2148
`¶ 87. Dr. Guccione’s testimony, however, is at odds with what is reflected
`in the prior art of the period. See Okajima v. Bourdeau, 261 F.3d 1350,
`1355 (Fed. Cir. 2001); In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir.
`1995); In re Oelrich, 579 F.2d 86, 91 (CCPA 1978); Reply 13 (arguing
`numerous prior art references disclose computer architectures using FPGAs
`in a manner similar to that disclosed in the ’110 patent). For example,
`Halverson, a Ph.D. thesis by a doctoral student, describes programming
`FPGAs, therefore indicating Petitioner’s assessment of the education and
`experience required in the field of programming FPGAs is accurate. See
`generally Ex. 1005; also see generally Ex. 1006 (textbook about FPGA-
`based computing machines); Ex. 1007 (patent relating to a reconfigurable
`computer network interface device including FPGAs); Ex. 1028; Ex. 1029,
`486; Ex. 1030, code (57).
`Second, we find insufficient evidence that the level of ordinary skill in
`the art would have required specialized knowledge in the field of High
`Performance Computing. Patent Owner cites to portions of the ’110 patent
`that describe enhancing overall processing speed in a multiprocessor
`computer architecture incorporating a number of memory algorithm
`processors, but has not shown why these systems are HPC architectures,
`much less limited to being HPC architectures. PO Resp. 4–5. The ’110
`patent does not limit the invention to HPC, but rather more broadly states
`that “[t]he present invention relates, in general, to the field of computer
`architectures incorporating multiple processing elements. More particularly,
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`the present invention relates to a multiprocessor computer architecture
`incorporating a multiprocessor computer architecture incorporating a
`number of memory algorithm processors in the memory subsystem to
`significantly enhance overall system speed.” Ex. 1001, 1:15–21. The one
`mention of “high performance systems” in the ’110 patent describes using
`hundreds or even tens of thousands of processors to solve a single problem
`in a timely manner. Id. at 1:47–55. This description, however, is non-
`limiting, and indicates a shortcoming of high performance systems, namely
`that issues such as sharing a single copy of an operating system may a