:,I
`
`
`
`Edited by
`
`Qualcomm, Ex. 1013, Page 1
`
`

`

`DESIGN OF ·HIGH-PERFORMANCE
`MICROPROCESSOR CIRCUITS
`
`Anantha Chandrakasan
`Massachusetts Institute of Technology
`Cambridge, MA
`
`William J. Bowhill
`Compaq Computer Corporation
`Shrewsbury, MA
`
`Frank Fox
`Rambus Inc.
`Mountain View, CA
`
`•
`
`• .IEEE
`
`PRESS
`
`LIBRARY & iNFORMAT!ON CENTER
`EXANT QY<":T[r· 1c- H,lf-
`CON
`,) ..:., , lY.,,•, n'(v,
`NEWPORT BEACH, CA
`
`The Institute of Electrical and Electronics Engineers, Inc., New York
`
`Qualcomm, Ex. 1013, Page 2
`
`

`

`This book and other books may be purchased at a discount
`from the publisher when ordered in bulk quantities. Contact:
`IEEE Press Marketing
`Attn: Special Sales
`445 Hoes Lane
`P.O. Box 1331
`Piscataway, NJ 08855-1331
`Fax: + 1 732 981 9334
`For more information about IEEE Press products, visit the
`IEEE Online Catalog Store at http://www.ieee.org/ieeestore.
`
`© 2001 by the Institute of Electrical and Electronics Engineers, Inc.
`3 Park Avenue, 17th Floor, New York, NY 10016-5997
`All rights reserved. No part of this book may be reproduced in any form,
`nor may it be stored in a retrieval system or transmitted in any f!Jrm,
`without written permission from the publisher.
`Printed in the United States of America.
`10
`
`9
`
`8
`
`7
`
`6
`
`5
`
`4
`
`3
`
`2
`
`1
`
`ISBN 0-7803-6001-X
`IEEE Order No. PC5836
`
`Library of Congress Cataloging-in-Publication Data
`Design of high-performance microprocessor circuits / Anantha Chandrakasan,
`William J Bowhill, Frank Fox, editors.
`p. cm.
`Includes bibliographical references and index.
`ISBN 0-7803-6001-X
`1. Microprocessors - Design and construction. 2. Logic circuits. I. Chandrakasan,
`Anantha P. II. Bowhill, William J-III. Fox, Frank, 1952
`
`TK7895.M5 D47 2000
`621.3815-dc21
`
`00-036977
`
`Qualcomm, Ex. 1013, Page 3
`
`

`

`Section 6.4 Methods to Characterize and Address Variation
`
`105
`
`6.4 METHODS TO CHARACTERIZE AND ADDRESS
`VARIATION
`
`In this section we briefly examine the methodologies used to understand and address
`process variations such as those presented in the previous section. Many of these
`approaches are built on statistical modeling and mathematical optimization methods;
`however, in this section we seek only to overview these approaches, and other references
`should be consulted for mathematical details. Key elements of statistical circuit analysis
`overviewed here are (a) extraction of statistical device models; (b) sensitivity analysis to
`estimate the effect of variation sources; (c) worst-case methods to more carefully limit
`and study variation concerns in circuit designs; and (d) spatial modeling and mismatch
`analyses.
`
`6.4.1 Statistical Device Models
`From the perspective of circuit design, the parameters P, which characterize a
`process, are often the model parameters required to perform circuit simulation.
`Internal to a circuit simulator, the model parameters are used to express the dependence
`between quantities such as current, charge, and voltage. A simple example of a device
`model is the Spice Level-I MOSFET model:
`
`(61)
`
`W
`2
`Ids = µC 0x L _ AL ( Vgs - V,h)
`
`for O < Vgs - V,h < V ds
`
`for which P = { W, L, V,h, µ, AL, C0x}- Many of these quantities are not directly mea(cid:173)
`surable and must therefore be inferred from measurements of Ids versus Vgs and V ds·
`This inference process, called model parameter extraction is usually performed using a
`nonlinear least squares analysis (e.g., see [1] Chap. 6). Due to the fact that the model is
`only an approximation to reality, and because the minimization is performed with finite
`tolerances, the parameter estimate derived is subject to error.
`In addition to a nominal model fit, we need to characterize variations in P. This
`may be done by measuring a number of devices, performing parameter extraction on
`each set of measurements to get a population of parameters P, and using the population
`to estimate the statistics of P. 1 Based on these statistics, large numbers of hypothetical
`cases can be simulated to study the resulting variation in performance. Numerous
`difficulties in this approach exist, including computational costs, data collection
`requirements, and potentially large errors in performance estimates due to propagation
`of systematic device model fitting errors.
`The difficulty and high cost of getting reliable and accurate statistics for the model
`parameters result in a situation where (1) the parameter statistics are not updated often
`to reflect changes and maturation in the fabrication process; and (2) there is often a
`large incentive to use analysis and design methods that are less sensitive to the detailed
`
`1 There are a number of other approaches to solving this problem; see, for example [3], [8].
`
`Qualcomm, Ex. 1013, Page 4
`
`

`

`106
`
`Chapter 6 Models of Process Variations in Device and Interconnect
`
`statistics of P, hence the extensive use of worst-case analysis techniques (which we will
`discuss below). Nevertheless, a large number of other analysis techniques have been
`tried with various levels of success. More information on the various alternative statis(cid:173)
`tical analysis techniques can be found in [20], [14], and [4].
`
`6.4.2 Sensitivity Analysis
`In some cases, it is easier to characterize one set of parameters (perhaps related to
`geometric variation) than the resulting electrical or simulation model parameters. In
`such cases, one is concerned with the transmitted variability or propagation of variance
`from one parameter P through to another parameter Q, by way of a known analytic or
`numeric function/, where Q =J(P).
`In the case where J can only be evaluated numerically (e.g., in understanding the
`impact of some process variation such as an anneal temperature on resulting geometric
`structure), monte carlo or other sampling methods are often utilized [13]. In many
`cases, however, a simple sensitivity analysis approach is used through a first-order
`expansion of some analytical function J relating P and Q:
`
`Q+AQ =f(P+AP)
`
`AQ~ IZIAP
`
`(6.2)
`
`where AP and AQ are typically considered to be the standard deviations of parameters
`P and Q. While many functions do not preserve normality, it is often assumed that the
`small deviations of AQ can also be approximated by a normal distribution, so that the
`variance propagation is approximated as a~ ~ (of/ 8P) 2 a~. Given approximate var(cid:173)
`iance values for some set of process variations, the resulting first-order electrical impact
`of the variations on device or canonical circuits is often derived and compared for
`different circuit, layout, or other design rule options (as, for example, in Section 6.5.2).
`6.4.3 Worst-Case Analysis
`The various components of Pare usually correlated. For example, Fig. 6.3 shows a
`representative distribution of four MOS transistor model parameters from a modern
`0.25 µm process. The correlation structure of P is thus required for accurate statistical
`analysis. Ignoring the correlation, i.e., assuming it is zero, leads to statistical perfor(cid:173)
`mance estimates which are in reality extremely improbable and are overly pessimistic.
`Principal component analysis [12] is often used to transform highly correlated process
`parameters to a smaller set of uncorrelated parameters to simplify statistical design
`analysis.
`The most common method for analyzing the implications of random and corre(cid:173)
`lated variations is worst-case analysis [4]. Consider a circuit performance z (e.g.,
`clock speed) that is a function of model parameters P, expressed as z = J(P). Due to
`variations in P, the performance z is a random variable. The goal of worst-case analysis,
`like all other forms of statistical design analysis [14], is to determine a measure of
`goodness or quality of the design. The ideal such measure is the yield of the design,
`which is defined as the proportion of circuits that meet the specifications. Since com(cid:173)
`puting the function/ typically involves performing a computationally expensive circuit
`simulation, computing the yield directly is very expensive. Worst-case analysis is the
`
`Qualcomm, Ex. 1013, Page 5
`
`

`

`Section 6.4 Methods to Characterize and Address Variation
`..
`
`. . .. ... . .
`
`107
`
`. .
`..... ,.
`. . :
`
`. .
`
`. . . ...
`... . . ,. . .
`··-:.--,-~(: ·~
`•·:.,.,:• .. ~"\~" ~-.. -.,:~-
`..
`.. . . .
`
`•
`
`(cid:127) :
`
`.·,-~ ........
`
`.
`
`.. ·.e•
`(cid:127) 'JC._
`I ~ ••
`_,.,.
`I(cid:127)
`
`-. ••
`
`.
`. ,···
`.. . .. .
`. . :. ..
`.. . . . .
`
`. .(cid:173). .
`. . .. -~·
`:S~~~~
`. ...
`"~ i
`. ·, ._.
`----~· .. . . .
`(cid:127) \,ti •••• .,,,,,.....
`•
`. ·. • ..
`
`,r
`
`••
`
`•
`
`•
`
`"" •
`
`. ·:;. ... :\
`
`,,, .
`. ..
`. . :.• .. ·. .
`~.
`. . . . '
`\: . .
`.
`.. -.~ "\ ~-':"-::
`·-~~:·
`..... -
`. · ......
`=--·
`
`. ..
`.
`' .
`..
`. -s ..
`~,
`. . .
`. . . .,.
`~' ..
`• •
`•:-
`«
`""•~'!.•"
`. ·.:~~ ..
`r:r,,.•.(cid:127)
`• • •
`.
`~
`. .•. . .
`'
`. . . . .
`..
`
`•
`
`,I •
`
`• ••••••
`
`V,h
`
`V,h
`
`Figure 6.3 Distribution of transistor model parameters.
`
`standard method for indirect measurement of the yield by effectively finding the worst(cid:173)
`case bounds for the yield. Various methods also exist whose goal is to work backward
`to find the worst-case process parameters P wc ( or process "corners" for P) that assure
`that the required yield is achieved.
`The effort necessary for finding P wc is nontrivial, and in fact is greater than that
`required to compute the yield since it requires the complete statistics of the output para(cid:173)
`meter z. Fortunately, however, the same performance of two structurally similar circuits
`often exhibits similar sensitivity to the parameters P and therefore results in nearly
`identical worst-case parameters [4]. As a practical example, a library of ASIC cells can
`use one unique setting for worst-case parameters for each type of performance (e.g.,
`delay, power dissipation, or noise immunity). This practice is so prevalent, in fact, that
`it is standard practice for manufacturing organizations to specify several sets of model
`parameters which are the worst cases or corners for typical digital circuit performances.
`
`6.4.4 Spatial Variation Modeling and Mismatch
`In analog circuit design, substantial work has been done to understand and model
`issues in device matching [7]. Increasingly, device matching is also of concern in high(cid:173)
`performance digital subcircuits. Here we overview some of these variation issues and
`the approaches used to analyze or guard against them.
`
`Qualcomm, Ex. 1013, Page 6
`
`

`

`384
`
`Chapter 18 I/O and ESD Circuit Design
`logic to prevent them from coming on when the driver itself is pulling the bus low.
`Similar circuits can be used to protect the PMOS pull-up from stress when the pad rings
`below Vss·
`18.4.4 Level Shifting
`The cross-coupled circuit shown in Fig. 18.5 level shifts low voltage swing core
`signals to the higher voltage used by the off-chip drivers. Gates G 1/G2 operate from the
`core supply and cause transistors Nl/N2 to pull down the gate of either Pl or P2 to Vss·
`The gates of these transistors are the outputs of this circuit and are buffered with an
`inverter operating from the off-chip-driver supply. Transistors Nl and N2 may be
`cascoded if necessary to reduce voltage stresses.
`
`Off-chip-driver Vdd rail
`
`P2
`
`02
`
`N2
`
`Input
`
`GI
`
`Core logic V,. rail
`
`Pl
`
`Nl
`
`Figure 18.5 Level shifter used to cross power
`supply domains.
`
`18.5 IMPEDANCE MATCHING
`Ideally an off-chip driver is connected to a printed wiring board transmission line that is
`terminated at the load (the "far end" of the transmission line) in the transmission line's
`characteristic impedance. Such far-end termination is usually created with resistors ( or
`MOS transistors configured as resistors) and in various forms is often used in high
`performance. Impedance matching at the driving end of a transmission line can prevent
`(or at least mitigate) multiple round-trip reflections along the transmission line by
`absorbing the reflected energy. Reducing this energy is important for reducing the
`severity of crosstalk and intersymbol interference [10], [11]. However, the drive current
`of a simple CMOS off-chip driver can vary by as much as 2: 1 across process, and more
`than that if the operating temperature range is large. Such a variation makes it impos(cid:173)
`sible to exactly impedance match the driver to the transmission line. Series terminating
`resistors, located either on- or off-chip but electrically near the driver, can provide a
`tighter match. On-chip resistors are typically made from N+ or well and have a
`resistance variation of up to ±20%. This wide range is due to variations in sheet
`resistivity (usually held to about ±10%), dimensional errors in processing (delta-L
`and delta-W), resistance increases due to self-heating, and voltage-induced resistance
`changes. Surface mount resistors with a tolerance of ±2% or better are usually
`employed for off-chip termination. However, the superior tolerance will not be advan(cid:173)
`tageous unless the surface mount resistors are optimally placed on the printed wiring
`board, immediately adjacent to the micropackage.
`
`Qualcomm, Ex. 1013, Page 7
`
`

`

`Architectural
`
`. . :
`
`••
`
`•
`
`•
`
`. -
`
`.. I e I
`
`•
`• •
`
`•
`
`•
`
`• . -
`
`•
`
`•
`
`. -
`•
`
`• • •
`•
`
`•
`
`and dela -loc
`
`ISBN (cid:143)
`
`- 7803 - 6001 - X
`90000
`
`--... :
`
`. .
`
`9 780780 360013
`
`Qualcomm, Ex. 1013, Page 8
`
`