Paper No. 1
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________________
`
`QUALCOMM INC. AND QUALCOMM TECHNOLOGIES,
`INC.,
`
`Petitioners
`
`v.
`
`APPLE INC.,
`
`Patent Owner
`
`U.S. PATENT NO. 8,271,812
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`TITLE: HARDWARE AUTOMATIC PERFORMANCE STATE
`TRANSITIONS IN SYSTEM ON PROCESSOR SLEEP AND
`WAKE EVENTS
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`Issue Date: September 18, 2012
`
`PETITION FOR INTER PARTES REVIEW
`UNDER 35 U.S.C. § 312
`
`1
`
`Exhibit 2002
`Qualcomm v. Apple
`IPR2019-00322
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________________
`
`QUALCOMM INC. AND QUALCOMM TECHNOLOGIES,
`INC.,
`
`Petitioners
`
`v.
`
`APPLE INC.,
`
`Patent Owner
`
`U.S. PATENT NO. 8,271,812
`
`TITLE: HARDWARE AUTOMATIC PERFORMANCE STATE
`TRANSITIONS IN SYSTEM ON PROCESSOR SLEEP AND
`WAKE EVENTS
`
`Issue Date: September 18, 2012
`
`PETITION FOR INTER PARTES REVIEW
`UNDER 35 U.S.C. § 312
`
`1
`
`Exhibit 2002
`Qualcomm v. Apple
`IPR2019-00322
`
`
`
`TABLE OF CONTENTS
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`Page
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`Introduction ........................................................................................................ 1
`I.
`II. Mandatory Notices ............................................................................................. 3
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`III. Grounds for Standing Pursuant to 37 C.F.R. § 104(a) ...................................... 5
`IV.
`Statement of Precise Relief Requested for Each Challenged Claim ................ 6
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`V.
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`Reasons for the Relief Requested Under 37 C.F.R. §§ 42.22(a)(2) and
`42.104(b)(4) ........................................................................................................ 7
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`1.
`2.
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`A Person of Ordinary Skill in the Art ...................................... 14
`Construction of Claim Terms ................................................... 14
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`VI. Claims 8 and 9 of the ’812 Patent Are Unpatentable ..................................... 32
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`Independent Claim 8 ................................................................ 32
`Dependent Claim 9 .................................................................. 42
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`1.
`2.
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`TABLE OF CONTENTS
`(continued)
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`Page
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`Independent Claim 8 ................................................................ 47
`Dependent Claim 9 .................................................................. 57
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`Dependent Claim 9 .................................................................. 60
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`1.
`2.
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`1.
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`1.
`Independent Claim 8 ................................................................ 64
`2.
`Dependent Claim 9 .................................................................. 71
`VII. Conclusion ........................................................................................................ 71
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`I.
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`Introduction
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`Pursuant to 35 U.S.C. § 312 and 37 C.F.R. § 42.100 et seq., Qualcomm Inc.
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`and Qualcomm Technologies, Inc. (collectively, “Petitioners” or “Qualcomm”)
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`request inter partes review of claims 8 and 9 (the “Challenged Claims”) of U.S. Patent
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`No. 8,271,812 (“the ’812 Patent,” Ex. 1001), which is assigned to Apple, Inc. (“Patent
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`Owner” or “Apple”).
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`The ’812 Patent relates to an integrated circuit, such as a system on chip
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`(“SoC”), which includes one or more performance domains, with each domain having
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`one or more components. Ex. 1001 Abstract, 2:31–34, 3:29–47 and Fig. 1. Among
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`these components are processors, which can have “awake” and “sleep” performance
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`states. Id. at 1:35–47, 6:37–50. When a processor is awake, it is supplied with a
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`voltage and a clock signal, and can process instructions. Id.; see also Ex. 1002
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`(Declaration of Vijay K. Madisetti, Ph.D), ¶ 40. “In the sleep state, the processor is
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`idle (not executing instructions),” and power is conserved. Ex. 1001, 6:38–39; see
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`also id. at 1:35–47 (discussing clock and power gating); Ex. 1002, ¶ 41.
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`Components can have performance states that are related to whether a processor
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`is awake or asleep. As the ’812 Patent explains:
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`When the processors are in the sleep state, these other
`components need not be operating at such a high
`performance level. Similarly, when the processors are
`awakened from the sleep state, the performance level at
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`which the processors and other components need to operate
`to support the activities being performed by the system may
`be different than the performance level prior to the
`processor entering the sleep state.
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`Ex. 1001, 1:40–47. Accordingly, processors, other non-processor components, and
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`their performance domains may transition between “wake” and “sleep” performance
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`states depending on whether a processor is awake or asleep. Id.; Ex. 1002, ¶¶ 42–48.
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`The ’812 Patent further explains that in the prior art, “[t]he sleep/wake transitions of
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`the processors and other components are changed under software control.” Ex. 1001,
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`1:48–49. However, software control of power management and sleep/wake
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`transitions had purported drawbacks that limited the amount of power conserved and
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`performance of the device. Id. at 1:49–58.
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`The ’812 Patent is directed to “a power management unit (PMU) [that] may
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`automatically transition (in hardware) the performance states of one or more
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`performance domains in a system.” Ex. 1001, Abstract, 1:62–65. According to the
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`specification, “the power management unit may monitor the processor to detect that
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`the processor is entering the sleep state or has entered the sleep state,” and transition
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`performance domains to their “sleep” performance states. Id. at 2:3–5, 5:44–49, 9:39–
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`10:2 and Fig. 3 (steps 40, 42, and 44). “[T]he power management unit may [also] be
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`programmable with a second set of target performance states to which the
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`performance domains are to transition when the processor exits the sleep state,” when
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`the processor awakens, and transition performance domains to their “wake” state
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`performance states. Id. at 2:8–12, 5:44–49, 10:13–25 and Fig. 3 (steps 48, 50, and
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`52).
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`However, integrated circuits having different performance domains comprised
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`of processor and non-processor components were already well-known at the time the
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`application for the ’812 Patent was filed in April 2010. Furthermore, there is nothing
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`patentable about a power management unit configured to transition the performance
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`state of each performance domain when a processor transitions to or from a sleep or
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`wake state. These claimed features were disclosed in the prior art, including by U.S.
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`Patents and published applications to Mandelblat, Kurts, and Lint, none of which were
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`of record during the prosecution of the ’812 Patent, as well as by the Kang Patent,
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`which was of record but was not previously considered in view of any of Mandelblat,
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`Kurts, or Lint.
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`Because the Challenged Claims are unpatentable over the prior art, inter partes
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`review should be instituted, and the Challenged Claims should be cancelled.
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`II. Mandatory Notices
` Real Party in Interest (37 C.F.R. § 42.8(b)(1))
`Qualcomm Inc. and Qualcomm Technologies, Inc. are the real parties-in-
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`interest.
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` Related Matters (37 C.F.R. § 42.8(b)(2))
`The ’812 Patent and its related continuation patents (U.S. Pat. Nos. 8,443,216
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`and 8,656,196) are involved in the following pending litigation that may affect, or be
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`affected by, a decision in this proceeding: Qualcomm Inc. v. Apple Inc., Case No.
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`3:17-cv-1375 (S.D. Cal.) (“’1375 Case”).
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`Petitioners are filing IPR petitions directed to related continuation patents
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`claiming priority to the ’812 patent (U.S. Pat. Nos. 8,443,216 and 8,656,196)
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`concurrently with the filing of this petition.
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` Lead and Back-Up Counsel and Service Information (37 C.F.R.
`§ 42.8(b)(3) and (b)(4))
`Lead Counsel
`John A. Marlott, Reg. No. 37,031
`JONES DAY
`77 W. Wacker Dr.
`Chicago, IL 60601
`(312) 269-4236
`jamarlott@jonesday.com
`
`Back-up Counsel
`Matthew W. Johnson, Reg. No. 59,108
`JONES DAY
`One Mellon Center
`500 Grant Street
`Pittsburgh, PA 15219
`(412) 394-9524
`mwjohnson@jonesday.com
`John M. Michalik, Reg. No. 56,914
`JONES DAY
`77 W. Wacker Dr.
`Chicago, IL 60601
`(312) 269-4215
`jmichalik@jonesday.com
`Thomas W. Ritchie, Reg. No. 65,505
`JONES DAY
`77 W. Wacker Dr.
`Chicago, IL 60601
`(312) 269-4003
`twritchie@jonesday.com
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`Pursuant to 37 C.F.R. § 42.10(b), a Power of Attorney accompanies this
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`Petition. Please address all correspondence to lead and back-up counsel at the address
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`above. Qualcomm also consents to electronic service by email at the email addresses
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`listed above.
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`Fees (37 C.F.R. § 42.103)
`The undersigned representative of Petitioners authorizes the Board to charge
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`the $15,500 Petition Fee, as well as any additional fees, to Deposit Account 501432,
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`ref: 178774-680003. Two claims are being reviewed, so $15,000 in post institution
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`fees are due for a total of $30,500.
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`III. Grounds for Standing Pursuant to 37 C.F.R. § 104(a)
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`Petitioners certify that the ’812 Patent is available for inter partes review, and
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`that Petitioners are not barred or estopped from requesting inter partes review of the
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`Challenged Claims on the grounds identified in this Petition. Apple filed and served
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`its first amended answer and counterclaims in the ’1375 Case, first asserting
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`infringement of the ’812 Patent by Petitioners, on November 29, 2017. ’1375 Case,
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`ECF No. 97. This petition is being filed within one year of service of Apple’s first
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`amended answer and counterclaims, and shortly after the District Court issued a claim
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`construction order adopting certain of Apple’s positions regarding the breadth of the
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`’812 Patent’s claims.
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`IV. Statement of Precise Relief Requested for Each Challenged Claim
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`37 C.F.R. § 42.104(b)(1): Claims for Which Review Is Requested
`Petitioners request review and cancellation of claims 8 and 9 of the ’812 Patent
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`(the “Challenged Claims”).
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`37 C.F.R. § 42.104(b)(2): Statutory Grounds and Prior Art on
`Which the Challenge is Based
`Petitioners request inter partes review of the Challenged Claims on the grounds
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`set forth below and request that each of the Challenged Claims be found unpatentable
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`and cancelled. An explanation of how the Challenged Claims are unpatentable is
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`provided in the form of the detailed description that follows, indicating where each of
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`the claim elements can be found in the prior art. Additional explanation and support
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`for each ground of rejection is set forth in Ex. 1002 (Declaration of Vijay K. Madisetti,
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`Ph.D.), referenced throughout this Petition.
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`Ground
`Ground 1
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`Ground 2
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`Ground 3
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`Ground 4
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`’812 Patent Claims
`8 and 9
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`8 and 9
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`9
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`8 and 9
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`Basis for Rejection
`35 U.S.C. § 102 based on U.S. Patent Pub. No.
`US Patent Pub. No. 2007/0043965 to
`Mandelblat (“Mandelblat”)
`35 U.S.C. § 103(a) based on Mandelblat in view
`of U.S. Patent No. 7,363,523 (“Kurts”)
`35 U.S.C. § 103(a) based on Mandelblat in view
`of U.S. Patent No. 7,426,648 (“Lint”)
`35 U.S.C. § 103(a) based on Kurts in view of
`U.S. Patent No. 7,369,815 (“Kang”)
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`The ’812 Patent issued September 18, 2012 from U.S. Application No.
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`12/756,006 (“’006 App.”), filed April 7, 2010, and does not claim priority to any
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`earlier-filed U.S. patent application. Accordingly, the earliest date to which the ’812
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`Patent could claim priority (hereinafter the “earliest effective filing date”) is April 7,
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`2010.
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`Mandelblat was filed August 22, 2005, published February 22, 2007, and is
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`prior art under pre-AIA 35 U.S.C. §§ 102(a), (b), and (e).
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`Kurts was filed August 31, 2004, issued April 22, 2008, and is prior art under
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`pre-AIA 35 U.S.C. §§ 102(a), (b), and (e).
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`Lint was filed September 30, 2004 and issued September 16, 2008, and is prior
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`art under pre-AIA 35 U.S.C. §§ 102(a), (b), and (e).
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`Kang was filed February 24, 2004 and issued May 6, 2008, and is prior art
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`under 35 U.S.C. § 102(a), (b), and (e).
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`V. Reasons for the Relief Requested Under 37 C.F.R. §§ 42.22(a)(2) and
`42.104(b)(4)
` Overview of the ’812 Patent and its Technology
`The ’812 Patent is entitled “Hardware Automatic Performance State
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`Transitions in System on Processor Sleep and Wake Events.” Ex. 1001. As its title
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`suggests, the ’812 Patent is related to transitioning the performance states of
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`performance domains and their components in response to a processor’s going to sleep
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`or waking up. Id. at Abstract, 1:33–58.
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`The ’812 Patent is directed to reducing the amount of time required for portions
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`of a system (e.g., an integrated circuit), referred to as “performance domains,” to
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`transition to a different “performance state” when the processor enters or exits a sleep
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`state. Id. at Abstract. The ’812 Patent purports to resolve this problem by controlling
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`these performance state changes using a programmable hardware-based “power
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`management unit,” or PMU.
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`Figure 1, reproduced below, discloses “an integrated circuit (IC) 10” that
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`includes performance domains. Id. at 3:29–33.
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`In Figure 1, “[t]he integrated circuit 10 includes a set of performance domains
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`14A-14F. Each performance domain 14A-14F includes at least one component of the
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`integrated circuit 10, and a given performance domain may include more than one
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`component.” Id. 3:32–36. Further, certain performance domains may have specific
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`functionality and associated components. Id. at 3:41–47. Dividing components of a
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`chip into different performance domains, in which the operational characteristics
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`could be separately adjusted was already well-known as of April 2010. Ex. 1002, ¶
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`54.
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`“The integrated circuit 10 also includes a power management unit (PMU)
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`28 . . . .” Ex. 1001, 3:47–48. “The PMU 28 may be configured to control transitions
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`between performance states for the various performance domains 14A-14F.” Id. at
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`3:63–65. The PMU 28 may transition the performance states of one or more of the
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`performance domains 14A–14F in response to a processor either “entering a sleep
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`state” and going to sleep, or “exiting the sleep state” and “waking” up. Id. at 3:65–
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`4:8. “In one embodiment, the PMU 28 may detect that the processor 16A-16B is
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`entering/exiting the sleep state, and may cause corresponding transitions in the
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`performance domains.” Ex. 1001, 5:46–48. It was already well known in the art in
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`April 2010 that the performance of components (and performance domains) could be
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`adjusted corresponding to whether a processor was in a wake or sleep state. Ex. 1002,
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`¶ 55.
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`“A performance domain may be one or more components that may be
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`controlled by the PMU 28 as a unit for performance configuration purposes.” Ex.
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`1001, 4:14–16. “[T]he PMU 28 may be configured to establish a corresponding
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`performance state for each performance domain.” Ex. 1001, 4:16–18. “The
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`performance state may include any combination of performance characteristics for the
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`components in a corresponding performance domain.” Id. at 4:31–33. “A
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`performance characteristic may be any configurable setting for a component that
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`affects the performance of that component.” Id. at 4:33–35. For example, a
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`component’s clock frequency or supply voltage level may be a performance
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`characteristic of that component. Id. at 4:35–38. When the clock frequency or
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`operating voltage is changed, power consumption and the performance state of the
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`domain also changes. Id. at 4:63–66. “In the case of voltage and clock frequency
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`changes, the PMU 28 may communicate the new settings to the clock/voltage control
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`unit 32.” Id. at 5:59–61. The ’812 Patent discloses numerous other characteristics of
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`a component that may qualify as a performance characteristic and impact power
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`consumption. Id. at 4:35–62, 4:67–5:18. For example, the ’812 Patent expressly
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`discloses that cache memory size may be a performance characteristic. Id. at 4:40–42
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`(“For example, cache sizes in various caches may be a performance characteristic.”).
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`These features were also known in the prior art in April 2010. Ex. 1002, ¶ 56.
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`The PMU may include “one or more performance configuration registers 30.”
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`Ex. 1001, 3:48–49, Fig. 1 (PMU 28 including “Perf Config” registers). These registers
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`specify the performance states of different performance domains based upon the
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`“awake” and “sleep” states of a processor. “For example, performance states to be
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`used in the performance domains 14A–14F when the processor is in sleep state may
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`be specified in the performance configuration registers 30. Performance states to be
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`used when the processor 16A–16B exits the sleep state (awakens) may also be
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`specified” Ex. 1001, 5:52–57. One embodiment of the PMU’s performance
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`configuration registers is shown in Figure 2. See Ex. 1001, 7:38–9:24. In Figure 2,
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`“[t]he register set 30B may include a configuration for each performance domain, and
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`for the sleep state and the wake state.” Ex. 1001, 7:41–43. Programmable registers
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`that were set with and stored voltage, clock frequency, and other performance
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`characteristics were not new as of April 2010. Ex. 1002, ¶ 57. Further, the prior art
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`disclosed registers that could be programmed with a set of wake state values, and also
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`with a set of sleep state values, that are applied depending on whether a processor is
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`in its wake state or its sleep state. Id.
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`Figure 3 is “a flowchart . . . illustrating operation of one embodiment of the
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`PMU 28 and the clock/voltage control unit 32 to manage performance state transitions
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`in performance domains when a processor is entering or exiting a sleep state.” Ex.
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`1001, 9:25–29. As shown, when “[t]he PMU 28 . . . detect[s] that the processor is
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`entering (or is about to enter) the sleep state” (block 40), it will “load the sleep
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`performance state for each performance domain from the performance configuration
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`registers 30 (block 42).” Id. at 9:39–48. Those performance domains will then
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`“transition . . . to the new performance states (block 44).” Id. at 9:56–59. Similarly,
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`“[t]he PMU 28 may [also] detect that a processor is exiting the sleep state ( or is about
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`to exit the sleep state)” (block 48), after which it will “load the wake performance
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`state for each performance domain from the performance configuration registers 30
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`(block 50).” Ex. 1001, 10:13–20. Those performance domains will then
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`“transition . . . to the new performance states (block 52).” Ex. 1001, 10:23–25.
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`Applying wake and sleep state performance characteristic values (e.g., voltage,
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`frequency, memory size) based on whether a processor is awake or asleep was also
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`well-known in April 2010. Ex. 1002, ¶ 58.
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`The Prosecution History of the ’812 Patent
`As filed, Application No. 12/756,006 (“the ’006 Application”) included claims
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`1–20. Independent claim 12 (eventually issued as claim 8) recited an “apparatus”
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`comprising: “a plurality of components, each component included in one of a plurality
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`of performance domains”; and “a power management unit configured to establish a
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`performance state in each of the plurality of performance domains,” and “configured
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`to transition at least a first performance domain … to a first performance state
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`programmed into the power management unit responsive to a processor transitioning
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`to a different performance state.” Ex. 1007, p. 39. Dependent claim 14 depended
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`from original claim 12, and further recited that “the power management unit is
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`configured to transition each of the performance domains into a respective power state
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`programmed into the power management unit responsive to the processor
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`transitioning to the different performance state.” Id. at 40. Dependent claim 15
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`depended from claim 12, and recited that “the different performance state comprises
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`a wakeup state, wherein the processor is transitioning from a sleep state.” Id. at 40.
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`Dependent claim 16 depended from claim 15, and further recited that “the different
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`performance state is different from a prior performance state at which the processor
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`was operating prior to entering the sleep state.” Id. at 40.
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`On February 24, 2012, the Examiner rejected, among others, claims 12 and 14
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`“under [pre-AIA] 35 U.S.C. 102(b) as being anticipated by Kang et al., US Patent
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`Appl. Pub. No. 2005/0064829.” Id. at 52 (citing Ex. 1015, “Kang Application”).
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`Among other things, the Examiner stated that the Kang Application included “a power
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`management unit (power control unit 140)” configured to transition “each of the
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`performance domains into a respective power state programmed into the power
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`management unit” in response to a processor’s “entry into sleep or exit to wake
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`mode.” Id. at 53 (rejecting claims 12 and 14). The examiner objected to dependent
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`claim 16, finding it “would be allowable if rewritten in independent form … .” Id. at
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`59.
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`On May 16, 2012, the Applicants responded by amending the power
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`management unit of claim 12 as follows:
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`16
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`Id. at 114. Applicants stated, “[c]laim 12 has been amended to include the features of
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`claims 15 and 16, and thus is in condition for allowance.” Id. at 117. Original claim
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`12, as amended, was allowed and issued as claim 8. Id. at 127.
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`37 C.F.R. § 42.104(b)(3): Claim Construction
`1.
`A Person of Ordinary Skill in the Art
`Petitioners maintain that a person of ordinary skill in the art (“POSITA”) as of
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`April 7, 2010 would have had a bachelor’s degree in electrical engineering or
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`computer engineering and at least two years of experience in the field of integrated
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`circuit design or an equivalent combination of education, work, and/or experience in
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`this field. Ex. 1002 ¶ 22.
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`2.
`Construction of Claim Terms
`In this IPR, the claims of the ’812 Patent “shall be given the broadest reasonable
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`construction in light of the [’812 Patent’s] specification.” 37 C.F.R. § 42.100(b).
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`Because a district court applies a different standard, however, the claim constructions
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`presented in this petition do not necessarily reflect the constructions that Petitioners
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`believe should be adopted by a district court.
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`In the ’1375 Case, the District Court adopted certain of Apple’s claim
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`construction positions. Ex. 1013, pp. 8–9. Petitioners have submitted the District
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`Court’s claim construction decision for the Board’s consideration. Power
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`Integrations, Inc. v. Lee, 797 F.3d 1318, 1326–27 (Fed. Cir. 2015) (“The fact that the
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`board is not generally bound by a previous judicial interpretation of a disputed claim
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`term does not mean, however, that it has no obligation to acknowledge that
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`interpretation or to assess whether it is consistent with the broadest reasonable
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`construction of the term.”). Although Petitioners reserve the right to appeal or
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`otherwise challenge the District Court’s claim construction order, Petitioners request
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`that the Board in this IPR construe any claim terms at least as broad as the District
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`Court. See, e.g., Cisco Systems, Inc. v. Crossroads Systems, Inc., IPR2014-01463,
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`Final Written Decision, Paper 49 at 11–12 (PTAB, Mar. 16, 2016).
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`(a)
`“performance domain”
`In the ’1375 Case, Apple construed “performance domain” to mean “one or
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`more components that may be controlled as a unit or independently for performance
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`configuration purposes.” Ex. 1008, pp. 17–19; Ex. 1009, pp. 6–7; Ex. 1010, pp. 105–
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`110 (Markman hearing transcript); Ex. 1011 ¶¶ 25–30; Ex. 1012, pp. 41–44, 69–105,
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`122–129. In particular, Apple argued that components within the claimed
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`“performance domain” can be controlled “independently” by the power management
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`unit (“PMU”) and do not have to transition together from one performance state to
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`another. Ex. 1008, pp. 14–19; Ex. 1009, pp. 6–7; Ex. 1010, pp. 104–108; Ex. 1011
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`¶¶ 25–28; Ex. 1012, pp. 69–90, 137.
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`Apple’s construction allows for a performance domain to include components
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`that transition performance states independently, with each component having
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`different performance state characteristics (e.g., different clock frequencies and
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`operating voltages). Id. The District Court adopted Apple’s construction. Ex. 1013,
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`p. 8. Apple’s construction, as argued to the District Court, should be adopted in this
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`proceeding. Ex. 1002, ¶ 94.
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`(b)
`“power management unit”
`In the ’1375 Case, Apple proposed that “power management unit” does not
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`require construction, but that a PMU is any “hardware and/or software that causes a
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`performance domain to transition to a performance state.” Ex. 1008, pp. 19–22; Ex.
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`1009, pp. 7–9; Ex. 1010, pp. 128–135, 144–145, 159; Ex. 1011 ¶¶ 31–37; Ex. 1012,
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`pp. 56–67, 110–135. In particular, Apple argued that a PMU need not be implemented
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`only in hardware; instead, Apple argued a PMU may be either hardware, software, or
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`any combination of hardware and software. Id. The District Court ultimately
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`construed PMU to be hardware or the combination of hardware and software. Ex.
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`1013, pp. 8–9. Apple’s construction, as argued to the District Court, should be
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`adopted in this proceeding. Ex. 1002, ¶ 95.
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`(c)
`“establish a . . . performance state”
`In the ’1375 Case, Apple proposed that “establish a … performance state” does
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`not require construction or, if construed, should mean “set the . . . one or more
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`performance characteristics to the appropriate values for the performance state.” Ex.
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`1008, pp. 22–23; Ex. 1009, pp. 9–10; Ex. 1010, pp. 146–149; Ex. 1011 ¶¶ 38–42; Ex.
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`1012, pp. 123–144. In particular, Apple argued that a performance domain need not
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`actually transition from one performance state to another in order for the PMU to
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`“establish a . . . performance state” of that domain. Id. The District Court concluded:
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`(i) that “the word ‘establish’ is . . . consistent with Apple’s use of ‘set,’” (ii) that “the
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`explicit requirement that the PMU be configured to make this transition is separate
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`from the ‘establish’ requirement, and (iii) that the term should be construed
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`“according to its plain and ordinary meaning.” Ex. 1013, p. 9. Petitioners maintain
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`that the Board should construe this term according to its plain and ordinary meaning
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`as the District Court did and consistent with Apple’s proposed construction and
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`arguments. Ex. 1002, ¶ 96.
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`(d)
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`“a prior performance state at which the processor
`was operating prior to entering the sleep state”
`In the ’1375 Case, Apple construed this phrase to mean “the performance state
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`at which the processor was last operating before the transition to the sleep state
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`began.” Ex. 1008, pp. 23–25; Ex. 1009, p. 10; Ex. 1012 ¶¶ 43–48; Ex. 1013, pp. 144–
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`165. To narrow the disputed claim construction issues in the ’1375 Case, Petitioner
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`agreed to Apple’s proposed construction. Ex. 1010, pp. 127. Apple’s construction,
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`however, is not the broadest reasonable interpretation because it narrows the phrase
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`“a prior performance state” to the “last operating” state. Petitioners maintain that the
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`plain and ordinary meaning refers to “a performance state” (or states) at which the
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`processor “was operating” some time before the processor “enter[ed] the sleep state.”
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`This is consistent with the specification, which explains that the post-sleep
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`performance state of a processor or other components can differ from their pre-sleep
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`performance states. Ex. 1001, 8:13–23. This plain and ordinary meaning of the term
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`should be accepted as the broadest reasonable interpretation in this proceeding. Ex.
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`1002, ¶ 97.
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` Overview of the Prior Art
`(a) Mandelblat
`US Patent Pub. No. 2007/0043965 (“Mandelblat”) is titled “Dynamic memory
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`sizing for power reduction.” Ex. 1003. Mandelblat “relates to integrated circuits
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`and/or computing systems,” and in particular, to “power management of memory
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`circuits.” Id. at ¶ 2.
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`Like the ’812 Patent, Mandelblat is directed to the reduction in power
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`consumption in microprocessors. Id. at ¶¶ 4–5, 17. Mandelblat discloses a
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`microprocessor containing multiple processor cores (902, 904), Power Management
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`Logic (PML) (906), containing a “Memory PML” (907), and a Dynamically Sizeable
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`Memory (905).
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`In the Dynamically Sizeable Memory, certain memory cells may be selectively
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`enabled or disabled for purposes of power savings, by way “sleep devices.” Id. at
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`¶¶ 17–19, Figs. 1–2. The “sleep devices” are controlled by the PML, and specifically
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`the Memory PML. Id. Cache size is directly related to power usage—a larger cache
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`uses more power, a smaller cache uses less.
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`The Mandelblat Dynamically Sizeable Memory may be at a Minimum Cache
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`size, a maximum or Full Cache size, or it may be at some point in between, and may
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`expand or shrink between these sizes. Id. at ¶¶ 38, Fig. 12. In this way, the
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`Dynamically Sizeable Memory may be sized based on processor power state, usage,
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`or other factors. Id. at ¶ 65.
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`Of particular importance is Mandelblat’s disclosure of cache expansion and
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`contraction operations upon cores entering or exiting the C4 state, which is a sleep
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`state.1 Id. at ¶¶ 53, 58, Fig. 12. Upon entering the C4 state, the Dynamically Sizeable
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`1 Mandelblat discloses one embodiment that “includes features and functionality
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`according to the Advanced Configuration and Power Interface (ACPI) Standard.”
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`Ex. 1003, ¶ 34 (referencing ACPI Specification, Rev. 3.0, Sep. 2, 2004 (Ex.
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`Memory shrinks from the Full Cache size to a size no less than a pre-set “Minimum
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`Cache Size.” Id. at ¶¶ 47–48. This process may be completed for each core in the
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`processor until all cores have entered the C4 state and processor as a whole enters the
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`C4 state. Id. at ¶ 50. The cache maintains this Minimum Cache size while the cores
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`are in C4. Id.
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`Upon waking up and exiting the C4 state, Mandelblat discloses that the
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`Dynamically Sizeable Memory may initiate an expand operation responsive to the
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`“one or more of the core(s) transitioning to a different power state.” Id. at ¶¶ 52.
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`Mandelblat further discloses this expansion may be to a revised Minimum Cache size
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`rather than the Full Cache size. Id. at ¶ 58.
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`(b) Kurts
`U.S. Patent No. 7,363,523 (“Kurts”) is titled “Method and apparatus for
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`controlling power management state transitions.” Ex. 1004. Similar to the ’812
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`1014)). The ACPI Standard specifies power management performance “C states”
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`that may be supported by a processor and its cores. Ex. 1002 ¶ 45. “The C0 power
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`state is an active power state where the CPU executes instructions. The C1 through
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`Cn power states are processor sleeping states where the processor consumes less
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`power and dissipates less heat than leaving the processor in the C0 state.” Ex.
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`1014 § 8.1; see also id. §§ 2.5, 8; Ex. 1004 (“Kurts”), 1:18–33.
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`Patent, Kurts states the objective of power state management in computing devices,
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`and specifically reducing “entry/exit latencies” of processors that may prevent
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`processors from entering deeper sleep and conserving power. Id. at 1:46–2:5.
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`Kurts discloses a processor (205) with cores and an execution unit (210), as
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`well as Power Management Logic (234) to manage the performance state of the
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`processor, including frequency/voltage levels. Id. at 3:25–44. Within the Power
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`Management Logic is a Voltage ID Table (“VID Table”) (277). Id. at 4:13, 4:20–35.
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`The VID table is a lookup table for voltage/frequency pairs corresponding to various
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`operating points at which the processor may run. The Power Management Logic
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`(234) uses the values in this VID Table to exert control over the processor’s clock
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`generator (211) and voltage regulator (212), thereby controlling the processor’s
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`voltage and frequency. Id. at 3:25–33, 4:20–35, Fig. 3.
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`In addition to the Power Management Logic (234), Deeper Sleep Logic (270)
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`controls the processor’s entry into and exit from a deeper sleep state, referred to as
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`C4. Id. at 3:64–4:2. Power Management State Control Logic (242) controls the
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`processor’s power state, or C-state, placing it into various power states, referred to,
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`from most active to deepest sleep as C0, C1, C2, C3, and C4. Id. at 1:15–33, 4:49–
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`63. Working together, these three components, the Power Management Logic, the
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`Deeper Sleep Logic, and the Power Management State Control Logic control the
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