(12) United States Patent
`de Cesare et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 8.443.216 B2
`*May 14, 2013
`
`USOO8443216B2
`
`(54) HARDWARE AUTOMATIC PERFORMANCE
`STATE TRANSTIONS IN SYSTEM ON
`PROCESSOR SLEEP AND WAKE EVENTS
`
`(75) Inventors: Josh P. de Cesare, Campbell, CA (US);
`Jung Wook Cho, Cupertino, CA (US);
`Toshi Takayanagi, San Jose, CA (US);
`Timothy J. Millet, Moutain View, CA
`(US)
`Assignee: Apple Inc., Cupertino, CA (US)
`
`(73)
`(*)
`
`(21)
`(22)
`(65)
`
`(63)
`
`(51)
`
`(52)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`This patent is Subject to a terminal dis
`claimer.
`
`Appl. No.: 13/590,217
`Filed:
`Aug. 21, 2012
`
`Prior Publication Data
`US 2012/0317427 A1
`Dec. 13, 2012
`
`Related U.S. Application Data
`Continuation of application No. 12/756,006, filed on
`Apr. 7, 2010, now Pat. No. 8,271,812.
`
`Int. C.
`G06F I/00
`G06F L/26
`G06F 3/038
`G06F 3/00
`G09G 3/18
`GI IC5/14
`H04M I/00
`U.S. C.
`USPC ........... 713/300; 713/320; 713/323; 713/324;
`345/52; 34.5/211: 365/227; 455/574; 719/321
`
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`
`(58) Field of Classification Search .................. 713/300,
`713/320,323,324; 34.5/52, 211; 365/227:455/574;
`71.9/321
`See application file for complete search history.
`References Cited
`
`(56)
`
`EP
`GB
`
`U.S. PATENT DOCUMENTS
`4,344,132 A
`8, 1982 Dixon et al.
`5,813,022 A
`9/1998 Ramsey
`(Continued)
`FOREIGN PATENT DOCUMENTS
`O855718
`7, 1998
`2472050
`1, 2011
`OTHER PUBLICATIONS
`Combined Search and Examination Report in Application No.
`GB1105852.6 issued Aug. 1, 2011.
`(Continued)
`Primary Examiner — Stefan Stoynov
`(74) Attorney, Agent, or Firm — Lawrence J. Merkel:
`Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
`(57)
`ABSTRACT
`In an embodiment, a power management unit (PMU) may
`automatically transition (in hardware) the performance states
`of one or more performance domains in a system. The target
`performance states to which the performance domains are to
`transition may be programmable in the PMU by software, and
`software may signal the PMU that a processor in the system is
`to enter the sleep state. The PMU may control the transition of
`the performance domains to the target performance states,
`and may cause the processor to enter the sleep state. In an
`embodiment, the PMU may be programmable with a second
`set of target performance states to which the performance
`domains are to transition when the processor exits the sleep
`state. The PMU may control the transition of the performance
`domains to the second targeted performance states and cause
`the processor to exit the sleep state.
`24 Claims, 5 Drawing Sheets
`
`Power Supply 12
`
`Performance Domain :
`14A
`
`i
`
`Processor 1.6A
`
`Clk/Voltage
`Control 32
`
`14B
`
`
`
`- - - - - - - - - - - -
`Component 18
`
`Perf config
`
`Performance Domain
`14C
`
`} Performance Domain
`14D
`
`
`
`
`
`Graphics 20
`
`Performance Domain
`14E
`
`Qualcomm, Ex. 1001, Page 1
`
`

`

`US 8,443.216 B2
`Page 2
`
`U.S. PATENT DOCUMENTS
`10, 2000
`Thoulon
`6,128,747
`A
`6, 2001
`Lo et al.
`6,247,082
`B1
`1, 2003
`Nookala
`6,510,525
`B1
`3, 2003
`Bhatia et al.
`6,535,798
`B1
`12, 2003
`Ober
`6,665,802
`B1
`Cooper
`11, 2004
`6,823,516
`B1
`Kang et al.
`5/2008
`7,369,815
`B2
`1/2009
`Knebel et al.
`7,475,320
`B2
`Wyatt
`9, 2009
`7,590,473
`B2
`5, 2011
`Gunther et al.
`7,949,887
`B2
`Padhye et al. ..........
`9, 2011
`B2 *
`8,020,017
`11, 2011
`Gunther et al.
`8,069,358
`B2
`3, 2003
`Zilka
`2003, OO61383
`A1
`Agrawal et al.
`2, 2005
`2005.0024105
`A1
`Kang et al.
`3, 2005
`2005, OO64829
`A1
`Maejima
`11, 2006
`2006/02598OO
`A1
`6, 2007
`2007/O15O759
`Srinivasan et al.
`A1
`7/2007
`2007/0156370
`White et al.
`A1
`Nguyen
`10, 2007
`2007/0234O78
`A1
`Farad-rad et al.
`4, 2008
`2008/0094.109
`A1
`T/2008
`2008. O168285
`de Cesare
`A1
`
`T13,323
`
`2008/0307245 A1 12/2008 de Cesare
`2009, OO63715 A1
`3/2009 de Cesare
`2009, O144578 A1
`6/2009 Tatsumi
`2009/0204835 A1
`8/2009 Smith et al. ................... T13,323
`2009/0204837 A1
`8, 2009 Rawal
`2010, OO23792 A1
`1/2010 Tsuji
`2010, 0211700 A1
`8, 2010 de Cesare
`2011/0078463 A1* 3/2011 Fleming et al. ............... T13,300
`
`OTHER PUBLICATIONS
`International Search Report and Written Opinion from PCT/US
`1 1/31358, mailed Jun. 13, 2011, Apple Inc., 12 pages.
`Non-Final Office Action in related U.S. Appl. No. 13/006,967, issued
`Nov.30, 2012, pp. 1-17.
`Notice of Preliminary Rejection (Non-Final) from the Korean Intel
`lectual Property Office regarding Korean Patent Application No.
`10-2011-32365 K&C Ref: PE1 13022/SIG issued on Aug. 30, 2012,
`pp. 1-4.
`
`* cited by examiner
`
`Qualcomm, Ex. 1001, Page 2
`
`

`

`0SU.
`U.S. Patent
`tnetm
`
`24a1ym
`
`5f01
`
`US 8.443.216 B2
`2B61
`
`3M
`
`
`
`au‘ey62We2hMyMiach2_1Sph11:0.u0mmm.1wWmfAFek0a3wCCP100P
`9«I.WmM_
`U0,.m
`
`2qIIIIIIIIIIIIIIHHHHHWHHHIIIIIIIIIIIIIII
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`
`S
`
`Qualcomm, Ex. 1001, Page 3
`
`Qualcomm, Ex. 1001, Page 3
`
`

`

`U.S. Patent
`
`May 14, 2013
`
`Sheet 2 of 5
`
`US 8.443.216 B2
`
`PDO Wake State
`PD0 Sleep State
`PD1 Wake State
`PD1 Sleep State
`
`PDn Wake State
`PDn Sleep State
`Sleep Cmd
`
`
`
`
`
`NO
`
`Load Wake Performance State
`for Each Performance Domain
`
`Transition to New — 52
`Performance States
`
`
`
`Record Timestamp
`
`— 54
`
`Fig. 3
`
`Qualcomm, Ex. 1001, Page 4
`
`

`

`U.S. Patent
`
`May 14, 2013
`
`Sheet 3 of 5
`
`US 8.443.216 B2
`
`
`
`AppS, OS, Etc. 60
`
`Graphics
`Driver 62
`
`Audio
`Driver 64
`
`Network
`Driver 66
`
`Other
`Peripheral
`Drivers 68
`
`PMU
`Driver 70
`
`Device
`Activity
`Table 72
`
`Qualcomm, Ex. 1001, Page 5
`
`

`

`U.S. Patent
`
`May 14, 2013
`
`Sheet 4 of 5
`
`US 8.443.216 B2
`
`Start - PMU Driver
`
`80 —
`
`
`
`Device Enable/
`Disable Request?
`
`Yes
`
`Record Event in
`Device Activity Table
`
`
`
`Change in
`Performance
`State?
`
`u-86
`
`u-88
`
`- 90
`Invoke Transition
`
`
`
`
`
`
`
`
`
`Processor
`to Sleep?
`
`Determine Desired
`Sleep and Wake States
`Based on Device
`Activity Table
`
`Update Perf Config
`Regs if Applicable
`98 —s
`
`End - PMU Driver
`
`Qualcomm, Ex. 1001, Page 6
`
`

`

`U.S. Patent
`
`May 14, 2013
`
`Sheet 5 of 5
`
`US 8.443.216 B2
`
`
`
`Power Supply 156
`
`Integrated Circuit
`10
`
`External Memory
`158
`
`Peripherals
`154
`
`Computer Accessible Storage Medium 200
`
`Apps, OS, Etc. 60
`
`Graphics
`Driver 62.
`
`Audio
`Driver 64
`
`Network
`Driver 66
`
`Other
`Peripheral
`Drivers 68
`
`PMU
`Driver 70
`
`Device
`Activity
`Table 72
`
`Qualcomm, Ex. 1001, Page 7
`
`

`

`US 8,443,216 B2
`
`1.
`HARDWARE AUTOMATIC PERFORMANCE
`STATE TRANSTIONS IN SYSTEM ON
`PROCESSOR SLEEP AND WAKE EVENTS
`
`This application is a continuation of U.S. patent applica
`tion Ser. No. 12/756,006, filed Apr. 7, 2010 and now U.S. Pat.
`No. 8,271,812, which is incorporated herein by reference in
`its entirety.
`
`BACKGROUND
`
`10
`
`15
`
`25
`
`30
`
`35
`
`1. Field of the Invention
`This invention is related to the field of systems including
`processors and peripheral devices, and managing power con
`Sumption in Such systems.
`2. Description of the Related Art
`As the number of transistors included on an integrated
`circuit “chip' continues to increase, power management in
`the integrated circuits continues to increase in importance.
`Power management can be critical to integrated circuits that
`are included in mobile devices such as personal digital assis
`tants (PDAs), cell phones, Smartphones, laptop computers,
`net top computers, etc. These mobile devices often rely on
`battery power, and reducing power consumption in the inte
`grated circuits can increase the life of the battery. Addition
`ally, reducing power consumption can reduce the heat gener
`ated by the integrated circuit, which can reduce cooling
`requirements in the device that includes the integrated circuit
`(whether or not it is relying on battery power).
`Clock gating is often used to reduce dynamic power con
`Sumption in an integrated circuit, disabling the clock to idle
`circuitry and thus preventing Switching in the idle circuitry.
`Additionally, some integrated circuits have implemented
`power gating to reduce static power consumption (e.g. con
`Sumption due to leakage currents). With power gating, the
`power to ground path of the idle circuitry is interrupted,
`reducing the leakage current to near Zero.
`Clock gating and power gating can be effective power
`conservation mechanisms. However, in Some cases, these
`mechanisms are not as effective as desired. For example,
`systems that include processors can cause the processors to
`enter a sleep state to conserve power. While the processor is in
`the sleep state, other components in the system are still active,
`and often are operating at performance levels that Support the
`active processors. When the processors are in the sleep state,
`these other components need not be operating at Such a high
`45
`performance level. Similarly, when the processors are awak
`ened from the sleep state, the performance level at which the
`processors and other components need to operate to Support
`the activities being performed by the system may be different
`than the performance level prior to the processor entering the
`sleep state.
`The sleep/wake transitions of the processors and other
`components are changed under Software control. The Soft
`ware executes on the processors, and thus changing the per
`formance levels of the processors and other components can
`affect the amount of time required to execute the software.
`These effects impact the efficiency of the transition, impact
`ing the power conserved and the performance of the applica
`tion. Furthermore, the software execution time can affect how
`often the processor is transitioned to the sleep state, and the
`amount of reduced performance that can be tolerated in the
`rest of the system.
`
`40
`
`50
`
`55
`
`60
`
`SUMMARY
`
`In an embodiment, a power management unit may be con
`figured to automatically transition (in hardware) the perfor
`
`65
`
`2
`mance states of one or more performance domains in a sys
`tem. The target performance states to which the performance
`domains are to transition may be programmable in the power
`management unit by Software. Additionally, the Software may
`signal the power management unit that a processor in the
`system is to enter the sleep state. Alternatively, the power
`management unit may monitor the processor to detect that the
`processor is entering the sleep state or has entered the sleep
`state. The power management unit may be configured to
`control the transition of the performance domains to the target
`performance States, and may also cause the processor to enter
`the sleep state in Some embodiments. In an embodiment, the
`power management unit may be programmable with a second
`set of target performance states to which the performance
`domains are to transition when the processor exits the sleep
`state. The power management unit may be configured to
`control the transition of the performance domains to the sec
`ond targeted performance states and may also cause the pro
`cessor to exit the sleep state in Some embodiments.
`In one embodiment, the transition of the performance
`domains into different target states may be more rapid when
`controlled by the power management unit than may be pos
`sible with software control. Accordingly, the power conser
`Vation may be more efficient than a purely software-con
`trolled implementation, and the performance of applications
`executing in the system may also be positively affected. Addi
`tionally, the configureability of the performance states may
`permit more fine-grained control of the performance level in
`the system and thus may permit additional power savings. In
`Some cases, the performance states may be reduced further
`than would be possible in the software-controlled implemen
`tation, because the time required for the software to execute
`while the system is in the lower performance states is a
`reduced factor (or may even be eliminated).
`Each component of the system may be included in a per
`formance domain, and each performance domain may
`include at least one component but may include multiple
`components, in various embodiments. The power manage
`ment unit may be programmable with performance state iden
`tifiers for each performance domain, and for each hardware
`managed transition (e.g. into the sleep state, out of the sleep
`state, or both into and out of the sleep state, in various embodi
`ments). The sleep state of the processor may also be a perfor
`mance state, as may various other performance states that the
`processor may be programmed to in various embodiments.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The following detailed description makes reference to the
`accompanying drawings, which are now briefly described.
`FIG. 1 is a block diagram of one embodiment of a system.
`FIG. 2 is a block diagram of one embodiment of perfor
`mance configuration registers illustrated in FIG. 1.
`FIG. 3 is a flowchart illustrating operation of one embodi
`ment of a power management unit to automatically change
`power States.
`FIG. 4 is a block diagram illustrating one embodiment of
`driver components.
`FIG. 5 is a flowchart illustrating operation of one embodi
`ment of a power management unit driver component.
`FIG. 6 is a block diagram illustrating another embodiment
`of a system.
`FIG. 7 is a block diagram of one embodimentofa computer
`accessible storage medium.
`While the invention is susceptible to various modifications
`and alternative forms, specific embodiments thereof are
`shown by way of example in the drawings and will herein be
`
`Qualcomm, Ex. 1001, Page 8
`
`

`

`3
`described in detail. It should be understood, however, that the
`drawings and detailed description thereto are not intended to
`limit the invention to the particular form disclosed, but on the
`contrary, the intention is to cover all modifications, equiva
`lents and alternatives falling within the spirit and scope of the
`present invention as defined by the appended claims. The
`headings used herein are for organizational purposes only and
`are not meant to be used to limit the scope of the description.
`As used throughout this application, the word “may is used
`in a permissive sense (i.e., meaning having the potential to),
`rather than the mandatory sense (i.e., meaning must). Simi
`larly, the words “include”, “including, and “includes” mean
`including, but not limited to.
`Various units, circuits, or other components may be
`described as "configured to perform a task or tasks. In Such
`contexts, “configured to' is a broad recitation of structure
`generally meaning "having circuitry that performs the task
`or tasks during operation. As such, the unit/circuit/component
`can be configured to perform the task even when the unit/
`circuit/component is not currently on. In general, the circuitry
`that forms the structure corresponding to “configured to may
`include hardware circuits. Similarly, various units/circuits/
`components may be described as performing a task or tasks,
`for convenience in the description. Such descriptions should
`be interpreted as including the phrase “configured to.” Recit
`ing a unit/circuit/component that is configured to perform one
`or more tasks is expressly intended not to invoke 35 U.S.C.
`S112, paragraph six interpretation for that unit/circuit/com
`ponent.
`
`DETAILED DESCRIPTION OF EMBODIMENTS
`
`Turning now to FIG.1, a block diagram of one embodiment
`ofa system is shown. In the embodiment of FIG.1, the system
`includes an integrated circuit (IC) 10 forming a system on a
`chip, and a power supply 12. The integrated circuit 10
`includes a set of performance domains 14A-14F. Each per
`formance domain 14A-14F includes at least one component
`of the integrated circuit 10, and a given performance domain
`may include more than one component. For example, the
`performance domain 14A in FIG. 1 includes two compo
`nents, a processor 16A and another component 18; and the
`performance domain 14E may include two or more peripher
`als 24. In the illustrated embodiment, the performance
`domain 14B includes an optional second processor 16B; the
`performance domain 14C includes a graphics unit 20; the
`performance domain 14D includes an audio unit 22; the per
`formance domain 14E includes networking peripherals and/
`or other peripherals and/or peripheral interface units 24; and
`the performance domain 14F includes a memory controller
`26. The integrated circuit 10 also includes a power manage
`ment unit (PMU) 28 (which includes one or more perfor
`mance configuration registers 30) and a clock/voltage control
`unit 32. The various components shown in FIG. 1 may be
`coupled in any desired fashion. For example, there may one or
`more buses or other interfaces between the components. The
`PMU 28 and the clock/voltage control unit 32 may also be
`coupled to the various components in addition to being
`coupled to the interfaces. For example, the clock/voltage
`control unit 32 may supply clock signals to the components
`(not shown in FIG. 1). The clock/voltage control unit 32 may
`be configured to communicate with the power Supply 12 to
`request one or more Supply Voltages from the power Supply
`12. The power Supply 12 may generate the requested Voltage
`or Voltages, and may supply the integrated circuit with the
`Voltages.
`
`4
`The PMU 28 may be configured to control transitions
`between performance states for the various performance
`domains 14A-14F. Particularly, the PMU 28 may be config
`ured to automatically transition one or more of the perfor
`mance domains 14A-14F in response to one or more proces
`sors 16A-16B entering a sleep state (or in response to
`determining that the processor is to enter the sleep state). The
`PMU 28 may also be configured to automatically transition
`one or more of the performance domains 14A-14F in
`response to the processor exiting the sleep state (or in
`response to determining that the processor is to exit the sleep
`state). Exiting the sleep state may also be referred to as
`“waking the processor. The sleep state and other states of the
`processors may be performance States of the performance
`domains that include the processors. Alternatively, the sleep
`state and other processor states may be performance charac
`teristics in a performance state for the performance domains
`including the processors.
`A performance domain may be one or more components
`that may be controlled by the PMU 28 as a unit for perfor
`mance configuration purposes. That is, the PMU 28 may be
`configured to establish a corresponding performance state for
`each performance domain, and may be configured to control
`transitions between performance states in each performance
`domain. The components that form a performance domain
`may transition together from one performance state to
`another performance state. On the other hand, components in
`different performance domains may be independent of each
`other, at least from the standpoint of hardware, and may have
`independently-determined performance states. Some perfor
`mance domains may be logically linked at a higher level (e.g.
`in software). For example, the performance domains 14C
`14D may be logically linked if a user is watching a video that
`includes sound (thus using the graphics unit 20 to display the
`Video images and the audio unit 22 to transmit the Sound).
`The performance state may include any combination of
`performance characteristics for the components in a corre
`sponding performance domain. A performance characteristic
`may be any configurable setting for a component that affects
`the performance of that component. For example, the operat
`ing frequency of the clock signal provided to a component
`may affect its performance. A lower operating frequency may
`result in lower performance. A corresponding Supply Voltage
`may also be a performance characteristic. Some performance
`characteristics may be component-specific. For example,
`cache sizes in various caches may be a performance charac
`teristic. A data width or other data transfer rate parameter of
`an interface may be a performance characteristic. A compo
`nent that includes a number of symmetrical units that may
`operate in parallel (e.g. execution units in a processor, pixel
`pipelines or other image processing pipelines in a graphics
`unit, etc.) may be configurable as to the number of symmetri
`cal units that are active. A number of instructions (processor),
`operations (graphics or audio), communications (network or
`other peripheral interface), or memory request (memory con
`trol unit) processed per unit of time may be a performance
`characteristic. A graphics resolution or size of the color pal
`ette (e.g. bits per pixel) may be a performance characteristic.
`Audio resolution and sample rates may be a performance
`characteristic. Memory bandwidth may be a performance
`characteristic. The sleep/wake State of the processor may be a
`performance characteristic. If components orportions thereof
`can be power-gated and/or clock-gated, the power and/or
`clock enables may be performance characteristics. Any
`parameter that may be changed and that may affect perfor
`mance may be a performance characteristic in various
`embodiments.
`
`US 8,443,216 B2
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`Qualcomm, Ex. 1001, Page 9
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`US 8,443,216 B2
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`5
`Changing the performance state in a performance domain
`may affect the power consumption of the performance
`domain. Reducing operating frequency and Supply Voltage
`have direct effects on power consumption. Reducing cache
`size may reduce power consumption because a portion of the
`cache may not be accessed, and even more reduction may be
`realized if the unused portion may be turned off. Furthermore,
`reduced cache size may reduce cache hit rates, which may
`increase memory latency to the consumer. Increased memory
`latency may reduce activity in the consumer, reducing power
`consumption. Reduced data transfer widths/rates on inter
`faces may reduce power consumption through reduced
`Switching. Additionally, reducing the rate at which data is
`Supplied to a consumer may reduce activity in the consumer,
`which may reduce power consumption in the consumer.
`Reduced parallel activity in symmetrical units may reduce
`power consumption through reduced activity, as may reduced
`instruction or other operation issue rates. Reducing graphics/
`audio resolution and color palette may reduce the amount of
`data transferred per image or unit of Sound. Reduced memory
`bandwidth may reduce power consumption in accessing the
`memory per unit time, and may reduce activity in the con
`SUC.
`In some embodiments, the performance state may include
`multiple instances of a performance characteristic. For
`example, if the processor is powered offin the sleep state and
`other components are in the same performance domain, the
`Voltage for the processor may be set separately from the
`Voltage for the other components that remain active. Simi
`larly, any other performance characteristics that apply to
`more than one component in a performance domain and that
`may be independent controlled for such components may be
`represented by multiple instances in the performance state.
`In embodiments in which a processor is in a performance
`domain with other components, the other components may
`remain active during times that the processor is in the sleep
`state. For example, the component 18 in the performance
`domain 14A may remain active during times that the proces
`sor 16A is in the sleep state. The performance characteristics
`of the component may be changed to reflect reduced opera
`tion while the processor is in the sleep state. For example, the
`component 18 may be an level 2 (L2) cache coupled to the
`processor 16A. In Such an embodiment, the L2 cache may not
`be accessed by the sleeping processor 16A but may remain
`active to maintain cache coherence. The L2 cache may oper
`ate at a lower clock frequency (and Voltage) in some embodi
`ments while still providing enough performance to ensure the
`cache coherence.
`The PMU 28 may include circuitry configured to cause the
`performance state transitions to occur in the performance
`domains. In one embodiment, the PMU 28 may detect that the
`processor 16A-16B is entering/exiting the sleep state, and
`may cause corresponding transitions in the performance
`domains. In other embodiments, software may explicitly
`communicate sleep/wake events to the PMU 28. In an
`embodiment, the PMU 28 is programmable with perfor
`mance configurations for each performance domain. For
`example, performance states to be used in the performance
`domains 14A-14F when the processor is in sleep state may be
`specified in the performance configuration registers 30. Per
`formance states to be used when the processor 16A-16B exits
`the sleep state (awakens) may also be specified. When either
`event occurs, the PMU 28 may cause the desired transitions.
`In the case of Voltage and clock frequency changes, the
`PMU 28 may communicate the new settings to the clock/
`voltage control unit 32. The clock/voltage control unit 32 may
`implement the new settings, generating the clocks at the
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`6
`requested frequencies and requesting the desired Supply Volt
`ages from the power Supply 12. The clock/voltage control unit
`32 may order the modifications, if necessary, to safely make
`the transitions. For example, if the clock frequency and Sup
`ply Voltage are being increased, it may be safer to increase the
`Voltage first, and then increase the clock frequency because
`the increased clock frequency may lead to incorrect operation
`if circuitry is operating more slowly at the current (lower)
`Supply Voltage. In some embodiments, the amount of time
`that elapses in a Supply Voltage change may be substantially
`greater than the time to change the clock frequency. If the
`clock frequency and Supply Voltage are being decreased, the
`clock frequency may be reduced first (or the frequency and
`Voltage may be reduced in parallel, since the lower clock
`frequency may be reached prior to the lower Supply Voltage in
`this case).
`The clock/voltage control unit 32 may include circuitry to
`communicate with the power Supply 12 to request the desired
`Supply Voltages, and may include clock generation circuitry.
`For example, the clock/voltage control unit 32 may include
`one or more phase lock loops (PLLs), clock dividers/multi
`pliers, etc. to generate clocks for the components.
`The various components included in the integrated circuit
`10 may implement any desired functionality. Generally, a
`component may refer to any circuitry that is defined to per
`form a specified set of operations in the integrated circuit, and
`has a defined interface to communicate with other compo
`nents in the integrated circuit. As illustrated in FIG. 1, exem
`plary components may include the processors 16A-16B, the
`component 18, the graphics unit 20, the audio unit 22, the
`networking peripheral and other peripheral/peripheral inter
`faces 24 (which may be multiple components), and the
`memory controller 26.
`The processors 16A-16B may implement any instruction
`set architecture, and may be configured to execute instruc
`tions defined in that instruction set architecture. Any microar
`chitectural implementation may be used (e.g. in order, out of
`order, speculative, non-speculative, Scalar, SuperScalar, pipe
`lined, Superpipelined, etc.). Microcoding techniques may be
`used in some embodiments, in combination with any of the
`above.
`As mentioned above, the performance state of the proces
`sors 16A-16B may include a sleep state. In the sleep state, the
`processor is idle (not executing instructions). The clock to the
`processor may be stopped. In some embodiments, power may
`also be removed from the processor in the sleep state. Alter
`natively, there may be more than one sleep state. One of the
`sleep states may include powering down the processor, and
`another sleep state may include retaining power to the pro
`cessor. Additionally, the processor may include at least one
`“awake state'. There may be multiple awake states. For
`example, different Supply Voltage/operating frequency com
`binations may be supported, different combinations of
`enabled execution units may be supported, different instruc
`tion issue rates may be supported, etc.
`The graphics unit 20 may include any circuitry involved in
`the display of images on a display device for, e.g., user view
`ing. The images may be static images, or may be part of a
`Video. The graphics unit 20 may include rendering hardware,
`refresh (of the display device) hardware, video encoders and/
`or decoders, video compression and decompression units,
`etc. The audio unit 22 may include any circuitry involved in
`the playing or recording of Sounds in the system. The audio
`unit 22 may include, e.g., audio encoders and/or decoders,
`digital signal processors, etc.
`The networking peripherals and other peripherals 24 may
`include a variety of circuitry. For example, the networking
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`Qualcomm, Ex. 1001, Page 10
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`7
`peripherals may include a media access controller (MAC)
`unit for the Supported network, as well as physical layer
`circuitry. The other peripherals may include any other desired
`peripherals, and/or peripheral interface controllers config
`ured to control off-chip peripheral interfaces such as Periph- 5
`eral Component Interconnect (PCI), PCI express (PCIe),
`firewire, Universal Serial Bus (USB), etc.
`The memory controller 26 may be configured to access
`memory devices such as dynamic random access memory
`devices (DRAM), synchronous DRAM (SDRAM), double 10
`data rate (DDR, DDR2, DDR3, DDR4, etc.) SDRAM, low
`power DDR (LPDDR2, etc.) SDRAM, RAMBUSDRAM
`(RDRAM), etc. In one embodiment, the memory controller
`26 may be configured to interface to one or more memory
`modules (e.g. single inline memory modules (SIMMs), dual 15
`inline memory modules (DIMMs), etc.) that include one or
`more of the above memories. Accordingly, the memory con
`troller 26 may be configured to communicate on the memory
`interfaces, to queue memory requests from other components
`in the integrated circuit 10, and to communicate with the other 20
`components to complete the memory operations.
`While the embodiment of the integrated circuit 10 shown in
`FIG. 1 includes numerous performance domains, more or
`fewer performance domains may be supported. For example,
`a single performance domain may be supported, or two per- 25
`formance domains may be Supported (e.g. one domain
`including the processors 16A-16B and another domain
`including the remaining components 18, 20, 22, 24, and 26).
`One or more processors 16A-16B may be included in a per
`formance domain with any subset of the components 18, 20, 30
`22, 24, and 26. Any combination of performance domains and
`components included in those domains may be implemented
`in various embodiments.
`Other embodiments of the integrated circuit 10 may
`include other combinations of components, including any 35
`subset of the illustrated components with or without other
`components, Supersets with other components, etc. Addition
`ally, while the illustrated embodiment illustrates the compo
`nents 16A-16B, 18, 20, 22, 24, and 26 all included in the
`integrated circuit 10, other embodiments may implement the 40
`components as two or more integrated circuits. Any level of
`integration or discrete components may be used.
`Turning now to FIG. 2, a block diagram illustrating one
`embodiment of the performance configuration registers 30 is
`shown. In the illustrated embodiment, the registers 30 include 45
`register set 30A, register set 30B, and register set 30C. The
`register set 30B may include a configuration for each perfor
`mance domain, and for the sleep state and the wake state.
`Accordingly, the illustrated set supports up to “n” perfor
`mance domains, where “n” is a positive integer. The sleep 50
`state for a given performance domain indicates the perfor
`mance state for the domain in response to the processor enter
`ing the sleep state. The wake state for the given performance
`domain indicates the performance state for the domain in
`response to the processor exiting the sleep state.
`In some embodiments, the registers 30B may directly store
`values defining the performance state to be established in the
`corresponding power domain. In such cases, the Software
`preparing the integrated circuit 10 for a sleep state of the
`processors 16A-16B may program each register 30B for the 60
`sleep state and the following wake State according to the
`activity in the system.
`In the illustrated embodiment, the