`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`KINGSTON TECHNOLOGY COMPANY, INC.,
`Petitioner,
` v.
`MEMORY TECHNOLOGIES, LLC,
`Patent Owner
`
`
`
`Case No.: To Be Assigned
`U.S. Patent No. 7,827,370
`
`
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 7,827,370
` Mail Stop “Patent Board”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`4812-5357-2485
`
`

`

`
`TABLE OF CONTENTS
`I.
`INTRODUCTION AND STATEMENT OF RELIEF REQUESTED (37
`C.F.R. §42.22(a)) ............................................................................................. 1
`II. MANDATORY NOTICES ............................................................................. 2
`A.
`Real Party-In-Interest (37 C.F.R. §42.8(b)(1)) ..................................... 2
`B.
`Identification of Related Matters (37 C.F.R. §42.8(b)(2)) .................... 2
`C.
`Counsel and Service Information (37 C.F.R. §§42.8(b)(3) & (b)(4)) ... 3
`D.
`Payment of fees (37 C.F.R. §42.103) .................................................... 4
`III. REQUIREMENTS FOR INTER PARTES REVIEW ...................................... 4
`A.
`Prior Art Relied Upon ........................................................................... 4
`B.
`Identification of Challenge .................................................................... 5
`IV. BACKGROUND OF THE TECHNOLOGY .................................................. 5
`V. OVERVIEW OF THE ’370 PATENT ............................................................ 8
`VI. SUMMARY OF THE PROSECUTION HISTORY ..................................... 11
`VII. SUMMARY OF THE PRIOR ART .............................................................. 12
`A.
`Chevallier ............................................................................................ 12
`B.
`Toombs ................................................................................................ 13
`C.
`Estakhri ................................................................................................ 14
`VIII. CLAIM CONSTRUCTION .......................................................................... 14
`A.
`“a data register” ................................................................................... 16
`B.
`“redefine the command to allow permanent write protection” ........... 17
`C.
`“wherein said at least one bit has a certain predefined value” ............ 18
`D.
`“wherein said at least one bit is reprogrammable” ............................. 19
`E.
`“memory group” .................................................................................. 20
`IX. A PERSON OF ORDINARY SKILL IN THE ART .................................... 21
`X. GROUND 1: CLAIMS 1-3, 5-6, 12-15, AND 25 ARE ANTICIPATED
`UNDER 35 U.S.C. §§ 102(a) AND (e) BY CHEVALLIER. ....................... 22
`A.
`Independent Claim 1 ........................................................................... 22
`B.
`Dependent Claim 2 .............................................................................. 28
`C.
`Dependent Claim 3 .............................................................................. 29
`D. Dependent Claim 5 .............................................................................. 30
`E.
`Dependent Claim 6 .............................................................................. 33
`F.
`Independent Claim 12 ......................................................................... 34
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`U.S. Patent No. 7,827,370
`Petition for Inter Partes Review
`G. Dependent Claim 13 ............................................................................ 38
`H. Dependent Claim 14 ............................................................................ 38
`I.
`Dependent Claim 15 ............................................................................ 38
`J.
`Independent Claim 25 ......................................................................... 39
`XI. GROUND 2: CLAIMS 1-3, 5-6, 12-15, AND 25 ARE OBVIOUS UNDER
`35 U.S.C. § 103 OVER CHEVALLIER IN VIEW OF THE KNOWLEDGE
`OF A POSA. .................................................................................................. 40
`A.
`Independent Claims 1, 12, and 25 ....................................................... 41
`B.
`Dependent Claim 3 .............................................................................. 42
`C.
`Dependent Claims 5 and 14 ................................................................ 44
`D. Dependent Claims 2, 6, 13, and 15 ..................................................... 45
`XII. GROUND 3: CLAIMS 1-3, 5-7, 12-15, 19, AND 25 ARE OBVIOUS
`UNDER 35 U.S.C. § 103 OVER CHEVALLIER IN VIEW OF TOOMBS.
`
`45
`A.
`Independent Claim 1 ........................................................................... 45
`B.
`Dependent Claim 2 .............................................................................. 48
`C.
`Dependent Claim 3 .............................................................................. 48
`D. Dependent Claim 4 .............................................................................. 51
`E.
`Dependent Claims 5, 13, and 14 ......................................................... 53
`F.
`Dependent Claim 6 .............................................................................. 57
`G. Dependent Claim 7 .............................................................................. 58
`H.
`Independent Claim 12 ......................................................................... 59
`I.
`Dependent Claim 15 ............................................................................ 61
`J.
`Dependent Claim 19 ............................................................................ 62
`K.
`Independent Claim 25 ......................................................................... 62
`XIII. GROUND 4: CLAIM 25 IS OBVIOUS UNDER 35 U.S.C. § 103 OVER
`THE CHEVALLIER-TOOMBS-ESTAKHRI COMBINATION. ............... 63
`XIV. CONCLUSION .............................................................................................. 64
`
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`U.S. Patent No. 7,827,370
`Petition for Inter Partes Review
`TABLE OF AUTHORITIES
` Page(s)
`Cases
`Memory Technologies, LLC v. Kingston Technology Corporation et
`al., 8:18-cv-00171-JLS-JDE (C.D. Cal.) .................................................................... 2
`In re Fracalossi,
`681 F.2d 792, 794 (CCPA 1982) ........................................................................ 41
`In re Meyer,
`599 F.2d 1026 (CCPA 1979) .............................................................................. 41
`In re Pearson,
`494 F.2d 1399 (CCPA 1974) .............................................................................. 41
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) .............................................................. 14, 15, 16
`Schrader-Bridgeport Int’l, et al. v. Wasica Finance GMBH et al.,
`Case No. IPR2014-00476, Paper 30 (PTAB July 22, 2015) .............................. 41
`Statutes and Codes
`United States Code
`Title 35, Section 102 ................................................................................. 1, 22, 41
`Title 35, Section 102(a) .............................................................................. 4, 5, 22
`Title 35, Section 102(b) ........................................................................................ 4
`Title 35, Section 102(e) ........................................................................................ 4
`Title 35, Section 103 ....................................................................................passim
`Title 35, Section 112 ........................................................................................... 16
`Title 35, Section 282(b) ...................................................................................... 14
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`U.S. Patent No. 7,827,370
`Petition for Inter Partes Review
`Rules and Regulations
`Code of Federal Regulations
`Title 37, Section 42.6(a)(2)(ii) ............................................................................ 66
`Title 37, Section 42.6(a)(2)(iii) ........................................................................... 66
`Title 37, Section 42.8 .......................................................................................... 66
`Title 37, Section 42.10(b) ..................................................................................... 3
`Title 37, Section 42.15 .......................................................................................... 4
`Title 37, Section 42.24(a)(1)(i) ........................................................................... 66
`Title 37, Section 42.104 ........................................................................................ 4
`Title 37, Section 42.104(b) ................................................................................... 5
`Title 37, Section 42.105 ........................................................................................ 4
`Title 37, Section 42.106 ........................................................................................ 4
`Title 37, Section 42.108(c) ........................................................................... 16, 41
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`U.S. Patent No. 7,827,370
`Petition for Inter Partes Review
`EXHIBIT LIST
`Exhibit No. Description
`1001
`U.S. Patent No. 7,827,370
`1002
`File History for U.S. Patent No. 7,827,370
`1003
`U.S. Patent App. Pub. No. 2004/0083346 to Chevallier et al.
`1004
`U.S. Patent No. 6,279,114 to Toombs et al.
`1005
`U.S. Patent No. 6,262,918 to Estakhri et al.
`Declaration of Dr. R. Jacob Baker
`1006
`U.S. Patent App. No. 10/279,470 to Chevallier et al.
`1007
`Third Joint Claim Construction and Prehearing Statement (N.D.
`1008
`Cal. Patent L.R. 4-3), filed in the related matter on Nov. 16, 2018
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`
`I.
`INTRODUCTION AND STATEMENT OF RELIEF REQUESTED (37
`C.F.R. §42.22(a))
`Kingston Technology Company, Inc. (“Petitioner” or “Kingston”) hereby
`petitions to institute an inter partes review of Claims 1-3, 5-7, 12-15, 19, and 25
`(the “Challenged Claims”) of U.S. Patent No. 7,827,370 (the “’370 Patent,” Ex.
`1001), and cancel those claims as unpatentable. The ’370 Patent concerns write-
`protecting a peripheral memory card.
`The prior art presented in this Petition—Chevallier (Ex. 1003), Toombs (Ex.
`1004), and Estakhri (Ex. 1005)—disclose each and every limitation of the
`Challenged Claims. Chevallier and Estakhri were not considered during original
`prosecution of the ’370 Patent, and the applicant admitted that Toombs discloses
`“that an entire card may be write protected by setting write protect bits in a CSD
`register” and that “addressed portions of memory can be write protected.”
`However, the applicant argued such write protection was not permanent, as
`claimed, “because Toombs describes removing/cancelling the write protection via
`a clear command.” Chevallier expressly discloses permanent write protection.
`Therefore, as discussed in detail below, Chevallier—alone or in combination
`with Toombs and/or Estakhri—anticipates and/or renders obvious the Challenged
`Claims of the ’370 Patent under 35 U.S.C. §§ 102 and 103. Accordingly, there is a
`reasonable likelihood that Petitioner will prevail with respect to at least one
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`U.S. Patent No. 7,827,370
`Petition for Inter Partes Review
`challenged claim, and Petitioner respectfully requests that the Board institute a trial
`for inter partes review and cancel all Challenged Claims as unpatentable.
`II. MANDATORY NOTICES
`A. Real Party-In-Interest (37 C.F.R. §42.8(b)(1))
`Petitioner Kingston Technology Company, Inc., is a real party-in-interest.
`Petitioner’s parent company, Kingston Technology Corporation (“Kingston
`Holding”), is a holding company without any employees or operations. However,
`because Kingston Holding is a co-defendant in the related matter identified below,
`is the sole owner of Petitioner, and shares some directors, Petitioner identifies
`Kingston Holding as an additional real party-in-interest.
`B.
`Identification of Related Matters (37 C.F.R. §42.8(b)(2))
`Patent Owner Memory Technologies, LLC (“MTL”) has asserted the
`Challenged Claims of the ’370 Patent, as well as claims from seven other patents,
`against Kingston and Kingston Holding in a co-pending litigation, Memory
`Technologies, LLC v. Kingston Technology Corporation et al., 8:18-cv-00171-
`JLS-JDE (C.D. Cal.). MTL’s Complaint was filed on January 31, 2018, and served
`on Kingston, at the earliest, on February 1, 2018.
`In addition to this Petition, Kingston has or will be filing petitions for inter
`partes review of the other seven patents that MTL has asserted against it.
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`U.S. Patent No. 7,827,370
`Petition for Inter Partes Review
`C. Counsel and Service Information (37 C.F.R. §§42.8(b)(3) & (b)(4))
`Petitioner designates the following Lead and Backup Counsel. Concurrently
`filed with this Petition is a Power of Attorney for appointing the following Lead
`and Backup Counsel, per 37 C.F.R. § 42.10(b). Service via hand-delivery may be
`made at the postal mailing addresses below. Petitioner consents to electronic
`service by e-mail at the following address: kingston-370ipr@pillsburylaw.com.
`Lead Counsel
`Back-Up Counsel
`Robert C.F. Pérez
`Christopher Kao, Kingston’s counsel in
`(Reg. No. 39,328)
`the co-pending litigation
` PILLSBURY WINTHROP SHAW
`(Pro hac vice motion to be filed)
` PILLSBURY WINTHROP SHAW
`PITTMAN LLP
`1650 Tysons Boulevard, 14th Floor
`PITTMAN LLP
`McLean, VA 22101
`Four Embarcadero Center, 22nd Floor
`Telephone: 703.770.7900
`San Francisco, CA 94111
`Facsimile: 703.770.7901
`Telephone: 415.983.1000
`Facsimile: 415.983.1200
` Brock S. Weber, Kingston’s counsel in
`the co-pending litigation
`(Pro hac vice motion to be filed)
` PILLSBURY WINTHROP SHAW
`PITTMAN LLP
`Four Embarcadero Center, 22nd Floor
`San Francisco, CA 94111
`Telephone: 415.983.1000
`Facsimile: 415.983.1200
`
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`U.S. Patent No. 7,827,370
`Petition for Inter Partes Review
`D.
`Payment of fees (37 C.F.R. §42.103)
`Petitioner authorizes the Patent and Trademark Office to charge Deposit
`Account No. 033975 for the petition fee and for any other required fees.
`III. REQUIREMENTS FOR INTER PARTES REVIEW
`This Petition complies with all statutory requirements under the AIA and 37
`C.F.R. §§ 42.104, 42.105, and 42.15, and should be accorded a filing date as the
`date of filing of this Petition pursuant to 37 C.F.R. § 42.106.
`A.
`Prior Art Relied Upon
`Exhibit 1003—United States Patent Application Publication No.
`2004/0083346 to Chevallier et al. (“Chevallier”), titled “Permanent Memory Block
`Protection in a Flash Memory Device,” filed October 24, 2002 and published April
`29, 2004. Chevallier is prior art under at least pre-AIA 35 U.S.C. §§ 102(a) and
`(e). Chevallier was not considered during the prosecution of the ’370 Patent.
`Exhibit 1004—United States Patent No. 6,279,114 to Toombs et al.
`(“Toombs”), titled “Voltage Negotiation in a Single Host Multiple Cards System,”
`filed November 4, 1998 and issued and published on August 21, 2001. Toombs is
`prior art under at least pre-AIA 35 U.S.C. §§ 102(a), (b), and (e). Toombs was
`cited by the Patent Office during prosecution of the ’370 Patent.
`Exhibit 1005—United States Patent No. 6,262,918 to Estakhri et al.
`(“Estakhri”), titled “Space Management for Managing High Capacity Nonvolatile
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`U.S. Patent No. 7,827,370
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`Memory,” filed June 30, 2000 and issued and published on July 17, 2001. Estakhri
`is prior art under at least pre-AIA 35 U.S.C. §§ 102(a), (b), and (e). Estakhri was
`not considered during the prosecution of the ’370 Patent.
`B.
`Identification of Challenge
`Pursuant to 37 C.F.R. §42.104(b), Petitioner shows the following grounds:
`1.
`Claims 1-3, 5-6, 12-15, and 25 are anticipated under 35 U.S.C. §§
`102(a) and (e) by Chevallier;
`2.
`Claims 1-3, 5-6, 12-15, and 25 are rendered obvious under 35 U.S.C.
`§ 103 by Chevallier;
`3.
`Claims 1-3, 5-7, 12-15, 19, and 25 (i.e., all Challenged Claims) are
`rendered obvious under 35 U.S.C. § 103 by Chevallier in view of
`Toombs; and
`4.
`Claim 25 is rendered obvious under 35 U.S.C. § 103 by Chevallier in
`view of Toombs and Estakhri.
`The Declaration of R. Jacob Baker, Ph.D., P.E., filed herewith (Ex. 1006,
`“Baker Decl.”), supports the challenge in this Petition that Claims 1-3, 5-7, 12-15,
`19, and 25 are invalid as anticipated and obvious.
`IV. BACKGROUND OF THE TECHNOLOGY
`Memory cards, such as PC cards, compact flash (“CF”) cards, secure digital
`(“SD”) cards, or multimedia cards (“MMC”), are electronic data storage devices
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`U.S. Patent No. 7,827,370
`Petition for Inter Partes Review
`used in various portable electronic devices such as digital cameras, mobile phones,
`laptop computers, tablets, and video game consoles (known as “host” devices).
`Ex. 1006, ¶74. Data is stored on a memory device by recording the data in bits in
`memory cells. Id., ¶75. This data can be read by sensing the values of the bits. Id.
`Memory devices are typically based on a block architecture in which the
`memory is divided into blocks of memory. Ex. 1006, ¶87. This allows file
`systems to erase certain blocks of memory instead of the entire device. Ex. 1003,
`¶0005. Memory sectors, memory blocks, and memory groups are units used to
`describe portions of a memory. Ex. 1004, 27:37-42, FIG. 66.
`MMCs can utilize one or more memory technologies such as ROM (read
`only memory), OTP (one-time programmable), MTP (multi-time programmable),
`or Flash. Id., 7:5-8, FIG. 4. An example MMC is shown in the figure below.
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`U.S. Patent No. 7,827,370
`Petition for Inter Partes Review
`
`Id., FIG. 14. As illustrated, a MMC communicates with a host device by a CMD
`bus line for commands and responses and a DAT bus line for transmission of data.
`Id., 7:57-65. The MMC includes a command set for controlling operations on the
`MMC such as data read/write or obtaining card information. Id., FIGs. 38-44.
`Each command is identified by a command number. For example, CMD 28 of Fig.
`42 identifies the “SET_WRITE_PROT” command. Id., FIG. 42.
`As illustrated above, the MMC includes an interface controller coupled to
`the MMC’s memory core. Ex. 1006, ¶83. The interface controller also couples to
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`U.S. Patent No. 7,827,370
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`a group of registers (e.g., OCR, CID, CSD, RCA, DSR) that can store information
`about the memory card. Ex. 1004, 9:45-59. For example, the CSD (Card Specific
`Data) register stores card information such as data format, data transfer speed, etc.
`Id., 10:22-33, FIGs. 17A-B. The CSD also contains entries that influence the
`effect of commands executed by the memory card. For example, the
`WP_GRP_ENABLE bit of the CSD register controls whether groups of memory in
`the memory core are protected by execution of a SET_WRITE_PROT command.
`Id., 30:1-12, Fig. 17B. As another example, the WP_GRP_SIZE CSD register bit
`defines the size of the group to be protected by the SET_WRITE_PROT command.
`Id. CSD register entries may be R=readable, W=writable once, or E=erasable
`(multiple writable). Id., 10:29-31.
`As of July 2004, the MMC standard allowed permanent (and temporary)
`write protection of an entire memory card by setting the
`PERM_WRITE_PROTECT (or TMP_WRITE_PROTECT) bit in the CSD
`register. Id., 12:56-67. The MMC standard also allowed write protecting memory
`groups of a memory card using the SET_WRITE_PROT command, which could
`be cleared by a CLR_WRITE_PROT command. Id., 30:9-12.
`V. OVERVIEW OF THE ’370 PATENT
`The ’370 Patent relates to permanently write protecting a memory card. The
`’370 Patent notes that it is desirable for some data to be protected from accidental
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`U.S. Patent No. 7,827,370
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`or conscious deletion by a user while other data is alterable. Ex. 1001, 1:31-49.
`According to the ’370 Patent, at the time of the invention, “[t]he MMC
`specification offers one solution to this kind of problem.” Id., 1:56-57. The MMC
`specification provides for write protecting a portion of a MMC using a specific
`command called SET_WRITE_PROT. Id., 1:60-62. However, the ’370 Patent
`asserts that command does not result in permanent write protection because the
`write protection can be cancelled using another command called
`(CLR_WRITE_PROT). Id., 1:63-66.
`The ’370 Patent recognizes that at the time of the invention the MMC
`specification did provide permanent write protection (i.e., write protection that was
`not changeable) by setting a permanent write protection bit called
`PERM_WRITE_PROTECT in the CSD (Card Specific Data) register of the
`memory card. Id., 1:66-2:2. However, the ’370 Patent asserts such permanent
`protection could only be applied to the entire card. The ’370 Patent instead
`purports to disclose “permanently write protecting a portion of a multimedia card.”
`Id., 2:7-8. Specifically, the ’370 Patent discloses “identifying a bit in a specific
`data register of the memory [and] setting said bit to have a certain predefined value
`that causes write protection command to mean permanent write protection of part
`of the memory.” Id., 2:12-18. The ’370 Patent discloses that after this bit is set,
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`U.S. Patent No. 7,827,370
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`the command is executed to cause a part of the memory to be permanently write
`protected. Id., 2:19-21.
`In one embodiment, the ’370 Patent discloses defining the
`PERM_WRITE_PROTECT bit of the CSD “in such way that setting of this bit
`does not as such protect the whole card,” but rather “indicate[s] that all the write
`protect groups protected with SET_WRITE_PROT command . . . are permanently
`write protected and cannot be un-protected using CLR_WRITE_PROTECT
`command.” Id., 2:55-62. The segment size of the memory to be protected “is
`defined in the units of WP_GRP_SIZE groups as known to those skilled in the art.”
`Id., 2:62-64. Part of the CSD fields corresponding to this embodiment is shown in
`Table 1:
`
`In another embodiment, one of the unused CSD bits (e.g., called
`PARTIAL_PERM_WP) may be defined to “indicate that a portion of the
`multimedia card [] is permanently write protected.” Id., 3:9-12. The
`PARTIAL_PERM_WP bit “should be re-programmable” and “could be cleared
`automatically when SET_WRITE_PROTECT command [] is received.” Part of
`the CSD fields according to this embodiment is shown in Table 2:
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`U.S. Patent No. 7,827,370
`Petition for Inter Partes Review
`
`Id., Table 2.
` VI. SUMMARY OF THE PROSECUTION HISTORY
`On August 18, 2010, the Patent Office issued a Notice of Allowance stating
`that “[t]he primary reasons for allowance of [the] independent claims . . . is the
`inclusion in the claims of ‘setting at least one bit in a data register configured to
`indicate that permanent write protection of the at least one part of the memory is
`allowed in order to redefine the command to allow permanent write protection that
`cannot be un-protected by a command, of the at least one part of the memory.’”
`Ex. 1002, 24.
`During prosecution, the applicant acknowledged that the Toombs
`Publication (U.S. Pub. 2001/0016887, Ex. 1004) cited by the Patent Office
`“described that an entire card may be write protected by setting write protect bits in
`a CSD register” and disclosed that “addressed portions of memory can be write
`protected.” Ex. 1002, 24. However, the applicant argued such write protection
`was not permanent “because Toombs describes removing/cancelling the write
`protection via a clear command.” Id.
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`U.S. Patent No. 7,827,370
`Petition for Inter Partes Review
`VII. SUMMARY OF THE PRIOR ART
`A. Chevallier
`Chevallier describes temporarily or permanently protecting memory blocks
`against write and erase operations. Ex. 1003, Abstract, ¶0008; Ex. 1006, ¶137.
`For example, Chevallier discloses a flash memory device having a temporary lock
`function that temporarily locks memory blocks in response to a lock command.
`Ex. 1003, ¶¶0008, 0016; Ex. 1006, ¶137. The temporary lock function can be
`cleared, allowing memory blocks that were protected by the temporary function to
`be erased or reprogrammed. Ex. 1003, ¶0016; Ex. 1006, ¶137.
`Chevallier also discloses a secure function that permanently locks memory
`blocks in response to a secure command. Ex. 1003, ¶¶0007, 0008, 0016, 0018,
`0036; Ex. 1006, ¶138. The memory blocks protected by the secure function are
`permanently secured against write and erase operations. Ex. 1003, ¶¶0016, 0036;
`Ex. 1006, ¶138. Notably, Chevallier discloses that the secure command and the
`lock command can be the same command. Ex. 1003, ¶¶0008, 0020; Ex. 1006,
`¶138. The secure function can be enabled and disabled by setting a secure function
`bit in a register. Ex. 1003, ¶0038; Ex. 1006, ¶138. The value of the bit controls
`whether a lock command will result in temporary write protection or in permanent
`write protection. Ex. 1003, Claims 18-19; Ex. 1006 ¶138.
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`U.S. Patent No. 7,827,370
`Petition for Inter Partes Review
`B.
`Toombs
`
`Toombs describes write protecting at least portions of groups of a memory
`of a MultiMediaCard (“MMC”). Ex. 1004, 29:40-42; Ex. 1006, ¶142. Toombs
`discloses that the MMC may include a number of data registers used to store
`information about the card, such as card / content specific information and
`configuration parameters. Ex. 1004, 9:51-60; Ex. 1006, ¶142. For example,
`Toombs discloses a card specific data register (CSD) that contains information
`about the memory card’s characteristics. Ex. 1004, 10:21-26; Ex. 1006, ¶142.
`Toombs discloses permanently write protecting the memory card by setting
`a non-erasable PERM_WRITE_PROTECT field in the CSD register. Ex. 1004,
`12:56-67, 30:1-3; Ex. 1006, ¶143. Toombs also discloses permanently write
`protecting the memory card by setting an erasable TMP_WRITE_PROTECT field
`in the CSD. Ex. 1004, 12:56-67, 30:1-3; Ex. 1006, ¶143.
`Lastly, Toombs discloses enabling write protection of memory groups (i.e.,
`less than the whole card) by setting a WP_GRP_ENABLE bit in the CSD. Ex.
`1006, ¶143. The size of each memory group to be write protected is defined by the
`WP_GRP_SIZE field in the CSD. Id. The addressed group(s) are then write
`protected by executing a SET_WRITE_PROT command. Ex. 1004, 30:3-10; Ex.
`1006, ¶143.
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`U.S. Patent No. 7,827,370
`Petition for Inter Partes Review
`C. Estakhri
`
`Estakhri discloses a flash memory device having a microprocessor circuit
`and a volatile storage unit for executing operations on non-volatile memory. Ex.
`1005, Fig. 1; Ex. 1006, ¶146. The volatile storage unit stores firmware that is
`executed by the microprocessor. Ex. 1005, 4:54-59; Ex. 1006, ¶146.
`VIII. CLAIM CONSTRUCTION
`The Patent Office has adopted a rule by which claims are construed in
`accordance with “the standard used in federal courts, in other words, the claim
`construction standard that would be used to construe the claim in a civil action
`under 35 U.S.C. 282(b), which is articulated in Phillips v. AWH Corp., 415 F.3d
`1303 (Fed. Cir. 2005).” This rule reflects that the PTAB in an AIA proceeding
`will apply the same standard applied in federal courts to construe patent claims.
`For example, claim construction begins with the language of the
`claims. Phillips, 415 F.3d at 1312-14. The “words of a claim are generally given
`their ordinary and customary meaning,” which is “the meaning that the term would
`have to a person of ordinary skill in the art in question at the time of the
`invention, i.e., as of the effective filing date of the patent application.” Id. at 1312-
`13. The specification is “the single best guide to the meaning of a disputed term
`and . . . acts as a dictionary when it expressly defines terms used in the claims or
`when it defines terms by implication.” Id. at 1321 (internal quotation marks
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`U.S. Patent No. 7,827,370
`Petition for Inter Partes Review
`omitted). Although the prosecution history “often lacks the clarity of the
`specification and thus is less useful for claim construction purposes,” it is another
`source of intrinsic evidence that can “inform the meaning of the claim language by
`demonstrating how the inventor understood the invention and whether the inventor
`limited the invention in the course of prosecution, making the claim scope
`narrower than it would otherwise be.” Id. at 1317. Extrinsic evidence, such as
`expert testimony and dictionaries, may be useful in educating the court regarding
`the field of the invention or helping determine what a person of ordinary skill in
`the art would understand claim terms to mean. Id. at 1318-19. However, extrinsic
`evidence in general is viewed as less reliable than intrinsic evidence. Id.
`All claim terms of Challenged Claims of the ’370 Patent have been accorded
`their plain and ordinary meaning as understood by a person having ordinary skill in
`the art at the time of the alleged invention (a “POSA”) and consistent with the
`intrinsic record. Petitioner’s interpretation of the claim terms in the ’370 Patent is
`further explained for each claim limitation in relation to the prior art discussed in
`the proposed grounds for invalidity, below, in Grounds 1-4.
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`U.S. Patent No. 7,827,370
`Petition for Inter Partes Review
`Under the Phillips standard and for clarity, Petitioner provides the following
`specific constructions.1
`A.
`“a data register”
`Challenged Claims 1, 5, 12, 14, and 25 all recite a “data register.” A POSA
`would have recognized that the plain and ordinary meaning of this phrase is “a
`portion of memory containing information about a memory card.” Ex. 1006,
`¶¶116-18. Indeed, Patent Owner has agreed to this construction in the co-pending
`related litigation, which is also governed under the Phillips standard. Ex. 1008, 1-
`2 (showing that the agreed construction of “data register” is “a portion of memory
`containing information about a memory card”).
`The intrinsic evidence also supports this construction. The specification
`refers primarily to a particular kind of data register, the “CSD (Card Specific Data)
`register.” Ex. 1001, 1:59-60. The CSD consists of fields which have bit strings of
`varying length. Id., 2:50-54. According to the specification, a “CSD provides
`
`1 Petitioner reserves the right to address any claim construction positions taken
`by the Patent Owner in its Preliminary Response, if any, including under 37
`C.F.R. § 42.108(c). Petitioner further reserves its ability to show that claims of
`the ’370 Patent are invalid under 35 U.S.C. §112 in the co-pending litigation,
`despite offering explicit and implicit claim constructions herein.
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`U.S. Patent No. 7,827,370
`Petition for Inter Partes Review
`information on how to access the card contents” (Id., 2:49), contains information
`about the size of memory groups to be write protected (Id., 1:58-60), contains a bit
`enabling permanent write protection on some or all of the memory card (Id., 2:65-
`3:7; 3:38-47), and contains information identifying the type of memory technology
`on a card and the address space of that memory (Id., 5:8-13). In sum, the ’370
`Patent discloses that a CSD contains information about the memory card. Ex.
`1006, ¶117.
`Therefore, a POSA would have recognized that “a data register” is “a
`portion of memory containing information about a memory card.” Ex. 1006, ¶118.
`B.
`“redefine the command to allow permanent write protection”
`Challenged Claims 1, 12, and 25 each recite this element. A POSA would
`have recognized this phrase to mean to “cause a command that would not result in
`permanent write protection to result in permanent write protection.” Ex. 1006,
`¶¶122-23. Here, again, Patent Owner has agreed to this construction in the co-
`pending related litigation. Ex. 1008, 1-2 (showing that the agreed construction of
`this phrase is to “cause a command that would not result in permanent write
`protection to result in permanent write protection”).
`The int