Declaration in Support of Inter Partes Review of U.S. Patent RE45,542
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`KINGSTON TECHNOLOGY COMPANY, INC.,
`Petitioner,
`v.
`MEMORY TECHNOLOGIES, LLC,
`Patent Owner
`
`U.S. Patent No. RE45,542
`
`DECLARATION OF R. JACOB BAKER, Ph.D., P.E.,
`REGARDING U.S. PATENT NO. RE45,542
`
`4820-9150-5030.v2
`
`Kingston Exhibit 1002 - 1
`
`

`

`I.
`
`II.
`
`Declaration in Support of Inter Partes Review of U.S. Patent RE45,542
`TABLE OF CONTENTS
`Contents
`INTRODUCTION ........................................................................................... 1
`A. Educational Background .................................................................................. 1
`B. Career History .................................................................................................. 2
`C. Other Relevant Qualifications ......................................................................... 7
`D. Materials and Other Information Considered .................................................. 8
`LEGAL PRINCIPLES ..................................................................................... 8
`A. Legal Standard for Prior Art ............................................................................ 9
`B. Legal Standard for Anticipation ....................................................................10
`C. Legal Standard for Obviousness ....................................................................11
`D. Legal Standard for Claim Construction .........................................................16
`E. Legal Standard for Priority Date ...................................................................23
`III. LEVEL OF ORDINARY SKILL IN THE ART ...........................................24
`IV. BACKGROUND OF THE TECHNOLOGY OF THE RE542
`PATENT ..................................................................................................................25
`A. Power Needs of Peripheral Devices ..............................................................25
`B. Power Management .......................................................................................28
`C. Limiting Power Consumption .......................................................................31
`V. OVERVIEW OF THE RE542 Patent ............................................................35
`A. Summary of the RE542 Patent ......................................................................35
`B. The RE542 Patent Prosecution History .........................................................45
`VI. CLAIM CONSTRUCTION (37 C.F.R. § 42.104(b)(3)) ...............................54
`A. “peripheral device” ........................................................................................55
`i
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`Kingston Exhibit 1002 - 2
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`Declaration in Support of Inter Partes Review of U.S. Patent RE45,542
`B. “default value” ...............................................................................................58
`C. “limiting value” .............................................................................................59
`D. “maximum power consumption of the peripheral device” ............................63
`VII. BRIEF DESCRIPTION OF PRIOR ART RELIED UPON ..........................71
`A. U.S. Patent No. 5,724,592 to Garner (“Garner”) ..........................................72
`B. U.S. Patent No. 6,279,114 to Toombs et al. (“Toombs”) ..............................76
`VIII. CLAIM-BY-CLAIM EXPLANATION OF GROUNDS OF
`UNPATENTABILITY.............................................................................................78
`A. Ground 1: Garner anticipates Claims 18, 23, 28-29, 32-33, 37, 38, and
`40 under § 102. ..............................................................................................78
`B. Ground 2: The combination of Garner and Toombs renders Claims 18,
`23-24, 28-29, 32-33, and 37-40 obvious under § 103 .................................112
`IX. Reservation of Rights ..................................................................................154
`X.
`CONCLUSION ............................................................................................155
`
`ii
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`4820-9150-5030.v2
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`Kingston Exhibit 1002 - 3
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`

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`Declaration in Support of Inter Partes Review of U.S. Patent RE45,542
`INTRODUCTION
`I.
`1. My name is R. Jacob Baker Ph.D., P.E. I am a Professor of Electrical
`
`and Computer Engineering at the University of Nevada, Las Vegas. I have
`
`prepared this report as an expert witness on behalf of Kingston Technology
`
`Company, Inc. (“Petitioner” or “Kingston”). In this report I give my opinions as to
`
`whether claims 18, 23-24, 28-29, 32-33, and 37-40 of U.S. Patent No. RE45,542
`
`(“the RE542 Patent”) (Ex. 1001) are valid. I provide technical bases for these
`
`opinions as appropriate.
`
`2.
`
`This declaration contains statements of my opinions formed to date
`
`and the bases and reasons for those opinions. I may offer additional opinions based
`
`on further review of materials in this case, including opinions and/or testimony of
`
`other expert witnesses.
`
`3.
`
`I have summarized in this section my educational background, career
`
`history, publications, and other relevant qualifications. My full curriculum vitae is
`
`attached as Appendix A to this declaration.
`
`A. Educational Background
`I received a B.S. degree and a M.S. degree in electrical engineering
`4.
`
`from the University of Nevada, Las Vegas (“UNLV”) in 1986 and 1988,
`
`respectively. I received my Ph.D. in Electrical Engineering from the University of
`
`Nevada, Reno, in 1993.
`
`1
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`Kingston Exhibit 1002 - 4
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`Declaration in Support of Inter Partes Review of U.S. Patent RE45,542
`5. My doctoral research, culminating in the award of a Ph.D. in
`
`Electrical Engineering in 1993, investigated the use of power MOSFETs (metal
`
`oxide semiconductor field effect transistors) in the design of very high peak power,
`
`and high-speed, instrumentation. I developed techniques to reliably stack power
`
`MOSFETs to switch higher voltages, that is, greater than 1,000 V at near 100
`
`Amps of current with nanosecond switching times. This work was reported in the
`
`paper entitled “Transformerless Capacitive Coupling of Gate Signals for Series
`
`Operation of Power MOSFET Devices,” published in the IEEE Transactions on
`
`Power Electronics. The paper received the 2000 Best Paper Award from the Power
`
`Electronics Society. In addition, I have published several other papers in this area
`
`and I hold a patent, Patent No. 5,874,830, in the area of power supply design,
`
`titled, “Adaptively biased voltage regulator and operating method,” which was
`
`issued on February 23, 1999.
`
`B. Career History
`I am a licensed Professional Engineer in the State of Idaho and have
`6.
`
`more than 30 years of experience, including extensive experience in circuit design
`
`and manufacture of Dynamic Random Access Memory (DRAM) semiconductor
`
`integrated circuit chips and CMOS Image Sensors (CISs) at Micron Technology,
`
`Inc. (“Micron”) in Boise, Idaho. I also spent considerable time working on the
`
`development of Flash memory while at Micron. My efforts resulted in more than a
`
`2
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`Kingston Exhibit 1002 - 5
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`

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`Declaration in Support of Inter Partes Review of U.S. Patent RE45,542
`dozen patents relating to Flash memory. One of my projects at Micron included the
`
`development, design, and testing of circuit design techniques for a multi-level cell
`
`(MLC) Flash memory using signal processing for a 35 nm technology node.
`
`Among many other experiences, I led the development of the delay locked loop
`
`(DLL) in the late 1990s so that Micron DRAM products could transition to the
`
`DDR memory command standard for addressing and controlling accesses to
`
`DRAM. I also provided technical assistance with Micron’s acquisition of Photobit
`
`during 2001 and 2002, including transitioning the manufacture of CIS products
`
`into Micron’s DRAM process technology.
`
`7.
`
`From 1985 to 1993, I worked for EG&G Energy Measurements and
`
`the Lawrence Livermore National Laboratory designing nuclear diagnostic
`
`instrumentation for underground weapon tests at the Nevada test site. During this
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`time, I designed over 30 electronic and electro-optic instruments including high-
`
`speed cable and fiber-optic receiver/transmitters, PLLs, frame- and bit-syncs, data
`
`converters, streak-camera sweep circuits, Pockell’s cell drivers, micro-channel
`
`plate gating circuits, and analog oscilloscope electronics.
`
`8.
`
`I have been teaching electrical engineering since 1991. From 1991-
`
`1992, I was an adjunct faculty member in the electrical engineering department of
`
`the University of Nevada, Las Vegas.
`
`3
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`Kingston Exhibit 1002 - 6
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`Declaration in Support of Inter Partes Review of U.S. Patent RE45,542
`From 1993 to 2000, I served on the faculty at the University of Idaho
`9.
`
`as an Assistant Professor and then as an Associate Professor of Electrical
`
`Engineering.
`
`10.
`
`In 2000, I joined a new electrical and computer engineering program
`
`at Boise State University where I served as department chair from 2004 to 2007. At
`
`Boise State University, I helped establish graduate programs in electrical and
`
`computer engineering including, in 2006, the university’s second Ph.D. degree.
`
`11.
`
`In 2012, I re-joined the faculty at UNLV where I am currently a
`
`Professor of Electrical and Computer Engineering. Over the course of my career as
`
`a professor, I have advised over 85 graduate students.
`
`12.
`
`I have been recognized for my contributions as an educator in the
`
`field. While at Boise State University, I received the President’s Research and
`
`Scholarship Award (2005), Honored Faculty Member recognition (2003), and
`
`Outstanding Department of Electrical Engineering Faculty recognition (2001). In
`
`2007, I received the Frederick Emmons Terman Award (the “Father of Silicon
`
`Valley”). The Terman Award is bestowed annually upon an outstanding young
`
`electrical/computer engineering educator in recognition of the educator’s
`
`contributions to the profession. In 2011, I received the IEEE Circuits and Systems
`
`4
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`Kingston Exhibit 1002 - 7
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`Declaration in Support of Inter Partes Review of U.S. Patent RE45,542
`Education Award. I have also received the Tau Beta Pi Outstanding Electrical and
`
`Computer Engineering Professor Award the four years I have been at UNLV.
`
`13.
`
`I have more than 30 years of experience doing research and
`
`development in the area of electrical instrumentation in a multitude of areas
`
`including diagnostic electrical and electro-optic instrumentation for scientific
`
`research, integrated electrical/biological circuits and systems, array (memory,
`
`imagers, and displays) circuit design, CMOS analog and digital circuit design,
`
`CAD tool development and online tutorials, low-power interconnect and packaging
`
`techniques, design of communication/interface circuits, circuit design for the use
`
`and storage of renewable energy, and power electronics.
`
`14.
`
`I have also performed technical analysis and expert witness consulting
`
`for over 100 companies and laboratories. I have worked as a consultant at other
`
`companies designing memory chips and modules, including Sun Microsystems,
`
`Oracle Corporation, and Contour Semiconductor. I have worked at other
`
`companies designing CISs, including Aerius Photonics, Lockheed Martin, and
`
`OmniVision Technologies.
`
`15.
`
`I have given more than 50 invited talks at conferences, companies,
`
`and Universities in the areas of integrated circuit design, including: AMD; Arizona
`
`State University; Beijing Jiaotong University; Carleton University; Carnegie
`
`5
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`4820-9150-5030.v2
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`Kingston Exhibit 1002 - 8
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`Declaration in Support of Inter Partes Review of U.S. Patent RE45,542
`Mellon; Columbia University; Dublin City University (Ireland); École
`
`Polytechnique de Montréal; Georgia Tech; Gonzaga University; Hong Kong
`
`University of Science and Technology; Indian Institute of Science (Bangalore,
`
`India); Instituto de Informatica (Brazil); Instituto Tecnológico y de Estudios
`
`Superiores de Monterrey; ITESM (Mexico); Iowa State University; Laval
`
`University; Lehigh University; Princeton University; Temple University;
`
`University of Alabama; University of Arkansas; University of Buenos Aires
`
`(Argentina); University of Illinois, Urbana-Champaign; Utah State University;
`
`University of Nevada, Las Vegas; University of Houston; University of Idaho;
`
`University of Nevada, Reno; University of Macau; University of Toronto;
`
`University of Utah; Yonsei University (Seoul, Korea); University of Maryland;
`
`IEEE Electron Devices Conference (NVMTS); IEEE Workshop on
`
`Microelectronics and Electron Devices (WMED); the Franklin Institute; National
`
`Semiconductor; AMI semiconductor; Micron Technology; Rendition; Saintgits
`
`College (Kerala, India); Southern Methodist University; Sun Microsystems;
`
`Stanford University; ST Microelectronics (Delhi, India); Tower (Israel); Foveon;
`
`ICySSS keynote; and Xilinx Publications and Patents.
`
`16.
`
`I have authored many books and papers on circuit design. My
`
`published books include CMOS Circuit Design, Layout, and Simulation (Baker,
`
`R.J., Wiley-IEEE, ISBN: 978-0470881323 (3rd ed., 2010)) and CMOS Mixed-
`
`6
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`4820-9150-5030.v2
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`Kingston Exhibit 1002 - 9
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`Declaration in Support of Inter Partes Review of U.S. Patent RE45,542
`Signal Circuit Design (Baker, R.J., Wiley-IEEE, ISBN: 978-0470290262 (2nd ed.,
`
`2009) and ISBN: 978-0471227540 (1st ed., 2002)). I have also co-authored DRAM
`
`Circuit Design: Fundamental and High-Speed Topics (Keeth, B., Baker, R.J.,
`
`Johnson, B., and Lin, F., Wiley-IEEE, ISBN: 978-0-470-18475-2 (2008)), DRAM
`
`Circuit Design: A Tutorial (Keeth, B. and Baker, R.J., Wiley-IEEE, ISBN: 0-7803-
`
`6014-1 (2001)), and CMOS Circuit Design, Layout and Simulation (Baker, R.J.,
`
`Li, H.W., and Boyce, D.E., Wiley-IEEE, ISBN: 978-0780334168 (1998)). I have
`
`also contributed as an editor and co-author on several other books on CMOS
`
`circuit design and VLSI.
`
`17.
`
`I am the author and co-author of more than 100 papers and
`
`presentations in the areas of solid-state circuit design and packages. In 2000, I
`
`received the Best Paper Award from the IEEE Power Electronics Society.
`
`18.
`
`I am a named inventor on 149 U.S. patents in integrated circuit design
`
`including Flash memory, DRAM, and CMOS image sensors.
`
`C. Other Relevant Qualifications
`I currently serve, or have served, on: the IEEE Press Editorial Board
`19.
`
`(1999-2004); as editor for the Wiley-IEEE Press Book Series on Microelectronic
`
`Systems (2010-present); as the Technical Program Chair of the 2015 IEEE 58th
`
`International Midwest Symposium on Circuits and Systems (MWSCAS 2015); on
`
`7
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`Kingston Exhibit 1002 - 10
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`Declaration in Support of Inter Partes Review of U.S. Patent RE45,542
`the IEEE Solid-State Circuits Society (SSCS) Administrative Committee (2011-
`
`2016); as a Distinguished Lecturer for the SSCS (2012-2015); and as the
`
`Technology Editor (2012-2014) and Editor-in-Chief (2015-present) for the IEEE
`
`Solid-State Circuits Magazine. These meetings, groups, and publications are
`
`intended to allow researchers to share and coordinate research. My active
`
`participation in these meetings, groups, and publications allowed me to see what
`
`other researchers in the field have been doing.
`
`20.
`
`In addition to the above, I am an IEEE Fellow and a member of the
`
`honor societies Eta Kappa Nu and Tau Beta Pi.
`
`D. Materials and Other Information Considered
`I have considered information from various sources in forming my
`21.
`
`opinions. I understand that a list of exhibits considered is being submitted by
`
`Kingston. I may review additional documents filed in connection with this
`
`proceeding as they become available.
`
`II. LEGAL PRINCIPLES
`I have applied the following legal principles provided to me by
`22.
`
`counsel in arriving at the opinions set forth in this declaration.
`
`8
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`4820-9150-5030.v2
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`Kingston Exhibit 1002 - 11
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`

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`Declaration in Support of Inter Partes Review of U.S. Patent RE45,542
`A. Legal Standard for Prior Art
`I understand that a patent or other publication must first qualify as
`23.
`
`prior art before it can be used to invalidate a patent claim.
`
`24.
`
`I understand that a U.S. or foreign patent qualifies as prior art to the
`
`claims of an asserted patent if the date of issuance of the patent is prior to the
`
`invention claimed in the asserted patent. I further understand that a printed
`
`publication, such as a book or an article published in a magazine or trade
`
`publication, qualifies as prior art to the claims of an asserted patent if the date of
`
`publication is prior to the invention claimed in the asserted patent.
`
`25.
`
`I understand that a U.S. or foreign patent qualifies as prior art to the
`
`claims of an asserted patent if the date of issuance of the patent is more than one
`
`year before the filing date of the asserted patent or the filing date to which the
`
`claims of the asserted patent are entitled to claim priority, whichever is earlier. I
`
`further understand that a printed publication, such as a book or an article published
`
`in a magazine or trade publication, constitutes prior art to an asserted patent if the
`
`publication occurred more than one year before the filing date of the asserted
`
`patent or the filing date to which the claims of the asserted patent are entitled to
`
`claim priority, whichever is earlier.
`
`9
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`4820-9150-5030.v2
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`Kingston Exhibit 1002 - 12
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`

`

`Declaration in Support of Inter Partes Review of U.S. Patent RE45,542
`I understand that a U.S. patent qualifies as prior art to the asserted
`26.
`
`patent if the U.S. patent was granted on a patent application filed in the United
`
`States before the invention of the asserted patent. I understand that a U.S. patent
`
`application publication qualifies as prior art to the asserted patent if the publication
`
`was from a patent application filed in the United States before the invention of the
`
`asserted patent.
`
`27.
`
`I understand that to qualify as prior art to the claims of an asserted
`
`patent, a reference must contain an enabling disclosure that allows one of ordinary
`
`skill to make or use the claimed subject matter of the asserted patent without undue
`
`experimentation.
`
`28.
`
`I understand that documents and materials that qualify as prior art can
`
`be used to invalidate a patent claim as anticipated or as obvious.
`
`B.
`29.
`
`Legal Standard for Anticipation
`I understand that once a claim of a patent has been properly construed,
`
`the second step in determining anticipation of that patent claim requires a
`
`comparison of the properly construed claim language to the prior art on a
`
`limitation-by-limitation basis.
`
`30.
`
`I understand that a prior art reference “anticipates” an asserted claim,
`
`and thus renders the claim invalid, if that prior art reference discloses all the
`
`10
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`4820-9150-5030.v2
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`Kingston Exhibit 1002 - 13
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`Declaration in Support of Inter Partes Review of U.S. Patent RE45,542
`elements of the claim as arranged in the claim, either explicitly or inherently (i.e.,
`
`all elements are necessarily present or implied).
`
`31.
`
`I understand that an asserted claim is anticipated if the claimed subject
`
`matter was known or used in the United States before the patent’s inventor(s)
`
`invented the claimed subject matter.
`
`32.
`
`I understand that a patent claim is anticipated if before the patent’s
`
`inventor(s) invention thereof, the claimed subject matter was made in this country
`
`by another inventor who had not abandoned, suppressed, or concealed it.
`
`33.
`
`I have written this report with the understanding that in an inter partes
`
`review anticipation must be shown by a preponderance of the evidence.
`
`C. Legal Standard for Obviousness
`I have been instructed by counsel on the law regarding obviousness,
`34.
`
`and understand that even if a patent claim is not anticipated, it is still invalid if the
`
`differences between the claimed subject matter and the prior art are such that the
`
`subject matter as a whole would have been obvious at the time the invention was
`
`made to a person of ordinary skill in the pertinent art.
`
`35.
`
`I understand that a person of ordinary skill in the art provides a
`
`reference point from which the prior art and claimed invention should be viewed.
`
`11
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`4820-9150-5030.v2
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`Kingston Exhibit 1002 - 14
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`Declaration in Support of Inter Partes Review of U.S. Patent RE45,542
`This reference point prevents a person of ordinary skill from using one’s insight or
`
`hindsight in deciding whether a claim is obvious.
`
`36.
`
`I also understand that an obviousness determination includes the
`
`consideration of various factors such as (1) the scope and content of the prior art,
`
`(2) the differences between the prior art and the asserted claim, (3) the level of
`
`ordinary skill in the pertinent art, and (4) the existence of secondary considerations
`
`such as commercial success, long-felt but unresolved needs, failure of others, etc.
`
`37.
`
`I am informed that secondary indicia of non-obviousness may include
`
`(1) a long felt but unmet need in the prior art that was satisfied by the invention of
`
`the patent; (2) commercial success or lack of commercial success of processes
`
`covered by the patent; (3) unexpected results achieved by the invention; (4) praise
`
`of the invention by others skilled in the art; (5) taking of licenses under the patent
`
`by others; and (6) deliberate copying of the invention. I also understand that there
`
`must be a relationship between any such secondary indicia and the invention. I
`
`further understand that contemporaneous and independent invention by others is a
`
`secondary consideration supporting an obviousness determination.
`
`38.
`
`I understand that an obviousness evaluation can be based on a
`
`combination of multiple prior art references. I understand that the prior art
`
`references themselves may provide a suggestion, motivation, or reason to combine,
`
`12
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`Kingston Exhibit 1002 - 15
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`Declaration in Support of Inter Partes Review of U.S. Patent RE45,542
`but other times the nexus linking two or more prior art references is simple
`
`common sense. I further understand that obviousness analysis recognizes that
`
`market demand, rather than scientific literature, often drives innovation, and that a
`
`motivation to combine references may be supplied by the direction of the
`
`marketplace.
`
`39.
`
`I understand that if a technique has been used to improve one device,
`
`and a person of ordinary skill in the art would recognize that it would improve
`
`similar devices in the same way, using the technique is obvious unless its actual
`
`application is beyond his or her skill.
`
`40.
`
`I also understand that practical and common sense considerations
`
`should guide a proper obviousness analysis, because familiar items may have
`
`obvious uses beyond their primary purposes. I further understand that a person of
`
`ordinary skill in the art looking to overcome a problem will often be able to fit the
`
`teachings of multiple publications together like pieces of a puzzle, although the
`
`prior art need not be like two puzzle pieces that must fit perfectly together. I
`
`understand that obviousness analysis therefore takes into account the inferences
`
`and creative steps that a person of ordinary skill in the art would employ under the
`
`circumstances.
`
`13
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`4820-9150-5030.v2
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`Kingston Exhibit 1002 - 16
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`Declaration in Support of Inter Partes Review of U.S. Patent RE45,542
`I understand that a particular combination may be proven obvious by
`41.
`
`showing that it was obvious to try the combination. For example, when there is a
`
`design need or market pressure to solve a problem and there are a finite number of
`
`identified, predictable solutions, a person of ordinary skill has good reason to
`
`pursue the known options within his or her technical grasp because the result is
`
`likely the product not of innovation but of ordinary skill and common sense.
`
`42.
`
`I understand that the combination of familiar elements according to
`
`known methods may be proven obvious when it does no more than yield
`
`predictable results. For example, when a patent simply arranges old elements with
`
`each performing the same function it had been known to perform and yields no
`
`more than one would expect from such an arrangement, the combination is
`
`obvious. In addition, when a work is available in one field of endeavor, design
`
`incentives and other market forces can prompt variations of it, either in the same
`
`field or a different one. If a person of ordinary skill can implement a predictable
`
`variation, obviousness likely bars its patentability.
`
`43.
`
`It is further my understanding that a proper obviousness analysis
`
`focuses on what was known or obvious to a person of ordinary skill in the art, not
`
`just the patentee. Accordingly, I understand that any need or problem known in the
`
`field of endeavor at the time of invention and addressed by the patent can provide a
`
`reason for combining the elements in the manner claimed.
`
`14
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`4820-9150-5030.v2
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`Kingston Exhibit 1002 - 17
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`Declaration in Support of Inter Partes Review of U.S. Patent RE45,542
`I understand that a claim can be obvious in light of a single reference,
`44.
`
`without the need to combine references, if the elements of the claim that are not
`
`found explicitly or inherently in the reference can be supplied by the common
`
`sense of one of skill in the art.
`
`45.
`
`I understand that a person of ordinary skill could have combined two
`
`pieces of prior art or substituted one prior art element for another if the substitution
`
`can be made with predictable results, even if the swapped-in element is different
`
`from the swapped-out element. In other words, the prior art need not be like two
`
`puzzle pieces that must fit together perfectly. The relevant question is whether
`
`prior art techniques are interoperable with respect to one another, such that that a
`
`person of skill would view them as a design choice, or whether a person of skill
`
`could apply prior art techniques into a new combined system.
`
`46.
`
`It is my understanding that prior art teachings are properly combined
`
`where a person of ordinary skill in the art having the understanding and knowledge
`
`reflected in the prior art and motivated by the general problem facing the inventor,
`
`would have been led to make the combination of elements recited in the claims.
`
`Under this analysis, the prior art references themselves, or any need or problem
`
`known in the field of endeavor at the time of the invention, can provide a reason
`
`for combining the elements of multiple prior art references in the claimed manner.
`
`15
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`4820-9150-5030.v2
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`Kingston Exhibit 1002 - 18
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`Declaration in Support of Inter Partes Review of U.S. Patent RE45,542
`I have been informed and understand that the obviousness analysis
`47.
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`requires a comparison of the properly construed claim language to the prior art on
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`a limitation-by-limitation basis.
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`48.
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`I have written this report with the understanding that in an inter partes
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`review obviousness must be shown by a preponderance of the evidence.
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`D. Legal Standard for Claim Construction
`I have been instructed by counsel on the law regarding claim
`49.
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`construction and patent claims, and understand that a patent may include two types
`
`of claims, independent claims and dependent claims. An independent claim stands
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`alone and includes only the limitations it recites. A dependent claim can depend
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`from an independent claim or another dependent claim. I understand that a
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`dependent claim includes all the limitations that it recites in addition to all of the
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`limitations recited in the claim from which it depends.
`
`50.
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`It is my understanding that in proceedings before the USPTO, claims
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`are construed similarly as in district court litigation, and that this standard is
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`sometimes referred to as the Phillips standard. Under this standard, it is my
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`understanding that claim terms are given the meaning the term would have to a
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`person of ordinary skill in the art at the time of the invention, in view of the
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`specification and file history.
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`16
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`4820-9150-5030.v2
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`Kingston Exhibit 1002 - 19
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`

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`Declaration in Support of Inter Partes Review of U.S. Patent RE45,542
`[Intentionally blank]
`51.
`
`52.
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`In comparing the claims of the RE542 Patent to the prior art, I have
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`carefully considered the RE542 Patent and its file history in light of the
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`understanding of a person of skill at the time of the alleged invention.
`
`53.
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`I understand that to determine how a person of ordinary skill would
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`understand a claim term, one should look to those sources available that show what
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`a person of skill in the art would have understood disputed claim language to
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`mean. Such sources include the words of the claims themselves, the remainder of
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`the patent’s specification, the prosecution history of the patent (all considered
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`“intrinsic” evidence), and “extrinsic” evidence concerning relevant scientific
`
`principles, the meaning of technical terms, and the state of the art.
`
`54.
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`I understand that, in construing a claim term, one looks primarily to
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`the intrinsic patent evidence, including the words of the claims themselves, the
`
`remainder of the patent specification, and the prosecution history.
`
`55.
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`I understand that extrinsic evidence, which is evidence external to the
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`patent and the prosecution history, may also be useful in interpreting patent claims
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`when the intrinsic evidence itself is insufficient.
`
`56.
`
`I understand that words or terms should be given their ordinary and
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`accepted meaning unless it appears that the inventors were using them to mean
`17
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`4820-9150-5030.v2
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`Kingston Exhibit 1002 - 20
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`

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`Declaration in Support of Inter Partes Review of U.S. Patent RE45,542
`something else. In making this determination, the claims, the patent specification,
`
`and the prosecution history are of paramount importance. Additionally, the
`
`specification and prosecution history must be consulted to confirm whether the
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`patentee has acted as its own lexicographer (i.e., provided its own special meaning
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`to any disputed terms), or intentionally disclaimed, disavowed, or surrendered any
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`claim scope.
`
`57.
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`I understand that the claims of a patent define the scope of the rights
`
`conferred by the patent. The claims particularly point out and distinctly claim the
`
`subject matter which the patentee regards as his invention. Because the patentee is
`
`required to define precisely what he claims his invention to be, it is improper to
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`construe claims in a manner different from the plain import of the terms used
`
`consistent with the specification. Accordingly, a claim construction analysis must
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`begin and remain centered on the claim language itself. Additionally, the context in
`
`which a term is used in the asserted claim can be highly instructive. Likewise,
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`other claims of the patent in question, both asserted and unasserted, can inform the
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`meaning of a claim term. For example, because claim terms are normally used
`
`consistently throughout the patent, the usage of a term in one claim can often
`
`illuminate the meaning of the same term in other claims. Differences among claims
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`can also be a useful guide in understanding the meaning of particular claim terms.
`
`18
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`4820-9150-5030.v2
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`Kingston Exhibit 1002 - 21
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`

`

`Declaration in Support of Inter Partes Review of U.S. Patent RE45,542
`I understand that the claims of a patent define the purported invention.
`58.
`
`I understand that the purpose of claim construction is to understand how one
`
`skilled in the art would have understood the claim terms at the time of the
`
`purported invention.
`
`59.
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`I understand that a person of ordinary skill in the art is deemed to read
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`a claim term not only in the context of the particular claim in which the disputed
`
`term appears, but in the context of the entire patent, including the specification. For
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`this reason, the words of the claim must be interpreted in view of the entire
`
`specification. The specification is the primary basis for construing the claims and
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`provides a safeguard such that correct constructions closely align with the
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`specification. Ultimately, the interpretation to be given a term can only be
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`determined and confirmed with a full understanding of what the inventors actually
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`invented an