(12) United States Patent
`Apostol, Jr. et al.
`
`USOO6247084B1
`(10) Patent No.:
`US 6,247,084 B1
`(45) Date of Patent:
`Jun. 12, 2001
`
`(54) INTEGRATED CIRCUIT WITH UNIFIED
`MEMORY SYSTEM AND DUAL BUS
`ARCHITECTURE
`(75) Inventors: George Apostol, Jr., Santa Clara; Peter
`R. Baran, Fremont; Roderick J.
`
`McInnis, Milpitas, all of CA (US)
`
`(73) Assignee: LSI Logic Corporation, Milpitas, CA
`(US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(*) Notice:
`
`(21) Appl. No.: 09/166,262
`22) Filled:
`Oct. 5, 1998
`(22) File
`Cl. 5,
`Related U.S. Application Data
`(60) Provisional application No. 60/061,489, filed on Oct. 8,
`1997.
`7
`
`(58) Field of Search ..................................... 711/149, 147,
`711/150; 710/240, 100, 108
`References Cited
`U.S. PATENT DOCUMENTS
`
`(56)
`
`5,561,777
`
`10/1996 Kao et al. - - - - - - - - - - - - - - - - - - - - - - - - - - - - 395/405
`
`9/1998 Biswas et al. ....................... 710/244
`5,805,905
`5,822,768 * 10/1998 Shakkarwar ...
`... 711/149
`5,854,638
`12/1998 Tung .................................... 34.5/512
`* cited by examiner
`Primary Examiner Rupal D. Dharia
`(57)
`ABSTRACT
`A unified memory System includes a processor, a memor
`y Sy
`p
`y
`controller, a plurality of buS transactor circuits and a shared
`memory port. A processor bus is coupled between the
`processor and the memory controller. A first multiple-bit,
`bidirectional System bus is coupled between the shared
`memory port, the memory controller and the plurality of bus
`transactor circuits. A Second multiple-bit, bidirectional Sys
`tem buS is coupled between the memory controller and the
`
`3.
`
`- - - - - - - - - - - - - - - - - - - - - - - - - - -Toros. 708"..e plurality of buS transactor circuits.
`
`711/147; 711/149; 711/150
`
`19 Claims, 36 Drawing Sheets
`
`
`
`PROCESSOR
`
`O
`
`15A
`
`15B
`
`15C
`
`BUS
`TRAN
`SACTOR
`
`BUS
`TRANSACTOR
`
`BUS
`TRANSACTOR
`
`EXTERNA
`MEMORY
`
`Kingston Exhibit 1011 - 1
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 1 of 36
`
`US 6,247,084 B1
`
`O
`ves
`
`
`
`? --
`
`TV/NHE_LXE
`
`ÅHOWNEIN
`
`271
`
`
`
`HOSSE OOH•H
`
`
`HETTO H_LNOO
`XHOVNE IN
`
`Kingston Exhibit 1011 - 2
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 2 of 36
`
`US 6,247,084 B1
`
`99
`
`ZZ
`
`
`
`
`
`9/
`
`WOHBE
`
`(6?u00)
`
`NCISI
`
`9EST)
`
`39
`
`JÐuueOS
`
`#78
`
`38
`
`Kingston Exhibit 1011 - 3
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 3 of 36
`
`US 6,247,084 B1
`
`
`
`OxCOOOOOOO
`
`OX40000000
`
`OX2OOOOOOO
`
`OX1 FCOOOOO
`
`OX17COOOOO
`
`OX106OOOOO
`
`OX105OOOOO
`
`OX104OOOOO
`
`OX1 O3OOOOO
`
`OX102OOOOO
`
`OX1 OOOOOOO
`
`OXO8OOOOOO
`
`go
`
`90
`
`Reserved for future
`USe
`
`System memory
`
`PCI memory
`
`Flash/PROM
`
`System ROM
`
`Reserved for future
`US6
`
`Serial I/O BOCk
`Registers
`
`Parallel I/O Block
`Registers
`
`Graphics & Display
`Registers
`
`Memory Controller
`Registers
`System & CPU Config
`address Space
`(TLB & Cache Tags and Rams)
`Alias address for
`first 128M PCI memory
`
`Alias address for
`first 128M System memory
`Y. 92
`
`Kingston Exhibit 1011 - 4
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 4 of 36
`
`US 6,247,084 B1
`
`
`
`S D R A M
`
`
`
`
`
`
`
`
`
`
`
`BuS
`
`124A
`
`Serial I/O
`
`15A
`
`
`
`126A
`124B
`
`288x64
`BIU 55AM SIU
`122B
`
`PCI & Parallel
`
`126B
`
`Memory
`Controller
`14
`
`Interrupt
`110
`
`
`
`
`
`PrOCeSSOr
`16k Icache
`8K DCache
`
`PBIU
`f 12
`
`124C
`Graphics
`
`Kingston Exhibit 1011 - 5
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet S of 36
`
`US 6,247,084 B1
`
`120 - 122
`DATA(63:0
`DATA ERR
`DATA LD
`DATA GNT
`DATA EOT
`
`BIU
`
`f
`
`O
`
`CMD 63:O
`CMD LD
`CMD GNT
`CMD PWA
`CMD REQ 2:O
`
`BCLK
`RESET N
`
`124
`DOUT 63:0
`DIN (63:0)
`ADDin (8:0
`CR
`WCE
`VALID PIO
`VP ACK
`WRITE
`SIU ACK VLD
`AB ACK
`PNTR VLD
`ACK BUS (7:0
`
`HEADER ADD
`HO FULL
`SCLK
`SRESET N
`
`CMD Type
`OO - Reserved
`9. ME Write
`FIG
`- 19:Mergy Read
`
`7
`
`6 5
`
`O
`
`SSED
`NEWRAMADR
`
`O
`
`DATA CRUEUE
`
`152
`N 255
`256 - 263
`FIG.7 264-27
`272 - 279
`280 - 287
`
`
`
`15OE
`
`- 122
`
`154
`
`15OA
`15OB
`150C i?
`100 - 107h
`1 O8h - 1 OFh
`11Oh - 117h
`118h - 11 Fh
`15OD
`
`Kingston Exhibit 1011 - 6
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 6 of 36
`
`US 6,247,084 B1
`
`63 62-6O 59-52 51-46
`
`45-38
`
`CMD
`
`SSD RAMADR
`
`
`
`37-35 34 33 32
`lo
`|
`
`31-O
`
`AD
`DRESS
`
`160-
`
`FIG.8
`
`63 62-6O 59-56 55-50
`
`47-40 39-3837 36-32 31-24 23-16 15-8
`
`170 -
`
`FIG.9
`
`
`
`TYPE CMD
`
`CYCLES
`
`Description
`
`Interrupt
`Write Single (uses MASK)
`Write Block (uses BCNT)
`Read Block
`Read Reply
`Cache Line Fill
`Reserved
`
`Kingston Exhibit 1011 - 7
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 7 of 36
`
`US 6,247,084 B1
`
`
`
`Tl_Fl_Fl_Fl_Fl_Fl_Fl_Fl_Fl_J
`
`XITO
`
`—\_/—
`
`
`
`LOETVIVO
`
`
`
`[O:99] VIVO
`
`XITO
`
`CITTOIWO
`
`Kingston Exhibit 1011 - 8
`
`

`

`x=
`
`
`OldJa\si6oyJesiBay
`
`
`
`ANANOYAqVsH
`
`—_
`OldGMWA
`GIAHOVAWNDIS
`
`sOvay|HAZINONHO
`
`“NAS
`
`00g
`
`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 8 of 36
`
`US 6,247,084 B1
`
`a
`
`YHAGNOdS3AY
`
`ANANDOld
`
`YaTONVH
`
`2oO
`wn2a
`BUS_REQ
`HEADER_ACK
`HEADER_REQ
`
`Bulwoou]Hurobino
`
`
`
`sjauueyysjeuueyuD
`
`HEADER_ACK
`HEADER_RE
`
`<
`
`HEADER_ACK
`HEADER_REQ
`
`GIAYLNd
`
`sng@OV
`
` o|wW>Ciauua\e
`ii}
`
`
`fw5/>
`
`Ww
`
`DATA QUEUES
`
`Kingston Exhibit 1011 - 9
`
`Kingston Exhibit 1011 - 9
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 9 of 36
`
`US 6,247,084 B1
`
`
`
`Kingston Exhibit 1011 - 10
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 10 Of 36
`
`US 6,247,084 B1
`
`
`
`N/HgTOId
`
`N/09BTOId
`
`XOVTCHA
`
`OIGHTOITVA
`
`Kingston Exhibit 1011 - 11
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 11 of 36
`
`US 6,247,084 B1
`
`
`
`Kingston Exhibit 1011 - 12
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 12 of 36
`
`US 6,247,084 B1
`
`
`
`
`
`Multiply/
`ACCum
`Unit
`
`256
`Icache
`Set-O
`256
`Cache
`
`Set
`
`:
`
`ISU
`
`LSU
`
`BIU
`
`---------------- I
`Cache
`Invalidation
`Interface
`
`Coprocessor
`Interface
`
`
`
`SCbuS
`Interface
`
`26O
`
`OCA
`Interface
`Writeback
`Buffer
`Dcache
`-7258
`H/
`Set-1
`
`- - )
`
`26
`?
`
`
`
`WSSES
`to Memory K
`Controller
`
`262
`
`FIG.17
`
`Kingston Exhibit 1011 - 13
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 13 of 36
`
`US 6,247,084 B1
`
`22
`
`PC
`requests
`Serial
`load & grant
`subsystem
`
`12OA
`
`1.26A
`
`load & grant
`
`12OB
`
`126B
`
`Parallel
`Subsystem
`
`12OC
`
`126C
`
`
`
`
`
`46
`
`Memory
`
`load & grant
`
`Graphics
`& Display
`subsystem
`N-288
`display DMA hand shake
`12
`
`b
`US
`
`displ
`ISplay
`
`282
`&
`
`272
`
`
`
`SDRAM
`COntroller
`
`Cpu
`BIU
`
`SCBuS
`
`PrOCeSSOr
`
`270 \-
`
`N274 N276
`
`28O
`
`286
`
`FIG. 18
`
`Kingston Exhibit 1011 - 14
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 14 Of 36
`
`US 6,247,084 B1
`
`282
`Internal
`BuS
`Interface
`
`280
`External
`Memory
`Interface
`
`
`
`data (63:0)
`ConC
`data gnt 2:0
`data Id 2:O
`data err
`data eot
`cmd.63:O
`d
`O2:O
`Cmd req02:O
`cmd req12:0
`cmd Id (2:O
`Cmd gnt 2:0
`cmd pVwa (2:0)
`
`framend
`Id disp 1:0
`disp req 1:0
`288
`disp. low 1:0
`GSE, --
`Interf
`SCAop (63:O
`teaCe
`KP
`SCBPWAn He
`SCBRDYn
`-
`-
`SCDip (63:0
`SCDop (63:0)
`Memory
`Controller KR
`SCDOEn
`
`P 286
`
`CSO in 1 :O
`
`SCTBEn 7:0
`
`raSO in
`CaSO
`WeOn
`clko (1:0
`cked 1:0
`ao (13:0
`CP
`dqm 7:0
`
`3.
`
`data2mem
`mem2Cdata
`
`SCTBLn
`SCTBST
`SCTPWn
`SCTSEn
`SCTSSn
`
`clocki
`reset
`
`FIG. 19
`
`Kingston Exhibit 1011 - 15
`
`

`

`Jun. 12, 2001
`
`Sheet 15 of 36
`
`US 6,247,084 B1
`
`U.S. Patent
`
`00€
`
`ju}
`80Eeyepgwiew
`
`J91]01]U09|¢Alowew|aSLE
`‘guiygew|POEiayeyseo,
`
`
`neu_oseo‘OOD! fo:Payxo‘U_osel
`
`_ouubp‘oe‘U-08Mrev
`0¢‘SIA|
`
`[o:eLlvuaM
`
`[0:4]Wod
`
`Kingston Exhibit 1011 - 16
`
`Kingston Exhibit 1011 - 16
`
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 16 of 36
`
`US 6,247,084 B1
`
`
`
`
`
`address
`
`OX102OOOOO
`
`--OXOOO
`
`--OX008
`
`--OXOO
`--OXO18
`
`--OXO20
`--OX100
`--OX108
`--OX11 O
`--OX118
`--OX140
`
`--OX178
`
`+0x280
`
`are 3CCeSS Description
`memory controller base address
`reset and StatuS
`system configuration register
`memory configuration register
`memory initialization and refresh register
`Frame configuration: x width and y height
`starting tile address and tile configuration for frame 0
`starting tile address and tile configuration for frame 1
`W
`Rw starting tile address and tile configuration for frame 2
`Rw starting tile address and tile configuration for frame 3
`
`R/W
`dither LUTI7:0
`Rw display dma control register
`FIG.21A
`
`Kingston Exhibit 1011 - 17
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 17 of 36
`
`US 6,247,084 B1
`
`
`
`address
`--OX288
`--OX22O
`--OX21 O
`--OX218
`--OX2OO
`--OX208
`--OX3OO
`+Ox308
`--OX31 O
`--OX318
`--Ox320
`--Ox328
`--OX33O
`--OX338
`--OX340
`--OX348
`--OX350
`--Ox358
`--Ox36O
`--Ox368
`--OX37O
`--OX378
`--OX38O
`--OX388
`--OX390
`
`access Description
`display drma ID register
`packer data register
`packer data starting address register
`packer data size register
`w load window cache register
`w flush window cache register
`R
`window current address register O
`R
`window remain registero
`Rw window starting address register 0
`Rw window size register 0
`R
`window current address register 1
`R
`window remain register 1
`Rw window starting address register 1
`Rw window size register 1
`R
`window current address register 2
`R
`window remain register 2
`Rw window starting address register 2
`Rw window size register 2
`window current address register 3
`window remain register 3
`window starting address register 3
`window size register 3
`display current offset register 0
`display remain register 0
`display starting offset register 0
`FIG.21B
`
`Kingston Exhibit 1011 - 18
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 18 of 36
`
`US 6,247,084 B1
`
`
`
`address
`
`name access Description
`display Screen size register 0
`display current offset register 1
`display remain register 1
`display starting offset register 1
`display screen size register 1
`window cache state register 0
`window cache state register 1
`window cache state register 2
`window cache state register 3
`Window Cache
`
`test configuration
`chip version number
`
`FIG.21C
`
`Kingston Exhibit 1011 - 19
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 19 Of 36
`
`US 6,247,084 B1
`
`
`
`
`
`BitS
`
`access
`
`6 3 2
`
`Description and default value
`system software reset
`software reset to memory controller
`reserved
`
`FIG.22
`
`
`
`
`
`
`
`access
`
`3 2
`
`Description and default value
`boot device
`0 - parallel port (default)
`1 - serial port
`0 - regular Sdram (default)
`1 - Sodram with virtual channel
`memory type
`00 - 16Mbit x8 scram (default)
`O - 16Mbit x 16 Sdram
`10 - 64Mbit x8 Scram
`11 - 64Mbit x 16 Sdram
`refresh type
`OO -burst of 1 (default)
`01 -burst of 2
`1O-burst of 3
`dither Control
`O: no dither
`1: dither, 32 bits cpu data becomes 16 bits
`Color depth for frame 00,
`00: 8 bits per pixel (default)
`01: 16 bits per pixel
`color depth for frame 1, default = 00
`color depth for frame 2, default = 00
`color depth for frame 3, default = 00
`0 - big endian (default)
`1 - Small endian
`reServerd
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`FIG.23
`
`
`
`
`
`
`
`5 64
`
`11 - 10
`13 - 12
`
`15 - 14
`
`1
`
`63 - 17
`
`Kingston Exhibit 1011 - 20
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 20 of 36
`
`US 6,247,084 B1
`
`aCCeSS
`
`Description and default value
`CAS in latency, default = 3
`tRCD, delay time ACT to READ/WRITE command
`default = 3
`
`7 - 4
`
`12 - 11 R
`16-15 R
`
`W
`
`tRSC, default = 2
`
`FIG.24
`
`
`
`access Description and default value
`refresh period in number clock cycle
`default = 31250 assuming 100 MHz
`wait cycles after power on
`default = 0x0400
`
`27 - 16 R/W
`
`31 - 28 R/W
`
`FIG.25
`
`
`
`access Description and default value
`Bits
`11 - O R/W
`Fwidth, number of pixels in the horizontal direction,
`default = 1024
`Fheight, number of pixels in the vertical direction,
`default = 768
`
`23 - 12 R/W
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Kingston Exhibit 1011 - 21
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 21 of 36
`
`US 6,247,084 B1
`
`access Description and default value
`
`Xtile: number of tiles in the horizontal direction
`default = 4
`
`Ytile: number of tiles in the vertical direction
`default = 3
`upper 16 bits of the Starting Tile address for Framex
`(note: lower 16 bits are always zero)
`reserved
`FIG.27
`
`Resolution
`
`1024x768
`
`800x600
`
`640x480
`
`Xtile
`(8bits/pixel)
`
`Xtile
`(16 bits/pixel)
`
`FIG.28
`
`
`
`
`
`
`
`
`
`Bits
`
`
`
`W/R
`
`access Description and default value
`W/R
`0: frame not ready to Swap
`1: frame ready to swap
`reset after frame Swap
`Both primary and secondary dma start next display
`from frame:
`O: as specified in display dmaid bit 5-4 and bit 1-0
`1: as specified in display dmaid bit 7-6 and bit 3-2
`This bit is toggled at VSync
`reserved
`FIG.29
`
`
`
`
`
`
`
`63 - 2 -
`
`Kingston Exhibit 1011 - 22
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 22 of 36
`
`US 6,247,084 B1
`
`Display DMAID Register
`
`access Description and default value
`primary display OID (default = 00)
`W primary display 1 D (default = 00)
`W secondary display OID (default = 00)
`secondary display 1 D (default = 00)
`reserved
`
`FIG.30
`
`Display Starting Offset Register
`
`access Description and default value
`RW Xoffset, X offset location from frame origin
`11 -
`23 - 12 R/W
`Yoffset, offset location from frame origin
`63 - 24
`reserved
`FIG.31
`
`Display screen Size Register
`
`
`
`
`
`63-24 -
`
`reserved
`FIG.32
`
`Kingston Exhibit 1011 - 23
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 23 of 36
`
`US 6,247,084 B1
`
`Dither LUT
`
`access Description and default value
`2-0 RW Blue LUT for x0= 0
`Blue LUT for x(O) = 0
`W
`5-3 R/W
`Green LUT for x(O) = 0
`Green LUT for x(O) = 0
`8-6 R/W
`Red LUT for x(0)=0
`Red LUT for x(O) = 0
`12-9 Rw Blue LUT for x(0) = 1
`Blue LUT for x(O) = 1
`15-13 Rw Green LUT for x(O) = 1
`Green LUT for x(O) = 1
`18- 16 R/W
`Red LUT for x(0)=1
`Red LUT for x(O) = 1
`63-24 -
`reserved
`reserved
`FIG.33
`
`15 - 13
`
`18 - 16
`
`63 - 24
`
`Window Starting Address Register
`Bits
`access Description and default value
`starting memory address for linear access
`Xoffset from frame origin for tile access
`yoffset from frame origin for tile access
`
`23 - 12
`
`25 - 24 R/W
`
`63-27 -
`
`Frame id, for tile access
`O: use frame 0,
`1: use frame 1
`2: use frame 2,
`3: use frame 3
`reserved
`FIG.35
`
`
`
`
`
`
`
`Window size register
`Bits
`access Description and default value
`byte count for linear access
`Pwidth, X width of tile access
`Pheight, Y height of tile access
`reserved
`FIG. 36
`
`23 - 12 R/W
`63 - 24 -
`
`
`
`
`
`Kingston Exhibit 1011 - 24
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 24 of 36
`
`US 6,247,084 B1
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`g|<------
`
`---------------------------------+------------------------------+------*------------------- — I — I —<)
`
`No.) ¿ )
`
`§§§§)
`
`
`
`Kingston Exhibit 1011 - 25
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 25 of 36
`
`US 6,247,084 B1
`
`Bits
`
`aCCGSS
`
`3 y O
`
`Load window cache register
`Description and default value
`starting segment to load
`: start at +0x400 (default)
`: Start at --OX480
`: Start at --0x500
`: Start at +0x580
`: Start at +0x600
`: Start at +OX680
`: Start at --Ox7OO
`: Start at +OX78O
`segment count
`: 4 segments (1024 bytes)
`: 1/2 segments (128 bytes)
`: 1 segments (256 bytes)
`: 1 and 1/2 segments (384 bytes)
`: 2 segments (512 bytes)
`: 2 and 1/2 segments (640 bytes)
`: 3 segments (768 bytes)
`: 3 and 1/2 segments (896 bytes)
`
`5 4
`
`
`
`
`
`
`
`window dma pointer
`0: reference to window starting address and size regs
`O in --OX300 to --Ox318
`1: reference to window starting address and size regs
`1 in +0x320 to --Ox338
`2: reference to window starting address and size regs
`2 in +0x340 to +0x358
`3: reference to window starting address and size regs
`3 in --Ox360 to --OX378
`
`
`
`
`
`1: Start new dma
`O: COntinue dma
`1: tiling frame buffer load
`O:linear memory load
`1: enable interrupt after complete loading
`O: disable interrupt
`reserved
`O: load complete
`1: load dma in progress
`This bit is set at load and reset at load Completion.
`
`FIG. 37
`
`
`
`1 O
`
`14 - 11
`
`1 5
`
`63 - 24
`
`Kingston Exhibit 1011 - 26
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 26 of 36
`
`US 6,247,084 B1
`
`
`
`5 4
`
`
`
`
`
`
`
`
`
`
`
`
`
`Flush window cache register
`Bits
`access Description and default value
`3 - O
`starting segment to flush
`R/W
`: start at +0x400 (default)
`: Start at --Ox48O
`: Start at +OX500
`: Start at +0x580
`: Start at --OX6OO
`: Start at --OX680
`: Start at --Ox7OO
`: Start at +OX78O
`number of segment to flush
`0: 4 segments (1024 bytes)
`1: 1/2 segments (128 bytes)
`2: 1 segments (256 bytes)
`3:1 and 1/2 segments (384 bytes)
`4: 2 segments (512 bytes)
`5: 2 and 1/2 segments (640 bytes)
`6:3 segments (768 bytes)
`7: 3 and 1/2 segments (896 bytes)
`pixel dma pointer
`0: reference to pixel starting address and size regs 0
`1: reference to pixel starting address and size regS 1
`2: reference to pixel starting address and size regs 2
`3: reference to pixel starting address and size regs 3
`1: Start new dma
`O: COntinue dma
`1: tiling frame buffer flush
`0: linear memory flush
`1: enable interrupt after Complete flushing
`O: disable interrupt
`1. opaque mode
`O: OverWrite mode
`reserved
`O: flush complete
`1: flush dma in progress
`This bit is set at flush reset at flush completion.
`
`1 O
`
`1 1
`
`4 - 12
`
`1 5
`
`63 - 24
`
`FIG 38
`
`Kingston Exhibit 1011 - 27
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 27 Of 36
`
`US 6,247,084 B1
`
`
`
`
`
`
`
`Window cache mode register
`Description and default value
`
`R/W
`
`mode
`00: ide
`O1: clean
`10: dirty
`11: reserved
`
`63-32 -
`
`reserved
`FIG. 39
`
`Packer data register
`access Description and default value
`7 - O W
`write an 8 bit pixel
`W
`write a 16 bit pixel
`read an 8 bit pixel
`read a 16 bit pixel
`reServed
`FIG.40
`
`Packer data starting address register
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`s
`
`15 - 10 R/W
`
`access Description and default value
`Starting packer location in window cache
`Xwidth dw: number doubleWord in X direction is cached
`color depth
`00: 8 bits per pixel
`01: 16 bits per pixel
`
`FIG.41
`
`
`
`Kingston Exhibit 1011 - 28
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 28 of 36
`
`US 6,247,084 B1
`
`Packer data size register
`access Description and default value
`object x size
`
`R/W
`R/W
`
`object y size
`put 0
`don't care
`
`FIG.42
`
`Display current address register
`
`Bits
`
`access Description and default value
`
`
`
`
`
`
`
`
`
`63-24 -
`
`reserved
`FIG.43
`
`Display remain size register
`
`63 - 24 -
`
`reserved
`FIG.44
`
`Kingston Exhibit 1011 - 29
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 29 Of 36
`
`US 6,247,084 B1
`
`Window current address register
`access Description and default value
`Current address for linear access
`Current Xoffset from frame origin for tile access
`Current yoffset from frame origin for tile access
`Frame id, for tile access
`0: use frame 0, (default)
`1: uSe frame 1
`2: use frame 2,
`3: use frame 3
`
`FIG.45
`
`
`
`Window remain register
`access Description and default value
`remaining byte count for linear access
`remainging Pwidth,
`X remain pixels in the line for tile access
`remaining Pheight, Y remain of tile access
`reserved
`
`FIG.46
`
`PIO Read Respond Timing
`
`CMD LD
`
`CMD GNT
`/
`\
`MP-XRRXData)-
`FIG.47
`
`Kingston Exhibit 1011 - 30
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 30 Of 36
`
`US 6,247,084 B1
`
`Cache Line Fill Response Timing
`
`CMD LD R
`
`CMD
`
`(CLF)(Data)(Data)(Data)(Data)
`FIG.48
`
`PIO Write Timing
`
`/
`
`N
`
`CMD LD
`CMD GNT
`CMD
`PWA
`
`FIG.49
`
`PIO Read Timing
`
`CMD LD
`CMD GNT
`CMD
`
`/
`
`\
`
`RBK
`FIG.50
`
`DMA Request Timing
`
`CMD LD
`
`CMD GNT
`CMD
`
`/
`
`\
`Xeace
`FIG.51
`
`Kingston Exhibit 1011 - 31
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 31 of 36
`
`US 6,247,084 B1
`
`CLK
`RESET n
`
`DATA (63:0
`CMD (63:0)
`DATA LD
`DISPLD 1:0
`CMD LD
`
`DATA GNT
`CMD GNT
`CMD PWA -- GRAPHCS/
`FRAMEND -- st SEM
`CMD REQ1:O) --
`DISP REQ1:0) --
`DISPLOW 1:0 -H
`
`TO
`Memo
`Eller
`
`DCLK
`FPSHIFT
`FPFRAME
`FPLINE
`DRDY
`ESE I:
`5:0
`SSE Flat Panel
`PCLK
`
`DASUB
`DAVSS
`DAVOD
`DAVSSR To CRT
`DAVSSG
`DAVSSB
`REF
`VREFIN
`OUTR
`OUTG
`OUTEB
`COMP
`VSYNC
`HSYNC
`BLANK
`
`FIG.52
`
`
`
`DISP LD 1:O) Signal Format
`DMA data when DATA LD
`aSSertS
`primary display data stream
`secondary
`display data stream
`Invalid
`
`FIG.53
`
`Kingston Exhibit 1011 - 32
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 32 of 36
`
`US 6,247,084 B1
`
`Special Screen Block Command Header Format
`63 62-6O 59-52 51-4847 46-38
`37-32 31 30-2625-24. 23-12
`
`11-O
`
`CMD Width
`
`RAMADRBSize
`
`YStart
`
`XStart
`
`FIG. 54
`
`Data Bus
`CMD BuS
`
`
`
`126C
`1.
`
`Graphics
`
`DPRAM
`
`22
`
`FIG.55
`
`7O
`2
`
`192-287
`
`
`
`
`
`1. 122C
`
`Graphics Subsystem DPRAM Partition
`704A
`Primary Display QUEUE ED 0xc0-0x11 f(96)
`704B
`C 0x90-0xbf(48)
`704
`
`144-191 CEO BitBLT Data Buffer
`
`
`
`
`
`64-127 Oc
`
`32-63
`
`O-31
`
`
`
`ED 0x40-0x7f(64)
`7O4E
`Ox20–0x3F(32)
`7O4F
`CURSOR Ram ED 0x0-0x1 f(32)
`
`BitMap Pattern Buffer
`
`Kingston Exhibit 1011 - 33
`
`

`

`U.S. Patent
`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 33 of 36
`
`US 6,247,084 B1
`US 6,247,084 B1
`
`uoljasqns
`
`0}212g
`
`Aeidsiq
`
`BSL
`
`IpyJapooeq
`
`d/lWWddd
`
`AdJPPYB[ONUOD
`
`ydn49}u}
`
`Icet
`
`
`
`
`
`
`
`
`beyAejdsiq---~--------------
`
`beyiosund--------------
`“OsaGNO
`
`8S“Old
`
`ZS‘Sld
`
`Kingston Exhibit 1011 - 34
`
`Kingston Exhibit 1011 - 34
`
`
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 34 of 36
`
`US 6,247,084 B1
`
`
`
`
`
`|
`
`|X|OOIEX | uO??ejedO§§G | lexid-195 |9 |
`
`Kingston Exhibit 1011 - 35
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 35 0f 36
`
`US 6,247,084 B1
`
`Control
`State
`Machine
`
`Register
`Sets
`
`
`
`Data Path
`
`FIG.60
`
`Kingston Exhibit 1011 - 36
`
`

`

`U.S. Patent
`
`Jun. 12, 2001
`
`Sheet 36 of 36
`
`US 6,247,084 B1
`
`
`
`
`
`
`
`DATAN
`DATA OUT
`ADDRESS
`CONTROL
`
`808
`
`MicroController
`
`Clock
`
`32
`32
`9
`5
`
`(f)
`.
`O CO
`
`l ES (VO
`
`16
`
`800
`
`25MB/Second
`25MB/Second TTT
`8
`8
`R
`T
`TT
`
`Fast-Ethernet
`
`MII(18)
`
`Placed
`Data-path
`
`1.5MB/second
`8 TTT
`1.5MB/second 8
`Universal
`TS Serial BuS
`
`Serial-A(2)
`
`Serial-B(2)
`Serial-C(2)
`Serial-D(2)
`
`1 26c-
`
`3.2MB/second
`3.2MB/second 8 TTT
`8
`T
`A
`232 s
`In CS
`-
`C
`sad, al
`s loo
`g|9th
`an
`
`
`
`
`
`RAM
`AC-97
`Host Controller
`RAM
`
`AC-link(6)
`BEEP
`
`806
`TWS(4)
`SmartCard
`
`GPIO
`
`FIG.61
`
`Kingston Exhibit 1011 - 37
`
`

`

`US 6,247,084 B1
`
`1
`INTEGRATED CIRCUIT WITH UNIFIED
`MEMORY SYSTEM AND DUAL BUS
`ARCHITECTURE
`
`CROSS-REFERENCE TO RELATED
`APPLICATION
`This application claims the benefit of U.S. Provisional
`Application Serial No. 60/061,489, filed Oct. 8, 1997, which
`is hereby incorporated by reference.
`
`BACKGROUND OF THE INVENTION
`The present invention relates to integrated circuits and, in
`particular, to an integrated circuit having a unified memory
`architecture.
`Unified memory architectures have been used for various
`computer applications, Such as network computers, Internet
`appliances and mission specific terminal applications. In a
`typical unified memory architecture, all devices requiring
`access to memory are coupled to a common System buS.
`These devices can include a processor, an input-output
`device or a graphics device, for example. A memory con
`troller arbitrates access to memory between the various
`devices.
`Memory latency is a common difficulty in unified
`memory architectures Since each device must arbitrate for
`access to memory over the System bus. Latency can be
`reduced by requesting bursts of data from memory. For
`example, graphics devices may request bursts of display
`data from a frame buffer. Since graphics devices continually
`Supply data to a Screen display, these devices have a high
`bandwidth requirement and cannot easily accommodate
`long memory latencies. On the other hand, processors typi
`cally request Specific data from memory or another device
`and then wait for the data without giving up access to the
`System bus. Also, processors require a relatively high pri
`ority. This often results in contention for the system bus
`between the processor and devices having high bandwidth
`requirements.
`A conventional System with multiple bus masters uses an
`address bus and a data bus to control the memory System.
`Typically, both of these buSSes are arbitrated for and granted
`to one master at a time. Many cycles of bus time are lost due
`to dead time between masters, and time required for each
`master to communicate its data request to the memory
`controller. In addition, the processor uses the same bus for
`doing “program Input/Output functions, which are very
`inefficient in terms of bus utilization.
`A typical System that includes a raster Scan display output
`for graphics uses a Second memory System for this time
`critical function. Not only does this extra memory System
`increases cost, but the overall performance of the System is
`impacted due to the need for the data to be copied from
`processor memory Space into the display memory Space.
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`SUMMARY OF THE INVENTION
`The unified memory System of the present invention
`provides a high enough bandwidth to enable a graphics and
`display Subsystem to use the Same memory as a processor
`and other bus transactor circuits. The unified memory Sys
`tem includes a processor, a memory controller, a plurality of
`buS transactor circuits and a shared memory port. A proces
`Sor bus is coupled between the processor and the memory
`controller. A first multiple-bit, bidirectional system bus is
`coupled between the shared memory port, the memory
`controller and the plurality of buS transactor circuits. A
`
`60
`
`65
`
`2
`Second multiple-bit, bidirectional System bus is coupled
`between the memory controller and the plurality of bus
`transactor circuits.
`Another aspect of the present invention relates to a
`method of passing data between a shared memory port, a
`memory controller and a plurality of buS transactor circuits,
`the method includes: passing memory data between the
`shared memory port, the memory controller and the plurality
`of bus transactor circuits over a multiple-bit, bidirectional
`data bus, passing non-memory data between the memory
`controller and the plurality of buS transactor circuits over a
`multiple-bit, bidirectional command bus, controlling acceSS
`by the plurality of bus transactor circuits to the data bus with
`the memory controller; and controlling access by the plu
`rality of bus transactor circuits to the command bus with the
`memory controller independently of access to the data bus.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a block diagram of an integrated circuit accord
`ing to one embodiment of the present invention.
`FIG. 2 is a block diagram showing the integrated circuit
`coupled to a variety external devices.
`FIG. 3 is a memory map of the integrated circuit.
`FIG. 4 is a more detailed block diagram of the integrated
`circuit, according to one embodiment of the present inven
`tion.
`FIG. 5 is a diagram illustrating inputs and outputs of a
`System buS interface unit in a bus transactor circuit within
`the integrated circuit.
`FIG. 6 is a diagram illustrating an acknowledge message
`format.
`FIG. 7 is a diagram illustrating logical separation of a dual
`port RAM in the system bus interface unit shown in FIG. 5.
`FIG. 8 is a diagram illustrating a command buS message
`header format.
`FIG. 9 is a diagram illustrating a command buS message
`header format for a Screen block transfer.
`FIG. 10 is a table illustrating available transaction types
`of a command field in the header formats of FIGS. 8 and 9.
`FIG. 11 is a waveform diagram illustrating data bus
`timing within the integrated circuit.
`FIG. 12 is a waveform diagram illustrating command bus
`within the integrated circuit.
`FIG. 13 is a block diagram illustrating an example of a
`subsystem interface to the DPRAM shown in FIG. 5.
`FIG. 14 is a waveform diagram illustrating waveforms in
`the subsystem interface shown in FIG. 13 during a PIO read.
`FIG. 15 is a waveform diagram illustrating waveforms in
`the subsystem interface shown in FIG. 13 during a PIO
`write.
`FIG. 16 is a waveform diagram illustrating waveforms
`during outbound data transferS.
`FIG. 17 is a block diagram of a processor in the integrated
`circuit according to one embodiment of the present inven
`tion.
`FIG. 18 is a simplified block diagram illustrating connec
`tion of a memory controller to the System blocks of inte
`grated circuit 10.
`FIG. 19 is a diagram illustrating inputs and outputs of the
`memory controller shown in FIG. 18.
`FIG. 20 is a block diagram of an interface between the
`memory controller and external memory.
`FIGS. 21A-21C together form a table of memory con
`troller registers.
`
`Kingston Exhibit 1011 - 38
`
`

`

`US 6,247,084 B1
`
`1O
`
`3
`FIG. 22 is a table which defines each bit of a reset and
`Status register.
`FIG. 23 is a table which defines each bit of a system
`configuration register.
`FIG. 24 is a table which defines each bit of a memory
`configuration register.
`FIG. 25 is a table which defines each bit of a memory
`initialization and refresh register.
`FIG. 26 is a table which defines each bit of a frame
`configuration register.
`FIG. 27 is a table which defines each bit of frame starting
`tile address and tile configuration registers.
`FIG. 28 is a table which lists common frame resolution
`15
`numbers.
`FIG.29 is a table which defines each bit of a display DMA
`control register.
`FIG.30 is a table which defines each bit of a display DMA
`ID register.
`FIG. 31 is a table which defines each bit of a display
`Starting offset register.
`FIG. 32 is a table which defines each bit of a display
`Screen size register.
`FIG. 33 is a table which defines each bit of a dither LUT
`25
`register.
`FIG. 34 is a diagram illustrating how pixel data is cached
`in a window cache.
`FIG. 35 is a table which defines each bit of a window
`Starting address register.
`FIG. 36 is a table which defines each bit of a window size
`register.
`FIG.37 is a table which defines each bit of a load window
`cache register.
`FIG.38 is a table which defines each bit of a flush window
`cache register.
`FIG. 39 is a table which defines each bit of a window
`cache Status register.
`FIG. 40 is a table which defines a packer data register.
`FIG. 41 is a table which defines each bit of a packer
`Starting address register.
`FIG. 42 is a table which defines each bit of a packer data
`Size register.
`FIG. 43 is a table which defines each bit of display current
`address registers.
`FIG. 44 is a table which defines each bit of display remain
`Size registers.
`FIG. 45 is a table which defines each bit of a window
`current address register.
`FIG. 46 is a table which defines each bit of window
`remain registers.
`FIG. 47 is a waveform diagram illustrating PIO read
`response timing.
`FIG. 48 is a waveform diagram illustrating cache line fill
`response timing.
`FIG. 49 is a waveform diagram illustrating PIO write
`timing.
`FIG. 50 is a waveform diagram illustrating PIO read
`timing.
`FIG. 51 is a waveform diagram illustrating DMA request
`timing.
`FIG. 52 is a diagram illustrating interface Signals to and
`from a graphics and display Subsystem within the integrated
`circuit.
`
`35
`
`4
`FIG. 53 is a table indicating a DISP LD1:0 signal
`format.
`FIG. 54 is a diagram of a DMA command header for
`Screen relative addressing direct memory accesses (DMAS).
`FIG. 55 is a block diagram of the graphics and display
`Subsystem.
`FIG. 56 is a diagram illustrating partitioning of a DPRAM
`in the graphics and display Subsystem.
`FIG. 57 is a simplified block diagram of a data path a bus
`interface unit of the graphics and display Subsystem.
`FIG. 58 is a simplified block diagram of a subsystem
`interface unit of the graphics and display Subsystem.
`FIG. 59 is a block diagram of a pixel pipe section of the
`graphics and display Subsystem.
`FIG. 60 is a block diagram of a graphics BitBLT data flow
`through the graphics and display Subsystem.
`FIG. 61 is a block diagram of a serial Subsystem in the
`integrated circuit.
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`The integrated circuit of the present invention has a
`unified memory and dual bus architecture which maximizes
`bandwidth to and from an external memory device while
`minimizing latency for individual Subsystems that compete
`for access to the memory device.
`FIG. 1 is a block diagram of the integrated circuit of the
`present invention. Integrated circuit 10 includes processor
`12, memory controller 14, plurality of buS transactor circuits
`15A-15C, shared memory port 20 and dual system buses 22
`and 24. Processor 12 is coupled to memory controller 14
`over a bidirectional processor buS 26 which includes pro
`cessor address lines 28, processor control lines 30 and
`processor data lines 32 which allow processor 12 to com
`municate with memory controller 14.
`Memory controller 14 is coupled to shared memory port
`20 and system buses 22 and 24. Shared memory port 20
`includes a memory address interface 40, a memory control
`interface 42 and a memory data interface 44. Memory data
`interface 44 is coupled to system bus 22. Shared memory
`port 20 is coupled to an external memory d