`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`KINGSTON TECHNOLOGY COMPANY, INC.,
`Petitioner,
` v.
`MEMORY TECHNOLOGIES, LLC,
`Patent Owner
`
`
`
`Case No.: To Be Assigned
`U.S. Patent No. 7,739,487
`
`
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 7,739,487
` Mail Stop “Patent Board”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`4836-7094-8485
`
`

`

`U.S. Patent No. 7,739,487
`Petition for Inter Partes Review
`
`TABLE OF CONTENTS
`I.
`INTRODUCTION AND STATEMENT OF RELIEF REQUESTED (37
`C.F.R. §42.22(a)) ............................................................................................. 1
`II. MANDATORY NOTICES ............................................................................. 2
`A.
`Real Party-In-Interest (37 C.F.R. §42.8(b)(1)) ..................................... 2
`B.
`Identification of Related Matters (37 C.F.R. §42.8(b)(2)) .................... 2
`C.
`Counsel and Service Information .......................................................... 3
`D.
`3
`E.
`(37 C.F.R. §§42.8(b)(3) & (b)(4)) ......................................................... 3
`F.
`Payment of fees (37 C.F.R. §42.103) .................................................... 3
`III. REQUIREMENTS FOR INTER PARTES REVIEW ...................................... 3
`A.
`Identification of Challenge .................................................................... 3
`IV. BACKGROUND OF THE TECHNOLOGY .................................................. 5
`A. MMC Cards ........................................................................................... 5
`B.
`Booting from Flash Memory Devices ................................................... 8
`C.
`Booting from Removable Flash Memory Devices ............................. 11
`V. OVERVIEW OF THE ’487 PATENT .......................................................... 13
`VI. SUMMARY OF THE PROSECUTION HISTORY ..................................... 16
`VII. CLAIM CONSTRUCTION .......................................................................... 18
`A.
`“data frame” ........................................................................................ 20
`VIII. A PERSON OF ORDINARY SKILL IN THE ART .................................... 20
`IX. DESCRIPTION OF THE PRIOR ART ........................................................ 21
`A.
`Toombs (Ex. 1005) .............................................................................. 21
`B. McClain (Ex. 1006) ............................................................................. 21
`C.
`Kozakai (Ex. 1007) .............................................................................. 22
`D. Kurakata (Ex. 1008) ............................................................................ 22
`X. GROUND 1: CLAIMS 6, 7, 20, AND 21 ARE RENDERED OBVIOUS
`BY TOOMBS AND MCCLAIN. .................................................................. 23
`A.
`Claim 6 ................................................................................................ 31
`1.
`Claim 6 [preamble] ................................................................... 31
`2.
`Claim 6[a] ................................................................................. 35
`3.
`Claim 6[b] ................................................................................. 35
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`U.S. Patent No. 7,739,487
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`4.
`Claim 6[c] ................................................................................. 38
`B.
`Claim 7 ................................................................................................ 41
`C.
`Claim 20 .............................................................................................. 43
`1.
`Claim 20 [preamble] ................................................................. 43
`To the extent that the preamble is limiting, Toombs and McClain
`disclose ...................................................................................... 43
`2.
`Claim 20[a] ............................................................................... 43
`3.
`Claim 20[b] ............................................................................... 44
`4.
`Claim 20[c] ............................................................................... 45
`5.
`Claim 20[d] ............................................................................... 46
`D.
`Claim 21 .............................................................................................. 47
`XI. GROUND 2: CLAIMS 6, 7, 20, AND 21 ARE RENDERED OBVIOUS
`BY TOOMBS, MCCLAIN, AND KOZAKAI. ............................................ 48
`A.
`Claim 6 ................................................................................................ 50
`1.
`Claim 6 [preamble] ................................................................... 50
`2.
`Claim 6[a] ................................................................................. 51
`3.
`Claim 6[b] ................................................................................. 51
`4.
`Claim 6[c] ................................................................................. 53
`B.
`Claim 7 ................................................................................................ 54
`C.
`Claim 20 .............................................................................................. 56
`1.
`Claim 20 [preamble] ................................................................. 56
`2.
`Claim 20[a] ............................................................................... 57
`3.
`Claim 20[b] ............................................................................... 57
`4.
`Claim 20[c] ............................................................................... 57
`5.
`Claim 20[d] ............................................................................... 57
`D.
`Claim 21 .............................................................................................. 59
`XII. GROUND 3: CLAIMS 13, 26, 42, AND 52 ARE RENDERED OBVIOUS
`BY TOOMBS, MCCLAIN, AND KURAKATA. ........................................ 60
`A.
`Claim 13 .............................................................................................. 62
`1.
`Claim 13 [preamble] ................................................................. 62
`2.
`Claim 13[a] ............................................................................... 63
`3.
`Claim 13[b] ............................................................................... 66
`4.
`Claim 13[c] ............................................................................... 67
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`U.S. Patent No. 7,739,487
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`B.
`Claim 26 .............................................................................................. 70
`1.
`Claim 26 [preamble] ................................................................. 70
`2.
`Claim 26[a] ............................................................................... 70
`3.
`Claim 26[b] ............................................................................... 70
`4.
`Claim 26[c] ............................................................................... 71
`5.
`Claim 26[d] ............................................................................... 71
`C.
`Claim 42 .............................................................................................. 74
`D.
`Claim 52 .............................................................................................. 74
`XIII. CONCLUSION .............................................................................................. 75
`
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`U.S. Patent No. 7,739,487
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`Table of Authorities
`Cases
`KSR Int’l Co. v. Teleflex, Inc.,
`127 S.Ct. 1727 (2007) ...................................................................... 30, 50, 62, 66
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) ................................................................... 18, 19
`Statutes and Codes
`United States Code
`Title 35, section 101 ............................................................................................ 17
`Title 35, section 102 ............................................................................................ 17
`Title 35, section 102(a) .....................................................................................4, 5
`Title 35, section 102(b) .....................................................................................4, 5
`Title 35, section 102(e) .....................................................................................4, 5
`Title 35, section 103 .................................................................................... passim
`Title 35, section 112 ............................................................................................ 20
`Title 35, section 282(b) ....................................................................................... 18
`Rules and Regulations
`Code of Federal Regulations
`Title 37, section 42.10(b) ...................................................................................... 3
`Title 37, section 42.103 ......................................................................................... 3
`Title 37, section 42.104(b) .................................................................................... 3
`Title 37, section 42.108(c) .................................................................................. 19
`Title 37, section 42.22(a) ...................................................................................... 1
`Title 37, section 42.8(b)(1) ................................................................................... 2
`Title 37, section 42.8(b)(2) ................................................................................... 2
`Title 37, section 42.8(b)(3) ................................................................................... 3
`Title 37, section 42.8(b)(4) ................................................................................... 3
`Federal Register
`Vol. 83, No. 51340 .............................................................................................. 18
`
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`U.S. Patent No. 7,739,487
`Petition for Inter Partes Review
`
`EXHIBIT LIST
`Exhibit No.
`Description
`1001
`U.S. Patent No. 7,739,487 to Mylly et al. (the “’487 Patent”)
`1002
`File History for U.S. Patent No. 7,739,487 to Mylly et al.
`1003
`Declaration of Dr. R. Jacob Baker
`1004
`Curriculum Vitae of Dr. R. Jacob Baker
`1005
`U.S. Patent. No. 6,279,114 to Toombs et al. (“Toombs”)
`1006
`U.S. Patent. No. 7,058,779 to McClain
`1007
`U.S. Patent No. 7,012,845 to Kozakai et al. (“Kozakai”)
`1008
`U.S. Patent No. 7,188,265 to Kurakata et al. (“Kurakata”)
`Information Disclosure Statement (“Toombs IDS”) and
`MultiMediaCard System Specification Version 1.4 (“MMC
`1009
`1.4”), File History of U.S. Patent No. 6,279,114 to Toombs
`et al. (“Toombs File History”)
`1010
`U.S. Patent No. 7,234,049 to Choi et al. (“Choi”)
`1011
`U.S. Patent No. 5,535,357 to Moran et al. (“Moran”)
`1012
`OneNAND Specification (“OneNAND”)
`1013
`M-Systems DiskOnChip G3 Data Sheet (“MDOC”)
`1014
`U.S. Patent No. 5,694,600 to Khenson et al. (“Khenson”)
`1015
`U.S. Patent No. 7,555,568 to Huang
`v
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`U.S. Patent No. 7,739,487
`Petition for Inter Partes Review
`
`Exhibit No.
`Description
`1016
`U.S. Patent No. 7,082,525 to Hutton et al. (“Hutton”)
`U.S. Patent Publication No. 2004/0266480 to Hjelt et al.
`1017
`(“Hjelt”)
`1018
`U.S. Patent No. 7,049,652 to Mokhlesi et al. (“Mokhlesi”)
`1019
`U.S. Patent No. 7,136,994 to Zimmer et al. (“Zimmer”)
`1020
`U.S. Patent No. 7,136,951 to Deng et al. (“Deng”)
`1021
`U.S. Patent No. 7,631,245 to Lasser
`1022
`U.S. Patent No. 6,377,511 to Okuda et al. (“Okuda”)
`1023
`U.S. Patent No. 5,689,459 to Chang et al. (“Chang”)
`Third Joint Claim Construction and Prehearing Statement
`1024
`(N.D. Cal. Patent L.R. 4-3), filed in the related matter on
`Nov. 16, 2018
`Microsoft Computer Dictionary at 94, 150, 159, 310, 404,
`1025
`480, 498, 515 (5th ed. 2002)
`1026
`U.S. Patent No. 6,842,818 to Okamoto et al. (“Okamoto”)
`Comprehensive Dictionary of Electrical Engineering (Phillip
`1027
`A. Lapalante et al., 1st ed. 1999)
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`U.S. Patent No. 7,739,487
`Petition for Inter Partes Review
`
`I.
`INTRODUCTION AND STATEMENT OF RELIEF REQUESTED
`(37 C.F.R. §42.22(a))
`Kingston Technology Company, Inc. (“Petitioner” or “Kingston”) hereby
`petitions to institute an inter partes review of Claims 6, 7, 13, 20, 21, 26, 42, and
`52 (the “Challenged Claims”) of U.S. Patent No. 7,739,487 (the “’487 Patent”) to
`Mylly (Ex. 1001), and cancel these claims as unpatentable. The prior art presented
`in this Petition—U.S. Patent. No. 6,279,114 (Ex. 1005, “Toombs”), U.S. Patent.
`No. 7,058,779 (Ex. 1006, “McClain”), U.S. Patent No. 7,012,845 (Ex. 1007,
`“Kozakai”), and U.S. Patent No. 7,188,265 (Ex. 1008, “Kurakata”) —were not
`considered during prosecution of the ’487 Patent.
`As discussed in detail below, Toombs and McClain render obvious Claims
`6, 7, 20, and 21 under 35 U.S.C. §103; Toombs, McClain, and Kozakai render
`obvious Claims 6, 7, 20, and 21 under 35 U.S.C. §103; and Toombs, McClain, and
`Kurakata render obvious Claims 13, 26, 42, and 52 under 35 U.S.C. §103. Thus,
`there is a reasonable likelihood that Petitioner will prevail with respect to at least
`one challenged claim, and Petitioner respectfully requests that the Board institute a
`trial for inter partes review and cancel the Challenged Claims as unpatentable.
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`U.S. Patent No. 7,739,487
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`II. MANDATORY NOTICES
`A. Real Party-In-Interest (37 C.F.R. §42.8(b)(1))
`Petitioner Kingston Technology Company, Inc., is a real party-in-interest.
`Petitioner’s parent company, Kingston Technology Corporation (“Kingston
`Holding”), is a holding company without any employees or operations. However,
`because Kingston Holding is the sole owner of Petitioner and shares some
`directors, Petitioner identifies Kingston Holding as an additional real party-in-
`interest. B.
`Identification of Related Matters (37 C.F.R. §42.8(b)(2))
`Patent Owner Memory Technologies, LLC (“MTL”) has asserted Claims 6,
`7, 13, 20, 21, 26, 42, and 52 of the ’487 Patent, as well as claims from U.S. Patent
`Nos. RE45,486 (the “RE ’486 Patent”), RE45,542 (the “RE ’542 Patent”),
`7,565,469 (the “’469 Patent”), 7,827,370 (the “’370 Patent”), 8,307,180 (the “’180
`Patent”), 9,063,850 (the “’850 Patent”), and 9,367,486 (the “’486 Patent”) against
`Kingston in a co-pending litigation, Memory Technologies, LLC v. Kingston
`Technology Co., Inc., 8:18-cv-00171 (C.D. Cal.). MTL’s original Complaint was
`filed on January 31, 2018, and served, at the earliest, on February 1, 2018.
`In addition to this Petition, Kingston will be filing petitions for inter partes
`review of the other seven patents that MTL has asserted against it.
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`U.S. Patent No. 7,739,487
`Petition for Inter Partes Review
`
`C. Counsel and Service Information (37 C.F.R. §§42.8(b)(3) & (b)(4))
`Petitioner designates the following Lead and Backup Counsel. Concurrently
`filed with this Petition is a Power of Attorney for appointing the following Lead
`and Backup Counsel, per 37 C.F.R. §42.10(b). Service via hand-delivery may be
`made at the postal mailing addresses below. Petitioner consents to electronic
`service by e-mail at the following address: kingston-487ipr@pillsburylaw.com.
`Lead Counsel
`Back-Up Counsel
`Robert C.F. Pérez
`Christopher Kao, Kingston’s counsel in
`(Reg. No. 39,328)
`the co-pending litigation
` PILLSBURY WINTHROP SHAW
`(Pro hac vice motion to be filed)
`Brock S. Weber, Kingston’s counsel in
`PITTMAN LLP
`the co-pending litigation
`1650 Tysons Boulevard, 14th Floor
`(Pro hac vice motion to be filed)
`McLean, VA 22101
` PILLSBURY WINTHROP SHAW
`Telephone: 703.770.7900
`Facsimile: 703.770.7901
`PITTMAN LLP
`Four Embarcadero Center, 22nd Floor
`San Francisco, CA 94111
`Telephone: 415.983.1000
`Facsimile: 415.983.1200
`
`F.
`Payment of fees (37 C.F.R. §42.103)
`Petitioner authorizes the Patent and Trademark Office to charge Deposit
`Account No. 033975 for the petition fee and for any other required fees.
`III. REQUIREMENTS FOR INTER PARTES REVIEW
`A.
`Identification of Challenge
`Pursuant to 37 C.F.R. §42.104(b), Petitioner shows the following grounds:
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`U.S. Patent No. 7,739,487
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` Claims 6, 7, 20, and 21 are rendered obvious by Toombs (Ex. 1005)
`and McClain (Ex. 1006) under 35 U.S.C. §103;
` Claims 6, 7, 20, and 21 are rendered obvious by Toombs (Ex. 1005),
`McClain (Ex. 1006), and Kozakai (Ex. 1007) under 35 U.S.C. §103;
` Claims 13, 26, 42, and 52 are rendered obvious by Toombs
`(Ex. 1005), McClain (Ex. 1006), and Kurakata (Ex. 1008) under 35
`U.S.C. §103.
`The ’487 Patent was filed on January 17, 2006 and does not claim priority to
`any foreign or U.S. patent application.
`Toombs was filed in the United States on November 4, 1998 and issued on
`August 21, 2001. Thus, Toombs is prior art under at least 35 U.S.C. §§102(a), (b),
`and (e). McClain was filed in the United States on March 5, 2002 and issued on
`June 6, 2006. Thus, McClain is prior art under at least 35 U.S.C. §102 (e).
`Kozakai has an earliest filing date in the United States of September 23,
`2003, published on June 30, 2005, and issued on March 14, 2006. Thus, Kozakai
`is prior art under at least 35 U.S.C. §§102(a) and (e).
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`Kurakata was filed in the United States on November 20, 2003, published on
`June 17, 2004, and issued on March 6, 2007. Thus, Kurakata is prior art under at
`least 35 U.S.C. §§102(a), (b), and (e).
`The Declaration of Jake Baker, Ph.D., filed herewith (Ex. 1003), supports
`the challenge in this Petition that the Challenged Claims of the ’487 Patent are
`invalid.
`IV. BACKGROUND OF THE TECHNOLOGY
`The ’487 Patent is directed to booting a host device from a peripheral
`device. Ex. 1001, Abstract; Ex. 1003, ¶83. This technology was well-developed
`by the time the ’487 Patent was filed in January 2006. Below is an overview of the
`state of the art prior to the filing date of the ’487 Patent.
`A. MMC Cards
`The MultiMediaCard System Specification Version 1.4 (“MMC 1.4”)
`defines specifications for MMC cards and the communications between MMC
`cards and their hosts. See generally Ex. 1009. MMC cards, like SD cards that
`followed them, are removable memory cards that can be used with computers,
`phones, and other devices. Ex. 1003, ¶74.
`MMC 1.4 discloses the power-up process to turn on an MMC card and
`initialize it for use. Ex. 1009, Fig. 39 (shown below).
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`The power-up procedure includes a power-up time to ramp the supply
`voltage to the minimum value (i.e., VDD min) and a supply ramp up time to ramp
`the supply voltage to the bus master supply voltage level. Id. After the power-up
`time, “the host starts the clock and sends the initializing sequence on the CMD
`line.” Id., 64. The initialization sequence can be a “contiguous stream of logical
`‘1’s” and the sequence length is the maximum of “1msec, 74 clocks or the supply-
`ramp-up-time.” Id., 64-65. After the initialization sequence, the host or bus
`master transmits CMD1, which “is a special synchronization command used to
`negotiate the operation voltage range and to poll the cards until they are out of their
`power-up sequence.” Id., 64. Thus, the power-up procedure includes the power up
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`time, supply ramp up time, and synchronization time, as illustrated above in Figure
`39. Ex. 1003, ¶74.
`In addition to the power-up procedure, MMC 1.4 also discloses the
`termination of the command and data lines.
`
`Ex. 1009, 67 (specifying bus signal line load). MMC 1.4 discloses resistors with a
`range of pull-up resistance for the command and data lines “to prevent bus
`floating.” Id. The importance of the pull-up resistors is described in the context of
`the various timing diagrams disclosed in MMC 1.4, where the command and data
`terminals are pulled HIGH by the pull-up resistors when either terminal is not
`actively driven to a value. See id., 48, 62 (describing high impedance (HIGH-Z)
`value); see also Ex. 1003, ¶75.
`MMC 1.4 was included in an Information Disclosure Statement filed on
`November 4, 1998 during prosecution of Toombs (“Ex. 1005”). Ex. 1009, 1, 2.
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`Toombs issued on August 21, 2001. Ex. 1005. Accordingly, MMC 1.4 was
`publicly available at least as of August 21, 2001.
`B.
`Booting from Flash Memory Devices
`The advantages of non-volatile flash memory were well-known at the time
`of the ’487 Patent. Ex. 1003, ¶77; see Ex. 1010, 1:33-38 (explaining that NAND
`flash memory is “easy to realize, has a large capacity, and is cost- effective,” as
`well as “easy to fabricate and has a good integrity”). Two other types of boot
`devices, magnetic hard disks and floppy disks, were known to be “large and
`somewhat susceptible to mechanical failure.” Ex. 1011, 1:38-40. In contrast, flash
`memory devices are “smaller, more rugged and consume less power.” Id., 1:48-50.
`Because of its advantages (i.e., “fast access, low power consumption, high
`reliability, and relatively low cost”), flash memory could be used to replace hard
`disk drives. See id., 1:55-58, 1:67-2:12. Accordingly, flash memory was used to
`boot computing devices. See Ex. 1011, 2:14-18 (replacing “the functionality of the
`BIOS, an operating system and a hard disk” with flash memory).
`One example of a bootable flash memory was Samsung’s OneNAND flash
`memory, which enabled boot from system power-up. Ex. 1012, 58, 103; see also
`id., 5 (“Samsung offers a variety of Flash solutions including NAND Flash,
`OneNANDTM and NOR Flash. Samsung offers Flash products both component and
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`a variety of card formats including RS-MMC, MMC, CompactFlash, and
`SmartMedia.”). Booting from OneNAND involved copying boot code from the
`flash memory into a buffer in response to power on reset and then reading the boot
`code from the buffer. Id., 103; see Ex. 1010, 5:59-65.
`Another example of a bootable flash memory was M-Systems’ DiskOnChip
`(“DOC” or “MDOC”), which enabled boot in response to a signal received on a
`pin of the flash memory. Ex. 1013, 10, 36. MDOC included a boot block with an
`eXecute In Place (XIP) capability to enable the flash memory to be the only non-
`volatile memory in a system. Id., 10. As shown in Figure 33, below, a host would
`power up the flash memory (highlighted in red) and assert reset by holding the
`RSTIN# pin in a low voltage state at power up to boot from the flash memory
`device (highlighted in blue):
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`Power Up
`retrieving
`boot data
`Id., 90-91, Fig. 33 (annotated), Table 22. Then, the host would enable boot mode
`by de-asserting reset (i.e., RSTIN# transitions from low to high). Id. After a
`delay, the flash memory device would download boot data from the flash memory
`to the boot block. Id. The host, in turn, would read the data from the boot block to
`continue the boot process (highlighted in orange). Id.
`Thus, it was known at the time of the ’487 Patent that a host could provide a
`boot signal to a flash memory by holding a pin of the memory in a low voltage
`state for a predefined period of time. Ex. 1003, ¶79.
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`initialization
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`U.S. Patent No. 7,739,487
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`C. Booting from Removable Flash Memory Devices
`At the time of the ’487 Patent, it was also well-known that a computer could
`boot from a removable device. See, e.g., Ex. 1014, 1:6-10. In addition to
`computers that could boot from removable devices, it was further known at the
`time of the ’487 Patent that a computer could boot from a removable flash memory
`device. See, e.g., Ex. 1015, 16:11-21; see infra, Section X (Combination of
`Toombs and McClain).
`For example, NAND flash memory devices, such as MMC cards, were used
`to reduce the time to boot computing devices, such as cellular phones. Ex. 1016,
`3:49-51, 4:44-62 (describing MMC and SD cards as exemplary devices to be used
`for boot without first copying the boot data to RAM); see also Ex. 1003, ¶111. In
`addition, flash memory has several advantages over other dedicated storage
`devices, such as read-only memory (ROM). Id., 3:34-48.
`As another example, Universal Serial Bus (USB) drives containing flash
`memory could be plugged into a computer, which could detect the presence of the
`drive and then boot via the USB interface to the drive. See Ex. 1015, 16:11-21.
`Thus, it was known at the time of the ’487 Patent that a computer could boot from
`a removable flash memory device. Ex. 1003, ¶81.
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`U.S. Patent No. 7,739,487
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`As described in the prior art, and in the background of the ’487 Patent, an
`MMC bus could be used to communicate with a flash memory device. Ex. 1017,
`¶0060, Fig. 11; see also Ex. 1001, 1:20-22 (“The invention introduces a booting
`mechanism also to a formerly known serial protocol memory card interface (MMC
`IF).”). “MMC cards involve[] the transfer of data using a minimum number of
`signals.” Ex. 1017, ¶0060. For example, Figure 11, below, shows an MMC
`interface for an MMC flash memory device:
`
`Ex. 1017, Fig. 11 (emphasis added).
`As shown above, MMC interface 1110 includes command, data, and clock
`lines for communication between the master (i.e., host device) and the MMC card.
`Id., Table 1, Fig. 11 (depicting an MMC interface with MMC_A_CMD,
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`MMC_A_DAT, and MMC_CLK lines). Both the command and data lines are
`bidirectional channels that operate in push-pull mode, “where, for example, a
`complementary pair of transistors is used to actively drive the interface level to a
`logic high or logic low.” Id., ¶0060. Bidirectional communication for the
`command line, for example, enables its use for both “card initialization and data
`transfer commands.” Id.
`Thus, it was known at the time of the ’487 Patent that an MMC interface
`with only three lines (i.e., command, data, and clock) could be used for
`communication to a flash memory device. Ex. 1003, ¶80.
`V. OVERVIEW OF THE ’487 PATENT
`The ’487 Patent relates to booting a host from a peripheral device, for
`example, a memory device. Ex. 1001, Abstract and 1:9-24. The memory device in
`the ’487 Patent is a Secure Digital (SD) card or Multi Media Card (MMC). Id.
`The memory device and the host of the ’487 Patent are connected via an MMC/SD
`interface, which includes power terminals, a data bus with data bus terminals, a
`clock line with a clock terminal, and a command line with a command terminal.
`Id., 2:28-40, Fig. 5 (illustrated below). As illustrated in Figure 5 below, the host
`includes a CPU and a controller and the memory device includes a controller and
`plurality of memory. Id., Fig. 5.
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`The background of the ’487 Patent acknowledges that “[b]oot definitions for
`existing mass memory components having a different electrical interface are
`already known.” Id., 1:31-34. Each of these memory devices used “some signal
`state (e.g. separate pin reserved for booting) during certain stage of power up to
`indicate to the memory component that it should fetch the first sector (typically
`512 B) of data to the IO buffers.” Id., 1:34-38, 1:52-56.
`The ’487 Patent further explains that for MMC/SD devices, which do not
`have a separate pin for booting, fetching of first (sector) data during boot up of a
`host device required (i) initializing the card, (ii) reading/writing the registers, and
`(iii) performing a normal read access to a known address. Id., 2:1-11. The ’487
`Patent purports to achieve broader usability of MMC/SD devices without the use
`of an additional pin to signal boot by holding the CMD pin low for a duration or by
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`sending a command with an argument for boot using the CMD pin. Id., 2:16-25,
`3:3-10, 3:63-4:30. Accordingly, the ’487 Patent explains that the capabilities of
`existing MMC and SD cards can be extended without changing too many
`properties of the memory cards (i.e., without addition an additional pin to the
`MMC/SD interface). Id., 2:22-25, 17:23-26.
`Figures 1 and 3 of the ’487 Patent, below, illustrate the different booting
`mechanisms (i.e., by holding the CMD pin low for a duration and by sending a
`command with an argument for boot using the CMD pin). Id., Figs. 1, 3.
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`As illustrated in Figure 1, above, a low signal is received at the command
`terminal during power up and then boot data is retrieved and sent via the data bus
`starting with a start bit. Id., 3:3-10, 3:63-4:30, Fig. 1. Further, as illustrated in
`Figure 3 above, an argument for a boot request is received during an initialization
`procedure, a clock signal is received at a clock terminal, and then boot data is
`retrieved and sent via the data bus starting with a start bit. Id. The host device part
`of the flowchart is depicted at the left side of Figures 1 and 3 while the part of the
`flowchart depicted on the right side of Figures 1 and 3 refers to actions or
`processes performed by or in the memory device. Id., 14:23-27.
`VI. SUMMARY OF THE PROSECUTION HISTORY
`The ’487 Patent issued from U.S. Patent Application No. 11/333,799 (the
`’799 Application) filed on January 17, 2006. Ex. 1001.
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`The USPTO issued a Non-Final Office Action dated November 14, 2008 in
`which some of the originally-presented claims were rejected under 35 U.S.C. §101
`and the other claims were indicated as being allowed. Ex. 1002, 89-92. A
`response with claims amendments was filed in response to the Office Action of
`November 14, 2008, which resulted in another Non-Final Office Action being
`issued by the USPTO. Id., 99-113, 119-122. In this Office Action, some of the
`claims were rejected under 35 U.S.C. §102 as being anticipated by Gillet (U.S.
`2005/0132116) and other claims were indicated as being objected to as being
`dependent upon a rejected base claim, but would be allowable if rewritten in
`independent form. Id., 119-122.
`On July 14, 2009, the Applicant filed a response arguing that the Office
`Action dated April 15, 2009 was improper. Id., 128-146. The Applicant asserted
`that Gillet does not disclose “setting the command terminal of said MMC/SD
`interface during power-up to low.” Id., 142. The Applicant acknowledged that
`Gillet discloses “setting one of the data bus lines (contacts 1, 8-13 / DAT1-DAT7)
`to a low state at a later, already powered up, state by the MMC card.” Id. The
`Applicant explained that “Gillet relies upon a different device using a different line
`during a different period of time than the claimed invention.” Id., 144.
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`A Notice of Allowance eventually issued on March 23, 2010 and the ’799
`Application issued as the ’487 Patent. Id., 293-296; Ex 1001.
`On July 23, 2010, a request for a certificate of correction was filed by the
`Applicant to correct the title to recite “an MMC/SD Device Method a Host Device
`May Be Booted From.” Ex. 1002, 313-314. The Applicant further sent a letter on
`August 31, 2010 providing a superseding request for a certificate of correction to
`further correct the title at Column 1, line 5 and on the Title Page, Item (54). Id.,
`318-319. On September 28, 2010, the superseding Certificate of Correction was
`i