Trials@uspto.gov
`571-272-7822
`
`Paper 11
`Entered: January 7, 2020
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INTEL CORPORATION,
`Petitioner,
`v.
`VLSI TECHNOLGY LLC,
`Patent Owner.
`
`IPR2019-01196
`Patent 7,246,027 B2
`
`
`
`
`
`
`
`
`
`Before BART A. GERSTENBLITH, MINN CHUNG, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`McGRAW, Administrative Patent Judge.
`
`DECISION
`Denying Institution of Inter Partes Review
`35 U.S.C. § 314, 37 C.F.R. § 42.4
`
`
`
`
`
`
`
`
`571-272-7822
`
`Paper 11
`Entered: January 7, 2020
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`INTEL CORPORATION,
`Petitioner,
`v.
`VLSI TECHNOLGY LLC,
`Patent Owner.
`
`IPR2019-01196
`Patent 7,246,027 B2
`
`
`
`
`
`
`
`
`
`Before BART A. GERSTENBLITH, MINN CHUNG, and
`KIMBERLY McGRAW, Administrative Patent Judges.
`McGRAW, Administrative Patent Judge.
`
`DECISION
`Denying Institution of Inter Partes Review
`35 U.S.C. § 314, 37 C.F.R. § 42.4
`
`
`
`
`
`
`
`
`
`IPR2019-01196
`Patent 7,246,027 B2
`
`INTRODUCTION
`I.
`Petitioner, Intel Corporation, filed a Petition (Paper 3, “Pet.”) for inter
`partes review of claims 1–3, 5–12, and 18–20 of U.S. Patent No.
`7,246,027 B2 (Ex. 1001, “the ’027 patent”), supported by the Declaration of
`David Harris (Ex. 1005, “Harris Declaration”). Patent Owner, VLSI
`Technology LLC, filed a Preliminary Response (Paper 7, “Prelim. Resp.”)
`supported by the Declaration of Engin Ipek, Ph.D. (Ex. 2001, “Ipek
`Declaration”). Thereafter, Petitioner filed an authorized Reply (Paper 9
`“Pet. Reply”) to which Patent Owner filed an authorized Sur-reply
`(Paper 10, “PO Sur-reply”). Applying the standard set forth in 35 U.S.C.
`§ 314(a), which authorizes institution of an inter partes review when “the
`information presented in the petition . . . and any response . . . shows that
`there is a reasonable likelihood that the petitioner would prevail with respect
`to at least 1 of the claims challenged in the petition,” we deny institution of
`an inter partes review of the challenged claims of the ’027 patent.
`A. Real Parties-in-Interest
`Petitioner identifies Intel Corporation as the real party-in-interest for
`Petitioner. Pet. 1. Patent Owner identifies VLSI Technology LLC and CF
`VLSI Holding LLC as the real parties-in-interest for Patent Owner. Paper 6,
`2.
`
`B. Related Matters
`The parties represent that the ’027 patent is at issue in VLSI
`Technology LLC v. Intel Corp., Case No. 18-966 (D. Del.). Pet. 1; Prelim.
`Resp. 9.
`
`2
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`IPR2019-01196
`Patent 7,246,027 B2
`C. The ’027 Patent
`The ’027 patent, titled “Power Optimization of a Mixed-Signal
`System on an Integrated Circuit,” was filed on March 11, 2005. Ex. 1001,
`Title, code [22]. The ’027 patent issued on July 17, 2007. Id. at code [45].
`The ’027 patent states that one difficulty of optimizing power
`consumption of an integrated circuit (“IC”) having mixed signals (i.e.,
`analog and digital) is that analog and digital components operate under
`different parameters for their desired functional results. See id. at 2:16–18.
`For example, “lower operational temperatures raise the threshold voltage
`level for analog components, affecting signal performance, while favorable
`for digital component operation.” Id. at 2:22–25. Conversely, “higher
`operational temperatures lower the threshold voltage level for analog
`components, while slowing digital gate response for digital components.”
`Id. at 2:25–28. Accordingly, power consumption considerations for each
`type of component (i.e., analog and digital components) would differ. Id. at
`2:28–30. The ’027 patent states that although there were design techniques
`to reduce power consumption generally, these techniques were designed
`assuming the worst-case operation of an integrated circuit. Id. at 2:9–11. As
`a result, these techniques resulted in “integrated circuits [that would]
`consume more power than needed because the power reducing techniques
`were under a worst-case assumption and not individually optimized on a
`chip-by-chip basis. Id. at 2:11–15.
`The ’027 patent provides a solution “for conserving power of a
`system-on-a chip having analog circuitry.” Id. at 2:40–41. With the
`methods described in the ’027 patent, “power consumption is optimized on
`an IC-by-IC basis, as well as over time.” Id. at 3:1–2.
`
`3
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`IPR2019-01196
`Patent 7,246,027 B2
`Figure 11, reproduced below is a block diagram of a power
`conservation circuit in accordance with the invention of the ’027 patent. Id.
`at 3:36–40.
`
`
`
`Figure 11, above, depicts power conserving circuit 250 that provides
`“adjust supply voltage signal 252” for a shared voltage source supplying
`power to the analog and the digital circuitry of battery-optimized system on
`chip 62. Id. at 14:26–30. Power conserving circuit 250 has “digital circuitry
`power optimization-power conserving circuit 92” and “analog circuitry
`power optimization-analog power conservation circuit 209.” See id. at
`14:31–35.
`Analog power conserving circuit 209 includes “a portion of an IC,”
`“process sense module 208,” “operational temperature sensor 210,” and
`look-up table 214. Id. at 12:17–20. In operation, process sense module 208
`
`4
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`IPR2019-01196
`Patent 7,246,027 B2
`senses the analog variation parameter of the IC portion and provides analog
`parameter signal 215. Id. at 12:23–25. A “suitable value used for assessing
`the analog variation parameter is the threshold voltage Vt of the IC.” Id. at
`10:63–65. The analog variation parameter can be assessed by measuring the
`gate voltage of a transistor at a point where a specific small drain current
`flows. Id. at 11:2–5. Operational temperature sensor 210 senses the
`operational temperature of an IC 100 portion and provides temperature
`signal 216. Id. at 12:25–27. Look-up table 214 receives analog variations
`parameter signal 215 and temperature signal 216, and using this information,
`generates analog voltage level (AVdd) adjust signal 218. Id. at 12:50–53,
`15:5–6. Digital power conserving circuit 92 provides an adjust signal for a
`supply voltage on a chip-by-chip basis such that the speed of a transistor is
`maintained at a rate just above the critical speed. Id. at 10:36–66.
`Comparator 260 receives inputs from analog power conserving
`circuit 209 (i.e., analog voltage level (AVdd) adjust signal 218) and from
`digital power conserving circuit (i.e., adjust supply voltage 217). Id. at
`14:35–36. Based on those inputs, comparator 260 selects adjust supply
`signal 252. Id. at 14:39–50.
`D. Challenged Claims
`Of the challenged claims, claims 1, 8, and 18 are independent.
`Claim 1 is representative and is reproduced below.
`1. A method for power supply optimization of an integrated
`circuit, comprising:
`determining an analog variation parameter representative of an
`integrated circuit fabrication process variance of the
`integrated circuit;
`determining an operational temperature associated with the
`analog variation parameter, and
`
`5
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`IPR2019-01196
`Patent 7,246,027 B2
`determining an adjustment signal for a power supply voltage
`level of the integrated circuit based on the analog variation
`parameter with respect to the operational temperature; and
`adjusting a regulation signal of a DC-to-DC converter based on
`the adjustment signal to optimize power consumption of the
`integrated circuit.
`Ex. 1001, 16:57–17:3.
`E. Prior Art and Asserted Grounds
`Petitioner challenges claims 1–3, 5–12, and 18–20 on the following
`grounds:
`Claims Challenged
`1, 2, 8, 9, 18, 19
`3, 5–7, 10–12, 20
`
`Petitioner relies on, inter alia, the Harris Declaration in support of its
`unpatentability contentions. See Ex. 1005.
`II. ANALYSIS
`A. Level of Ordinary Skill in the Art
`In determining whether an invention would have been obvious at the
`time it was made, we consider the level of ordinary skill in the pertinent art
`at the time of the invention. Graham v. John Deere Co, 383 U.S. 1, 17
`(1966). Petitioner contends a person of ordinary skill in the art at the time of
`the alleged invention (“POSITA”) would have had a Master’s degree in
`
`References
`Starr,1 Bilak2
`Starr, Bilak, Kang3
`
`35 U.S.C. §
`103
`103
`
`
`1 US 6,933,869 B1, filed March 17, 2004, issued August 23, 2005 (Ex. 1002,
`“Starr”).
`2 US 7,577,859 B2, filed February 20, 2004, issued August 18, 2009
`(Ex. 1003, “Bilak”).
`3 US 7,583,555 B2, filed March 30, 2004, issued September 1, 2009
`(Ex. 1004, “Kang”).
`
`6
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`IPR2019-01196
`Patent 7,246,027 B2
`Electrical Engineering or Computer Engineering, plus at least two years of
`experience in IC design, or alternatively a Bachelor’s degree in one of those
`fields plus at least four years of experience in IC design. Pet. 16 (citing
`Ex. 1005 ¶ 48). Patent Owner does not dispute Petitioner’s articulation of a
`level of skill for a POSITA. See Prelim. Resp. 23.
`Based on our review of the ’027 patent and the types of problems and
`solutions described in the ’027 patent and cited prior art, we adopt and apply
`Petitioner’s definition of a person of ordinary skill in the art at the time of
`the claimed invention.
`B. Claim Construction
`For petitions filed on or after November 13, 2018, a claim shall be
`construed using the same claim construction standard that would be used to
`construe the claim in a civil action under 35 U.S.C. § 282(b), including
`construing the claim in accordance with the ordinary and customary
`meaning of such claim as understood by one of ordinary skill in the art and
`the prosecution history pertaining to the patent. 37 C.F.R. § 42.100(b)
`(2018). Petitioner filed its Petition after November 13, 2018. Paper 4, 1.
`Thus, we apply the claim construction standard as set forth in Phillips v.
`AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc).
`The parties set forth proposed claim constructions for three claim
`terms that are also disputed in the concurrent district court litigation.
`See Pet. 12–15 (citing Ex. 1010 [Joint Chart, Ex. A] at 6–8); Prelim.
`Resp. 23–32. These terms are “determining/determine an analog variation
`parameter,” “an operational temperature,” and “determining/determine a
`digital variation parameter.” See Pet. 12; Prelim. Resp. 23, 30, 32.
`We determine that an explicit claim construction is not required for
`purposes of this Decision. See Nidec Motor Corp. v. Zhongshan Broad
`
`7
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`IPR2019-01196
`Patent 7,246,027 B2
`Ocean Motor Co., 868 F.3d 1013, 1017 (Fed. Cir. 2017) (stating that only
`terms that are in controversy need to be construed, and then only to the
`extent necessary to resolve the controversy).
`C. Principles of Law
`A claim is unpatentable under 35 U.S.C. § 103(a) if the differences
`between the claimed subject matter and the prior art are such that the subject
`matter, as a whole, would have been obvious at the time the invention was
`made to a person having ordinary skill in the art to which said subject matter
`pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). The
`question of obviousness is resolved on the basis of underlying factual
`determinations, including: (1) the scope and content of the prior art; (2) any
`differences between the claimed subject matter and the prior art; (3) the level
`of skill in the art; and (4) where in evidence, so-called secondary
`considerations.4 Graham, 383 U.S. at 17–18.
`D. Asserted Unpatentability of Independent Claims 1, 8, and 18 over
`Starr and Bilak
`Petitioner contends that independent claims 1, 8, and 18 are
`unpatentable under 35 U.S.C. § 103 over the combination of Starr and Bilak.
`See Pet. 25–57. To support its contention, Petitioner provides explanations
`as to how the prior art allegedly teaches each claim limitation of the
`challenged independent claims. Id. Petitioner also relies upon the Harris
`Declaration. Ex. 1005. For the following reasons, we do not institute a
`review based on this challenge.
`
`
`4 Patent Owner does not present arguments or evidence of such secondary
`considerations in its Preliminary Response. Therefore, secondary
`considerations do not constitute part of our analysis.
`
`8
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`IPR2019-01196
`Patent 7,246,027 B2
`Claims 1 and 18 recite “determining an analog variation parameter
`representative of an integrated circuit fabrication process variance of the
`integrated circuit.” Ex. 1001, 16:59–61, 20:1–3 (emphasis added). Claim 8
`recites a similar limitation. See id. at 17:52–54 (“determine an analog
`variation parameter representative of an integrated circuit fabrication
`process variance of the integrated circuit” (emphasis added)).
`A dispositive issue is whether Petitioner has sufficiently established
`Starr discloses determining “an analog variation parameter” as recited in
`each of the challenged independent claims.
`Petitioner relies on Starr for this claim element, stating:
`As required by both Petitioner’s and Patent Owner’s proposed
`constructions, Starr similarly teaches monitoring the threshold
`voltage of an analog portion of an IC. Ex. 1002, Fig. 10
`(showing “threshold voltage monitoring circuit 86”), 4:63–66
`(circuit B is monitored by monitoring and compensation
`circuitry 34 and can contain “analog circuits”), 1:55–2:7, 2:11–
`14, 4:36–42, 5:47–55, 7:50–63, 8:16–21, 9:61–10:10, 10:35–42.
`Pet. 31 (emphasis added).
`Petitioner also addresses the differences in the parties’ claim
`construction, stating:
`Further, Starr teaches that the monitored threshold voltage varies
`during operation, as
`required by Petitioner’s proposed
`construction. [Ex. 1002], 7:51–52 (“During operation of the
`integrated circuit 32, monitoring and compensation circuitry 34
`measures changes . . . in transistor threshold voltage.”). A
`[person of ordinary skill in the art] would have also understood
`that Starr’s threshold voltage may vary on an IC-by-IC basis, as
`required by Patent Owner’s proposed construction, because it
`was well known in the prior art that manufacturing variances can
`“occur from lot to lot and from wafer to wafer, but also within
`
`9
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`IPR2019-01196
`Patent 7,246,027 B2
`wafers and even within dice.” Ex. 1007, 1:15–22; Ex. 1005,
`¶¶ 54, 88.
`Pet. 31–32 (emphases altered).
`Based on the current record, we are not persuaded that Petitioner has
`shown sufficiently that the cited passages of Starr disclose “monitoring the
`threshold voltage of the analog portion of an IC” as asserted by Petitioner.
`See id. (stating as “required by both [parties’] proposed constructions, Starr
`similarly teaches monitoring the threshold voltage of an analog portion of an
`IC”). Although Petitioner cites to a number of passages of Starr as
`disclosing the disputed limitation, Petitioner does not sufficiently explain
`how these passages relate to monitoring or determining the threshold voltage
`of the analog portion of the integrated circuit as opposed to monitoring or
`determining the threshold voltage of an integrated circuit that contains
`analog components. We also note that Petitioner does not provide any
`argument or evidence that “determining an analog variation parameter” can
`be determined by monitoring the threshold voltage of a combination of the
`digital and analog portions of the integrated circuit.
`Petitioner asserts circuit 86 of Figure 10 is a “threshold voltage
`monitoring circuit” and that “circuit B [of Figure 4] is monitored by
`monitoring and compensation circuitry 34 and can contain ‘analog circuits.’”
`Pet. 31 (citing Ex. 1002, Fig. 10, 4:63–66). These cited passages, however,
`do not state that Starr’s threshold voltage monitoring circuits monitor
`specifically the analog portion of an integrated circuit. For example,
`Figure 10 identifies a “threshold voltage monitoring circuit” but does not
`state that the circuit monitors the threshold voltage of the analog portion of
`an integrated circuit. Similarly, column 4, lines 63 through 64, states that
`“[o]ther circuits (e.g., circuit B [of Figure 4]) may contain sensitive high-
`
`10
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`IPR2019-01196
`Patent 7,246,027 B2
`performance digital or analog circuits” but does not state that monitoring and
`compensation circuity 34 monitors the analog portion of circuit B; see also
`Ex. 1002, 7:51–52 (stating “monitoring and compensation circuitry 34
`measures changes … in transistor threshold voltage”).
`Petitioner also lists a string of citations to Starr but does not explain
`how these disclosures teach “monitoring the threshold voltage of an analog
`portion of an IC.” Pet. 31 (citing Ex. 1002, 1:55–2:7, 2:11–14, 4:36–42,
`5:47–55, 7:50–63, 8:16–21, 9:61–10:10, 10:35–42). The Harris Declaration
`also cites to these same disclosures of Starr but does not provide any
`explanation as to how these disclosures teach “monitoring the threshold
`voltage of an analog portion of an IC.” Ex. 1005 ¶ 88. Rather, the Harris
`Declaration merely adds the text of the citations as parentheticals. See id.
`Petitioner “has the burden from the onset to show with particularity
`why the patent it challenges is unpatentable.” Harmonic Inc. v. Avid Tech.,
`Inc., 815 F.3d 1356, 1363 (Fed. Cir. 2016); see also SAS Inst., Inc. v. Iancu,
`138 S. Ct. 1348, 1355 (2018) (“in an inter partes review, the petitioner is
`master of its complaint”). Based on our review of the record presented, we
`find that there is insufficient explanation supported by record evidence that
`Starr “teaches monitoring the threshold voltage of an analog portion of an
`IC” as asserted by Petitioner, and therefore Petitioner does not establish a
`reasonable likelihood that Starr teaches determining “an analog variation
`parameter,” as recited in independent claims 1, 8, and 18. For these reasons,
`we determine Petitioner has not demonstrated a reasonable likelihood of
`prevailing on its challenge to independent claims 1, 8, and 18 of the
`’027 patent.
`
`11
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`IPR2019-01196
`Patent 7,246,027 B2
`E. Asserted Unpatentability of Dependent Claims 2, 3, 5–7, 9–12, 19,
`and 20 over Starr and Bilak or over Starr, Bilak, and Kang
`Petitioner contends that dependent claims 2, 9, and 19 would have
`been obvious over Starr and Bilak and that claims 3, 5–7, 10–12, and 20
`would have been obvious over Starr, Bilak, and Kang. Pet. 51–52, 55, 56–
`80. As noted above, we determine that Petitioner has not demonstrated a
`reasonable likelihood of prevailing on its challenge to independent claims 1,
`8, and 18. None of Petitioner’s arguments regarding the dependent claims
`cures the deficiencies regarding the independent claims. Therefore,
`Petitioner has not demonstrated a reasonable likelihood of prevailing on its
`challenge that claims 2, 9, and 19 would have been obvious over Starr and
`Bilak or that claims 3, 5–7, 10–12, and 20 would have been obvious over
`Starr, Bilak, and Kang.
`F. Discretional Denial under 35 U.S.C. § 314(a)
`Because we determine that Petitioner has not demonstrated a
`reasonable likelihood of prevailing with respect to at least one claim of the
`’027 patent challenged in the Petition, we do not address Patent Owner’s
`argument that the Board should exercise its discretion to deny institution
`under 35 U.S.C. § 314(a). See Prelim. Resp. 9–11; PO Sur-reply 1–5.
`III. CONCLUSION
`For the foregoing reasons, we conclude that Petitioner has not
`demonstrated a reasonable likelihood of prevailing with respect to at least
`one claim of the ’027 patent challenged in the Petition. Therefore, we do not
`institute an inter partes review on any of the asserted grounds as to any of
`the challenged claims.
`
`12
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`IPR2019-01196
`Patent 7,246,027 B2
`
`IV. ORDER
`In consideration of the foregoing, it is hereby:
`ORDERED that the Petition is denied and that we do not institute a
`trial on the challenges to the claims of the ’027 patent advanced in the
`Petition.
`
`
`13
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`IPR2019-01196
`Patent 7,246,027 B2
`FOR PETITIONER:
`
`Dominic E. Massa
`Richard Goldenberg
`Daniel Williams
`Yvonne Lee
`WILMER HALE
`dominic.massa@wilmerhale.com
`richard.goldenberg@wilmerhale.com
`daniel.williams@wilmerhale.com
`yvonne.lee@wilmerhale.com
`
`
`FOR PATENT OWNER:
`
`H. Annita Zhong
`Benjamin Hattenback
`IRELL & MANELLA
`hzhong@irell.com
`bhattenbach@irell.com
`
`
`
`14
`
`
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