US007246027B2
`
`(12) United States Patent
`May et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,246,027 B2
`Jul. 17, 2007
`
`(54) POWER OPTIMIZATION OF A
`MIXED-SIGNAL SYSTEM ON AN
`INTEGRATED CIRCUIT
`(75) Inventors: Marcus W. May, Austin, TX (US);
`Matthew D. Felder, Austin, TX (US)
`(73) Assignee: Sigmatel, Inc., Austin, TX (US)
`(*) Notice:
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`(21) Appl. No.: 11/078,150
`(22) Filed:
`Mar. 11, 2005
`O
`O
`(65)
`Prior Publication Data
`US 2006/021792O A1
`Sep. 28, 2006
`p
`(51) Int. Cl.
`(2006.01)
`GOIK L/00
`(52) U.S. Cl. ...................................................... 702/130
`(58) Field of Classification Search
`702/130
`702/117, 121, 124, 60, 64: 377/19, 20. 438/1 4.
`s u. 1 r. s r. 1 is sws Y
`is
`438/17.18
`See application file for complete search history. s
`References Cited
`
`(56)
`
`U.S. PATENT DOCUMENTS
`5,563,928 A * 10/1996 Rostoker et al. .............. 377/20
`* cited by examiner
`
`Primary Examiner John Barlow
`Assistant Examiner—Xiuqin Sun
`(74) Attorney, Agent, or Firm—Garlick Harrison &
`Markison; Kevin L. Smith
`57
`ABSTRACT
`(57)
`
`A method and apparatus for conserving power of a mixed
`signal system-on-a-chip having analog circuitry, involving
`determination of an analog variation parameter that is rep
`resentative of an integrated circuit fabrication process vari
`ance of the integrated circuit, and an operational temperature
`associated with the analog variation parameter. With the
`analog variation parameter and the operational temperature,
`9.
`p
`p
`p
`an adjustment signal is determined for a power Supply level
`of the integrated circuit, such that power consumption of the
`integrated circuit is optimized. Further, in mixed-signal
`integrated circuits with digital and analog circuitry, a digital
`variation parameter is determined, where the adjustment
`signal determination is based on the digital variation param
`eter and the analog Variat1On parameter W1th respect to the
`d h
`log variati on p
`ith resp
`h
`operational temperature. With Such a method and apparatus,
`power consumption is optimized on an IC-by-IC basis such
`that power consumption of each IC is optimized.
`
`21 Claims, 10 Drawing Sheets
`
`external sources 34
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`host computer 36
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`video deCOder 38
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`memory stick 40
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`Wireless
`modern 42
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`camcorder image
`SensOr 44
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`battery-operated
`system on a chip 12
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`DC to DC
`Converter 26
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`battery 14
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`display 18
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`input device 22
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`input signals 54
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`multiple function battery
`operated device 10
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`INTEL 1001
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`

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`U.S. Patent
`
`Jul. 17, 2007
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`Sheet 1 of 10
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`US 7,246,027 B2
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`U.S. Patent
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`Jul. 17, 2007
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`U.S. Patent
`
`Jul. 17, 2007
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`Sheet 8 of 10
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`US 7,246,027 B2
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`302
`determine an Analog
`Variation Parameter
`for device
`
`
`
`
`
`
`
`
`
`304
`
`determine
`Operational
`Temperature
`for integrated circuit
`
`306
`
`determine an AV
`adjust signal based on
`the Analog Variation
`Parameter and
`Operational Temperature
`
`
`
`digital circuit
`component
`present?
`
`O
`
`31 O
`optimize power consumption of
`integrated circuit by adjusting
`Supply voltage V to the Analog
`Variation Parameter via the AV
`adjustment signal
`
`
`
`
`
`
`
`FIG. 12A
`
`-(a)
`
`

`

`U.S. Patent
`
`Jul. 17, 2007
`
`Sheet 9 of 10
`
`US 7,246,027 B2
`
`measure processing speed of at
`least a portion of an integrated
`circuit to produce measured
`processing Speed
`
`Compare the measured
`processing speed with a critical
`processing speed for the at
`least a portion of the integrated
`circuit
`
`
`
`comparison favorable?
`
`maintain Digital Variation
`Parameter supply
`voltage setting
`
`
`
`
`
`
`
`
`
`Digital Variation Parameter is the
`favorable comparison result
`
`determine an adjustment signal as
`a favorable comparison between
`the analog and the digital variation
`parameters
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`optimize power consumption of
`integrated circuit by
`adjusting Supply voltage via the
`adjustment signal
`
`FG. 12B
`
`

`

`U.S. Patent
`
`Jul. 17, 2007
`
`Sheet 10 of 10
`
`US 7,246,027 B2
`
`
`
`)
`
`376
`perform a function by the at
`least a portion of the integrated
`circuit
`
`Count a number of cycles of a
`known clock during the
`performing of function
`
`equate the number of cycles of
`the known clock to the
`processing Speed
`
`FG. 12C
`
`

`

`US 7,246,027 B2
`
`1.
`POWER OPTIMIZATION OFA
`MIXED-SIGNAL SYSTEM ON AN
`INTEGRATED CIRCUIT
`
`TECHNICAL FIELD
`
`This invention relates generally to portable electronic
`equipment and more particularly to a sensing digital and
`analog parameters of an integrated circuit to provide power
`Supply optimization.
`
`10
`
`BACKGROUND
`
`2
`circuit technology is currently the most accepted process,
`which uses Supply Voltages of 1.8 volts. Several years ago,
`however, 0.35 micron and 0.50 micron CMOS integrated
`circuit technologies were the prevalent processes, which
`could use supply voltages of about 3.3 volts. In the near
`future, 0.10 and 0.13 micron CMOS integrated circuit tech
`nology will likely become the technology of choice because
`of lower supply voltages of about 1.0 volts.
`While these design techniques worked to reduce power
`consumption generally, they had been designed assuming
`the worst-case operation of an integrated circuit. As such,
`integrated circuit circuits would be consuming more power
`than needed because the power reducing techniques were
`under a worst-case assumption and not individually opti
`mized on a chip-by-chip basis.
`Generally, digital components and analog components are
`operated under different processes, techniques, or param
`eters for their desired functional results. Because digital
`component operation is based on clock speed, and analog
`component operation is based on bias factors such as thresh
`old Voltage, different operational parameters or conditions
`may be more favorable for one over the other. For example,
`lower operational temperatures raise the threshold Voltage
`level for analog components, affecting signal performance,
`while favorable for digital component operation. Con
`versely, higher operational temperatures lower the threshold
`Voltage level for analog components, while slowing digital
`gate response for digital components. Accordingly, power
`consumption considerations for each type of component
`would differ.
`Therefore, a need exists for an integrated circuit that
`provides multiple functions through mixed-signal operation
`and architectures for handheld devices with appropriate
`optimized power-consumption and with a minimal require
`ment of external components.
`
`SUMMARY
`
`Provided is a method and apparatus for conserving power
`of a system-on-a-chip having analog circuitry. An aspect is
`a method and apparatus for increasing the power Supply
`efficiency of an integrated circuit, by determining an analog
`variation parameter that is representative of an integrated
`circuit fabrication process variance of the integrated circuit.
`An operational temperature is determined, where the opera
`tional temperature is associated with the analog variation
`parameter. With the analog variation parameter and the
`operational temperature, an adjustment signal is determined
`for a power Supply level of the integrated circuit, Such that
`power consumption of the integrated circuit is optimized.
`A further aspect involves determining a digital variation
`parameter, and determining the adjustment signal based on
`the digital variation parameter and the analog variation
`parameter with respect to the operational temperature. The
`digital variation parameter is determined by using a speed
`sensing technique, which begins by measuring the process
`ing speed of at least a portion of an integrated circuit (“IC)
`to produce measured processing speed. The portion of the IC
`may be a test circuit, a critical path of the IC, and/or a replica
`of the critical path of the IC. The processing continues by
`comparing the measured processing speed with a critical
`processing speed for the at least a portion of the integrated
`circuit. The processing then continues by adjusting Supply
`Voltage to the integrated circuit to reduce power consump
`tion of the integrated circuit when the measured processing
`speed compares favorably to the critical processing speed.
`
`15
`
`As is known, integrated circuits are used in a wide variety
`of electronic equipment, including portable, or handheld,
`devices. Such handheld devices include personal digital
`assistants (PDA), CD players, MP3 players, DVD players,
`AM/FM radio, a pager, cellular telephones, computer
`memory extension (commonly referred to as a thumb drive),
`etc. These handheld devices include one or more integrated
`circuits to provide the functionality of the device. For
`example, a thumb drive may include an integrated circuit for
`interfacing with a computer (for example, personal com
`puter, laptop, server, workstation, etc.) via one of the ports
`of the computer (for example, Universal Serial Bus, parallel
`port, etc.) and at least one other memory integrated circuit
`(for example, flash memory). As such, when the thumb drive
`is coupled to a computer, data can be read from and written
`to the memory of the thumb drive. Accordingly, a user may
`store personalized information (for example, presentations,
`Internet access account information, etc.) on his/her thumb
`drive and use any computer to access the information.
`As another example, an MP3 player may include multiple
`integrated circuits to Support the storage and playback of
`digitally formatted audio (that is, formatted in accordance
`with the MP3 specification). As is known, one integrated
`circuit may be used for interfacing with a computer, another
`integrated circuit for generating a power Supply Voltage,
`another for processing the storage and/or playback of the
`digitally formatted audio data, and still another for rendering
`the playback of the digitally formatted audio.
`Integrated circuit technology has led to a plethora of
`handheld devices; however, to be “wired in today’s elec
`tronic world, multiple handheld devices would be needed.
`For example, one may own a cellular telephone for cellular
`telephone service, a PDA for scheduling, address book, etc.,
`one or more thumb drives for extended memory function
`ality, an MP3 player for storage and/or playback of digitally
`recorded music, a radio, etc. Thus, even though a single
`handheld device may be relatively small, carrying multiple
`handheld devices on one's person can become quite bur
`densome.
`Such handheld devices use a battery (or batteries) to
`supply power to the circuitry of the device. The greater the
`circuit power consumption, the shorter the battery life (that
`is, the length of time a device can be operated before having
`to replace or charge the battery).
`With the goal of extending battery lifespan for portable
`devices, various techniques had been used. One technique
`has been to turn off circuitry that is not needed to support the
`present function and to put the device in a “sleep' mode
`when the entire device is not in use.
`Another technique is related to improvements in inte
`grated circuit fabrication that allows for smaller devices to
`be developed and to be operated at lower voltages, thus
`consuming less power. For example, 0.18 micron Comple
`mentary Metal Oxide Semiconductor (“CMOS) integrated
`
`25
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`35
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`

`

`US 7,246,027 B2
`
`3
`With such a method and apparatus, power consumption is
`optimized on an IC-by-IC basis, as well as over time.
`DESCRIPTION OF THE DRAWINGS
`
`10
`
`15
`
`25
`
`FIG. 1 is a schematic block diagram of a multiple function
`battery operated device that includes a battery-optimized
`system-on-a-chip in accordance with the present invention;
`FIG. 2 is a schematic block diagram of another multiple
`function battery operated device that includes a battery
`optimized system-on-a-chip in accordance with the present
`invention;
`FIG. 3 is a schematic block diagram of a power conserv
`ing circuit in accordance with the present invention;
`FIG. 4 is a graph of supply voltage versus transistor speed
`in accordance with the present invention;
`FIG. 5 is a graph of integrated circuit power consumption
`versus supply voltage in accordance with the present inven
`tion;
`FIG. 6 is a logic diagram of a method for conserving
`power in accordance with the digital circuitry in accordance
`with the present invention;
`FIG. 7a is a schematic of a process sensing channel in
`accordance with the present invention;
`FIG.7b illustrates a graph that plots interrelationships of
`fabrication parameter corners versus headroom Voltage in
`accordance with the present invention;
`FIG. 8 is a schematic block diagram of an analog power
`conservation circuit in accordance with the present inven
`tion;
`FIG. 9 is a schematic diagram of the operational tempera
`ture sensor in accordance with the present invention;
`FIG. 10 is a graph of current versus temperature that
`illustrates the operation of the operational temperature sen
`sor of FIG. 9;
`35
`FIG. 11 is a schematic block diagram of a power con
`serving circuit having a first component for assessing power
`conservation for a digital circuit, and a second component
`for assessing power conservation for an analog circuit in
`accordance with the present invention; and
`FIGS. 12a, 12b, and 12c are a logic diagram for a method
`for conserving power for a mixed signal integrated circuit in
`accordance with the present invention.
`
`40
`
`DETAILED DESCRIPTION
`
`45
`
`50
`
`55
`
`FIG. 1 is a schematic block diagram of a multiple function
`battery operated device 10 that includes a battery-optimized
`system-on-a-chip 12, a battery 14, an inductor 16, a display
`18, a connector 20, and an input device 22. The multiple
`function battery operated device 10 may also be referred to
`as a handheld device. The connector 20 provides coupling
`between the battery-optimized system-on-a-chip 12 and
`external sources 34, which may be a host computer 36, a
`video decoder 38, a memory stick 40, a wireless modem 42.
`a camcorder image sensor 44. The battery-optimized sys
`tem-on-a-chip 12 includes a multimedia module 24, a high
`speed interface 28, a processing module 30, on-chip memory
`32, and an on-chip DC-to-DC converter 26. In general, the
`multiple function battery operated device 10 may be, but is
`not limited to, an MP3 player/recorder, a thumb drive
`memory extension, a digital camera, a digital camcorder, a
`DVD player/recorder, video conferencing device, a personal
`digital assistant ("PDA"), a radio, a television, and/or a CD
`player/recorder.
`65
`The DC-to-DC converter 26 is operably coupled to the
`battery 14 and inductor 16 to produce at least one supply
`
`60
`
`4
`voltage (V). In general, the DC-to-DC converter may be
`a buck converter, a boost converter, a fly-back converter, a
`half bridge converter, and/or a full bridge converter. Note
`that the DC-to-DC converter can also be an inductor-less
`configuration including a linear regulator and/or a Switched
`capacitor regulator. In one embodiment, the DC-to-DC
`converter is a boost converter that includes a sink transistor,
`at least one load transistor, and regulation circuitry. The
`regulation circuitry monitors the supply Voltage (V) with
`respect to a reference voltage and produces therefrom a
`regulation signal. The regulation signal, in one phase,
`enables the sink transistor to build up energy in the inductor
`and, in another phase, enables the load transistor to transfer
`the energy of the inductor to the supply voltage. The
`DC-to-DC converter 26 may be constructed in accordance
`with the teaching of U.S. Pat. No. 6,204.651, entitled
`METHOD AND APPARATUS FOR REGULATING ADC
`VOLTAGE, which is hereby incorporated by reference, and
`provides the supply voltage the processing module 30, the
`on-chip memory 32, the high-speed interface 28, and/or the
`multimedia module 24. The DC-to-DC converter 26 may
`also provide the supply voltage off-chip to power the display
`18 and/or the input device 22.
`The high-speed interface 28 is operably coupled to bus 25
`within the system-on-a-chip 12 and externally via the con
`nector 20. As such, the high-speed interface 28, which may
`be a universal serial bus (“USB) interface, a serial-to
`deserial interface, or parallel interface, provides connectiv
`ity between one or more external sources 34 and the system
`on-a-chip 12. For example, the host computer 36, which may
`be a personal computer, laptop, workstation, etc., provides
`digitized audio (for example, an MP3 file, WMA Windows
`Media Architecture , MP3 PRO, Ogg Vorbis, AAC
`Advanced Audio Coding, a CD file, etc.) and/or digitized
`video signals (for example, an MPEG (motion picture expert
`group) file, a JPEG (joint photographic expert group) file, a
`DVD file, a video graphics file, a text file, etc.) to the
`high-speed interface 28. The high-speed interface 28 con
`verts the format of the received data into a generic format of
`the system-on-a-chip, which is based on the type of pro
`cessing module 30 and/or the type of on-chip memory 32.
`The high-speed interface then provides the generic for
`matted data to the processing module 30, the on-chip
`memory 32, and/or the multimedia module 24. For instance,
`the digitalized audio and/or video data may be stored in the
`on-chip memory 32 for later playback, where the processing
`module 30 controls the storing of the data via a multimedia
`application 46. Note that processing module 30 may be a
`single processing device or a plurality of processing devices.
`Such a processing device may be a microprocessor, micro
`controller, digital signal processor, microcomputer, central
`processing unit, field programmable gate array, program
`mable logic device, state machine, logic circuitry, analog
`circuitry, digital circuitry, and/or any device that manipu
`lates signals (analog and/or digital) based on operational
`instructions.
`The on-chip memory 32 may be a single memory device
`or a plurality of memory devices. Such a memory device
`may be a read-only memory, random access memory, Vola
`tile memory, non-volatile memory, static memory, dynamic
`memory, flash memory, cache memory, and/or any device
`that stores digital information. Note that when the process
`ing module 30 implements one or more of its functions via
`a state machine, analog circuitry, digital circuitry, and/or
`logic circuitry, the memory storing the corresponding opera
`tional instructions may be embedded within, or external to.
`the circuitry comprising the state machine, analog circuitry,
`
`

`

`15
`
`5
`digital circuitry, and/or logic circuitry. The memory 32
`stores, and the processing module 30 executes, operational
`instructions corresponding to multimedia applications 46
`that include, but are not limited to audio playback, audio
`record, video playback, video record, storing text, displaying
`text, storing video graphics, file system transfer, and/or
`displaying video graphics.
`The data that is stored in the on-chip memory 32 may be
`Subsequently retrieved under the control of the processing
`module 30 while executing a multimedia application 46 to
`render the data audible and/or visible. In this instance, the
`processing module 30 causes the data to be retrieved from
`the on-chip memory 32 and to be provided to the multimedia
`module 24. The multimedia module 24 processes the data to
`produce rendered output data 52, which may include analog
`audio signals, digital audio signals, analog video signals,
`digital video signals, text, and/or video graphics, and pro
`vides the rendered output data 52 to the display 18. The
`display 18, which may be a headphone jack, a speaker or
`speakers, a Liquid Crystal Display (“LCD) video graphics
`display, an electro-luminance backlight video graphics dis
`play, etc., converts the rendered output data 52 into audible
`and/or visual information.
`In other examples, the high-speed interface 28 may
`exchange audio data, video data, video graphics data, and/or
`text data with the video decoder 38, the memory stick 40, the
`wireless modem 42, and/or the camcorder image sensor 44.
`As such, the multiple function battery operated device 10
`may function as a portable MP3 player/recorder, a personal
`DVD player/recorder, a personal CD player/recorder, etc.
`The multimedia module 24 may also receive input signals
`54 from the input device 22, which may be a microphone, a
`keypad, a video capture device (for example, a digital
`camera or a digital camcorder), etc. Such input signals 54
`may be video signals, audio signals, video graphics signals,
`and/or text signals. Upon receiving the input signals 54, the
`multimedia module 24, in conjunction with the processing
`module 30 executing a multimedia application, converts the
`input signals 54 into the generic digital format of the
`system-on-a-chip for storage in the on-chip memory or for
`providing to an external source via the high-speed interface
`28.
`As one of average skill in the art will appreciate, the
`system-on-a-chip may include a memory interface operably
`coupled to the bus 25, which is coupled to a flash memory,
`or the like, to extend the memory of the battery operated
`device 10. As such, in one embodiment, all of the video,
`Video graphics, text, and/or audio data is stored in the
`on-chip memory and in another embodiment, the video,
`Video graphics, text, and/or audio data is at least partially
`stored off-chip in the external memory and retrieved when
`needed.
`As one of average skill in the art will further appreciate,
`when the battery operated, or handheld, device 10 is not
`coupled to the host device, (that is, it is in a battery powered
`mode) the processing module 30 executes a multimedia
`application 46 to detect the disconnection and to place the
`handheld device in a battery operation mode. In the battery
`operation mode, the processing module 30 retrieves, and
`Subsequently executes, a set of operational instructions from
`the on-chip memory 32 to support the battery operational
`mode. For example, the battery operational mode may
`correspond to MP3 file playback, digital dictaphone record
`ing, MPEG file playback, JPEG file playback, text messag
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`ing display, cellular telephone functionality, and/or AM/FM
`radio reception.
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`As one of average skill in the art will still further
`appreciate, due to the comprehensiveness of the system-on
`a-chip 12, the battery-operated device 10 requires minimal
`additional components, thus reducing cost and complexity
`of the resulting device 10. Further, by including battery
`optimizing techniques, the system-on-a-chip optimally con
`sumes power to fully extend the life of the battery.
`FIG. 2 is a schematic block diagram of another multiple
`function battery operated device 60 that includes a battery
`optimized system-on-a-chip 62, a plurality of external
`memories 86, the battery 14, an external power source 68, a
`video and/or text display 78, a headphone jack 74, speaker
`(s) 76, a microphone 84, a keypad 82, and a video capture
`device 80.
`The battery-optimized system-on-a-chip 62 includes a
`plurality of high-speed interfaces 28, a plurality of memory
`interfaces 64, a plurality of processing modules 30, the
`DC-to-DC converter 26, a battery charger 66, the on-chip
`memory 32, the multimedia module 24, a power conserving
`circuit 250 providing an adjust signal 252 (which will be
`described in greater detail with reference to FIGS. 3 through
`12), and an electro-luminance backlighting drive circuitry
`70. The multimedia module 24 includes a capacitor-less
`headphone driver 72. The on-chip memory 32 includes
`random access memory (“RAM) 90 and read only memory
`(“ROM) 88.
`The plurality of high-speed interfaces 28-1 through 28-n
`allow the system-on-a-chip 62 to be simultaneously coupled
`to multiple external sources 34. The high-speed interfaces
`may utilize the same or different interface protocols. For
`example, all of the high-speed interfaces 28 may utilize a
`USB interface protocol, an Ethernet interface protocol, a
`fire-wire interface protocol, a serial/deserial interface pro
`tocol, etc. Alternatively, each high-speed interface 28-1
`through 28-n may use a different interface protocol. For
`instance, high-speed interface 28-1 may support a USB
`interface, high-speed interface 28-2 may support Ethernet,
`and high-speed interface 28-n may support a fire-wire inter
`face. One or more of the processing modules 30-1 through
`30-in coordinates and arbitrates the high-speed interfaces 28
`access to the bus 25.
`The plurality of memory interfaces 64-1 through 64-n
`allow the system-on-a-chip 62 to be coupled to a plurality of
`external memory devices 86-1 through 86-in. The external
`memory devices 86-1 through 86-in may be NAND flash
`memory devices, NOR flash memory devices, and/or any
`other type of random access memory devices or read only
`memory devices.
`While executing one or more multimedia applications,
`one or more of the processing modules 30 coordinates the
`reading and/or writing of multimedia data to and from the
`external memory devices 86. For instance, one of the
`external memory devices 86 may store MP3 files for sub
`sequent playback, another external memory device 86, may
`store video files (for example, MPEG, JPEG, etc.) for
`Subsequent playback, and another external memory device
`may store text and/or videographics relating to operation of
`the device 60 and/or related to inputted data via the keypad
`82, the video capture device 80, and/or one of the external
`sources 34 (see FIG. 1).
`Each of the external memory devices 86 may or may not
`be compliant with a memory interface standard. As such, the
`memory interfaces 64 include a flexible topology to accom
`modate the various types of external memory devices 86 that
`may be coupled to the system-on-a-chip 62. For a detailed
`discussion of the functionality of the memory interfaces 64
`refer to U.S. patent application entitled FLEXIBLE
`
`

`

`7
`MEMORY INTERFACE SYSTEM, having Ser. No. 10/865,
`585 and a filing date of Jun. 10, 2004, which is hereby
`incorporated by reference.
`The multimedia module 24 is operably coupled to receive
`input signals 54 from a microphone 84, a keypad 82, and/or
`a video capture device 80. The video capture device 80 may
`be a digital camera and/or a digital camcorder that Supplies
`MPEG files, JPEG files, and/or other standardized format for
`still and/or motion digital images. The multimedia module
`24 receives the digital video images from the video capture
`device 80 and either converts them into the generic format
`of the system-on-a-chip to produce generic video that are
`stored either in the on-chip memory 32 and/or in the external
`memory 86 or provides the digital video images to the bus
`25 for storage in the on-chip memory 32 and/or in the
`external memory 86. One or more of the processing modules
`30 coordinates the storing of the digital video images and
`whether the data will be converted to the generic format or
`not. The generic format may involve portioning packets of
`the video image into data words of a size corresponding to
`the bus width of the processing modules 30, storage word
`size of the on-chip or off-chip memory, and/or of the bus
`width of the bus 25.
`The multimedia module 24 is also coupled to receive
`input signals 54 from the keypad 82. The keypad 82 may be
`a touch screen pad, a keyboard, Voice recognition module,
`and/or any device that produces text messages. The multi
`media module 24 receives the text messages from the
`keypad 82 and either processes them for display on the video
`and/or text display 78 or for storage in the RAM 90 and/or
`in the external memory 86. The processing of the text
`message may involve routing it to the video and/or text
`display 78, converting it to the generic format for storing in
`the RAM 90 or the external memory 86, or rendering it for
`display (that is, converting text information into pixel infor
`mation).
`The multimedia module 24 is further coupled to receive
`input signals 54 from the microphone 84. The multimedia
`module 24 converts the analog audio input signals from the
`microphone 84 into digital audio input signals using an
`encoding scheme, such as pulse code modulation (“PCM).
`The multimedia module 24 provides the digital audio signals
`to the RAM 90 and/or the external memory 86 for storage
`under the control of the processing module 30, which is
`executing an audio recording multimedia application 46.
`Accordingly, in this mode, the multiple function battery
`operated device 60 may function as a dictaphone.
`The multimedia module 24 is operably coupled to provide
`analog audio signals to the speaker(s) 76 and/or to the
`headphone jack 74. The multimedia module 24 may gener
`ate the analog audio signals by performing a PCM decoding
`of digital audio signals stored in the on-chip memory 32
`and/or stored in the external memory 86. The multimedia
`module 24 includes a driver, or multiple drivers, to supply
`the analog audio signals to the speaker(s) 76. The multime
`dia module 24 also includes the capacitor-less headphone
`driver 72 to Supply the analog audio signals to the head
`phone jack. The capacitor-less headphone driver 72 reduces
`the number of external components by eliminating the need
`for coupling capacitors from the on-chip drivers to the
`headphone jack, wherein the coupling capacitors enabled
`level shifting of the analog audio signals from the driver
`level of 0.9-volts (for example, an alternating current
`(“AC) ground for the left channel and right channel drivers)
`to 0-volts for the headphones. By reducing the number of
`required external components, the cost of producing a mul
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`tiple function battery operated device 60 is reduced without
`sacrificing features and/or functionality.
`The multimedia module 24 is further coupled to the video
`and/or text display 78, which may be an electro-luminance
`backlight display, an LCD display, or any other type of
`display that displays text, video graphics, and/or video
`images (still or motion). The multimedia module 24 receives
`digital video data from the on-chip memory and/or an
`external memory 86 under the control of the processing
`module 30, which is executing a text and/or video playback
`multimedia application. Upon receiving the digital video
`data, the multimedia module 24 converts it into pixel infor
`mation (for example, RGB, YUV. YCrCb, etc.), which is
`provide