Trials@uspto.gov Paper No. 46
`571-272-7822
` Entered: March 10, 2021
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`INTEL CORPORATION,
`Petitioner,
`v.
`TELA INNOVATIONS, INC.,
`Patent Owner.
`
`IPR2019-01637
`Patent 10,141,335 B2
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`
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`Before JO-ANNE M. KOKOSKI, KRISTINA M. KALAN, and
`WESLEY B. DERRICK, Administrative Patent Judges.
`KALAN, Administrative Patent Judge.
`
`
`
`JUDGMENT
`Final Written Decision
`
`Determining All Challenged Claims Unpatentable
`35 U.S.C. § 318(a)
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`INTRODUCTION
`I.
`Intel Corporation (“Petitioner”) filed a Petition (Paper 2, “Pet.”)
`requesting inter partes review of claims 1–11, 15, 18, 20, and 22–24 of U.S.
`Patent No. 10,141,335 B2 (Ex. 1001, “the ’335 patent”). Tela Innovations,
`Inc. (“Patent Owner”) filed a Preliminary Response to the Petition.
`Paper 11. We authorized additional briefing on the issues set forth in the
`Preliminary Response. Paper 13. Petitioner in turn filed a Reply to Patent
`Owner’s Preliminary Response (Paper 14) and Patent Owner filed a Sur-
`Reply to Petitioner’s Preliminary Reply (Paper 15).
`We instituted an inter partes review of claims 1–11, 15, 18, 20,
`and 22–24 of the ’335 patent on the ground of unpatentability alleged in the
`Petition. Paper 16 (“Dec.”). After institution of trial, Patent Owner filed a
`Patent Owner Response. Paper 28 (“PO Resp.”). Petitioner filed a Reply.
`Paper 35 (“Reply”). Patent Owner filed a Sur-Reply. Paper 38 (“Sur-
`Reply”). An oral hearing was held on December 9, 2020, and a transcript of
`the hearing is included in the record. Paper 45 (“Tr.”).
`This Final Written Decision is issued pursuant to 35 U.S.C. § 318(a).
`For the reasons that follow, we determine that Petitioner has shown by a
`preponderance of the evidence that claims 1–11, 15, 18, 20, and 22–24 of
`the ’335 patent are unpatentable.
`Related Proceedings
`A.
`The parties state that the ’335 patent is at issue in a number of
`proceedings, including Intel Corp. v. Tela Innovations, Inc., No. 3:18-cv-
`02848-WHO (N.D. Cal.) (the “NDCA Action”). Pet. 3–5, Paper 5, 2. The
`parties also state that the ’335 patent was at issue in an International Trade
`Commission (“ITC”) investigation, Inv. No. 337-TA-1148 (the “ITC
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`Proceeding”), but was later terminated from the ITC Proceeding. Pet. 3; PO
`Resp. 3.
`The ’335 Patent
`B.
`The ’335 patent, titled “Semiconductor Cip [sic] Including Region
`Having Rectangular-Shaped Gate Structures and First-Metal Structures,” is
`directed to an integrated circuit. Ex. 1001, code (54), 4:37–39. The ’335
`patent explains that a push for circuit chip area reduction in the
`semiconductor industry has resulted in improvements in the lithographic
`process that enable smaller feature sizes to be achieved. Id. at 3:60–4:4. In
`the evolution of lithography, the minimum feature size approached, and
`subsequently reached a scale less than, the wavelength of the light source
`used to expose the feature shapes, leading to unintended interactions
`between neighboring features. Id. at 4:5–8. The ’335 patent defines the
`difference between the minimum feature size and the wavelength of light as
`the lithographic gap. Id. at 4:11–13. The ’335 patent further describes that
`an interference pattern occurs as each shape on the mask interacts with the
`light. Id. at 4:16–17. The interference patterns from neighboring shapes can
`create constructive or destructive interference. Id. at 4:17–19. In view of
`the foregoing, the ’335 patent identifies a need for a solution that manages
`lithographic gap issues as technology continues to progress toward smaller
`semiconductor device feature sizes. Id. at 4:30–33.
`The ’335 patent describes that a dynamic array architecture is
`provided to address semiconductor manufacturing process variability
`associated with a continually increasing lithographic gap. Id. at 8:62–65.
`Figure 2 of the ’335 patent, shown below, illustrates a generalized stack of
`layers used to define a dynamic array architecture.
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`Figure 2 depicts the generally underlying structure of a dynamic array. Id.
`at 11:4–18. The dynamic array is built up in a layered manner upon base
`substrate 201 (e.g., a silicon substrate or silicon-on-insulator (SOI)
`substrate). Id. at 11:20–22. Diffusion regions 203 are defined in base
`substrate 201 and represent selected regions of base substrate 201 within
`which impurities are introduced for the purpose of modifying the electrical
`properties of base substrate 201. Id. at 11:22–27. Above diffusion
`regions 203, diffusion contacts 205 are defined to enable connection
`between diffusion regions 203 and conductor lines. Id. at 11:27–29. Gate
`electrode features 207 are defined above diffusion regions 203 to form
`transistor gates. Id. at 11:32–34. Gate electrode contacts 209 are defined to
`enable connection between gate electrode features 207 and conductor lines.
`Id. at 11:34–36. Interconnect layers are defined above diffusion contact 205
`layer and gate electrode contact layer 209. Id. at 11:39–40. The
`interconnect layers include first metal (metal 1) layer 211, first via (via 1)
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`layer 213, second metal (metal 2) layer 215, second via (via 2) layer 217,
`third metal (metal 3) layer 219, third via (via 3) layer 221, and fourth metal
`(metal 4) layer 223. Id. at 11:40–45.
`Figure 5 of the ’335 patent is shown below:
`
`Figure 5 illustrates an exemplary layout of a dynamic array that includes a
`gate electrode layer, a diffusion contact layer, and a diffusion layer. Id.
`at 16:10–13. The diffusion layer shows p-diffusion region 401 and n-
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`diffusion region 403. Id. at 15:52–54. The gate electrode layer shows gate
`electrode features 501 that define the transistor gates. Id. at 16:13–15. Gate
`electrode features 501 are defined as linear shaped features extending in a
`parallel relationship across the dynamic array in a “y” reference direction.
`Id. at 16:15–18. Gate electrode features 501 form n-channel and p-channel
`transistors as they cross diffusion regions 403 and 401, respectively. Id.
`at 16:30–32. The ’335 patent describes that each of the gate electrode tracks
`may be interrupted any number of times in linearly traversing across the
`dynamic array in order to provide required electrical connectivity for a
`particular logic function to be implemented. Id. at 16:41–44. When a given
`gate electrode track is required to be interrupted, the separation between
`ends of the gate electrode track segments at the point of interruption is
`minimized to the extent possible. Id. at 16:45–49. Minimizing the
`separation between ends of the gate electrode track segments at the points of
`interruption serves to maximize the lithographic reinforcement, and
`uniformity therefor, provided from neighboring gate electrode tracks. Id.
`at 16:53–56.
`Figure 8B of the ’335 patent is shown below:
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`Figure 8B depicts metal 1 layer defined above the gate electrode layer of
`Figure 5, in accordance with one embodiment of the invention. Id. at 17:38–
`41, 21:41–43, 22:21–24. Specifically, metal 1 layer includes a number of
`metal 1 tracks 801–821 defined to include linear shaped features extending
`in a parallel relationship across the dynamic array. Id. at 21:43–46.
`The ’335 patent states that a semiconductor chip can include a region
`having at least ten conductive structures, with some of the conductive
`structures forming at least one transistor gate electrode. Id. at 5:50–57. The
`conductive structures each have a width in a direction that is perpendicular
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`to a direction along its lengthwise centerline and that is less than 45
`nanometers. Id. at 6:16–19, 6:27–30, 6:38–39. The ’335 patent further
`states that the pitch between the lengthwise centerlines of conductive
`structures is less than or equal to about 193 nanometers. Id. at 6:40–46.
`With regard to the embodiments depicted in Figures 8A and 8B, the ’335
`patent discloses that the pitch of metal 1 tracks 801–821 and metal 2 tracks
`1001 is minimized while ensuring optimization of lithographic
`reinforcement provided by neighboring tracks. Id. at 21:51–55, 22:57–60.
`In one example, metal 1 tracks 801–821 are centered on a vertical grid of
`about 0.24 µm for a 90 nm process technology. Id. at 21:55–57. In another
`example, the optimum contacted gate electrode track pitch is 0.36 µm and
`the optimum metal 2 track pitch is 0.24 µm for a 90 nm process technology.
`Id. at 23:5–8.
`Illustrative Claim
`C.
`Petitioner challenges claims 1–11, 15, 18, 20, and 22–24 of the ’335
`patent. Independent claim 1 is illustrative of the challenged claims and is
`reproduced below:
`1. A semiconductor chip, comprising:
`gate structures formed within a region of the semiconductor
`chip, the gate structures formed in part based on corresponding
`gate structure layout shapes used as an input to a lithography
`process, the gate structure layout shapes positioned in
`accordance with a gate horizontal grid, the gate horizontal grid
`including at least seven gate gridlines, each gate structure
`layout shape having a substantially rectangular shape and
`positioned to extend lengthwise in a y-direction in a
`substantially centered manner along an associated gate gridline,
`each gate gridline having at least one gate structure layout
`shape positioned thereon, wherein adjacently positioned ones of
`the gate structures are separated from each other by a gate pitch
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`of less than or equal to about 193 nanometers, each of the gate
`structures having a width of less than or equal to about 45
`nanometers, wherein each pair of the gate structures that are
`positioned in and end-to-end manner are separated from each
`other by a line end-to-line end gap of less than or equal to about
`193 nanometers;
`a first-metal layer formed above top surfaces of the gate
`structures within the region of the semiconductor chip, the first-
`metal layer positioned first in a stack of metal layers counting
`upward from top surfaces of the gate structures, the first-metal
`layer separated from the top surfaces of the gate structures by at
`least one insulator material, adjacent metal layers in the stack of
`metal layers separated by at least one insulator material,
`wherein the first-metal layer includes first-metal structures
`formed in part based on corresponding first-metal structure
`layout shapes used as an input to a lithography process, the
`first-metal structure layout shapes positioned in accordance
`with a first-metal vertical grid, the first-metal vertical grid
`including at least eight first-metal gridlines, each first-metal
`structure layout shape having a substantially rectangular shape
`and positioned to extend lengthwise in an x-direction in a
`substantially centered manner on an associated first-metal
`gridline, each of the first-metal structures having at least one
`adjacent first-metal structure positioned next to each of its sides
`at a y-coordinate spacing of less than or equal to 193
`nanometers, wherein each pair of the first-metal structures that
`are positioned in an end-to-end manner are separated by a line
`end-to-line end gap of less than or equal to about 193
`nanometers;
`at least six contact structures formed within the region of the
`semiconductor chip, the at least six contact structures formed in
`part utilizing corresponding at least six contact structure layout
`shapes as an input to a lithography process, the at least six
`contact structures formed in physical and electrical contact with
`corresponding ones of at least six of the gate structures, each of
`the at least six contact structure layout shapes having a
`substantially rectangular shape and a corresponding length
`greater than a corresponding width and with the corresponding
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`length oriented in the x-direction, each of the at least six contact
`structure layout shapes positioned and sized to form its
`corresponding contact structure to overlap both edges of the top
`surface of the gate structure to which it is in physical and
`electrical contact,
`wherein at least one gate structure within the region is a
`first-transistor-type-only gate structure that forms at least one
`gate electrode of at least one transistor of a first transistor type
`and does not form a gate electrode of a transistor of a second
`transistor type, wherein at least one gate structure within the
`region is a second-transistor-type-only gate structure that forms
`at least one gate electrode of at least one transistor of the second
`transistor type and does not form a gate electrode of a transistor
`of the first transistor type, wherein a total number of first-
`transistor-type-only gate structures within the region is equal to
`a total number of second-transistor-type-only gate structures
`within the region, wherein the region includes at least four
`transistors of the first transistor type and at least four transistors
`of the second transistor type that collectively form part of a
`logic circuit.
`Ex. 1001, 30:2–31:13.
`Instituted Grounds of Unpatentability
`D.
`We instituted inter partes review of claims 1–11, 15, 18, 20, and 22–24
`of the ’335 patent on the following ground:
`Reference(s)/Basis
`Claims Challenged
`
`35 U.S.C. §
`
`Becker,1 Greenway2
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`1–11, 15, 18, 20, 22–24
`
`§ 103
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`1 US 7,446,352 B2, issued Nov. 4, 2008 (Ex. 1006).
`2 Greenway, Robert, et al., Interference Assisted Lithography for Patterning
`of 1D Gridded Design, vol. 7271, SPIE, p. 72712U-1 (2009) (Ex. 1013).
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`Petitioner relies on the declaration testimony of Dr. Stanley Shanfield.
`Ex. 1002; Ex. 1062. Patent Owner relies on the declaration testimony of
`Dr. Sunil P. Khatri. Ex. 2074.
`II. ANALYSIS
`Legal Standards
`A.
`A claim is unpatentable under 35 U.S.C. § 103(a) if the differences
`between the subject matter sought to be patented and the prior art are such
`that the subject matter as a whole would have been obvious to a person of
`ordinary skill in the art at the time the invention was made. KSR Int’l Co. v.
`Teleflex Inc., 550 U.S. 398, 406 (2007). Obviousness is resolved based on
`underlying factual determinations, including: (1) the scope and content of
`the prior art; (2) differences between the prior art and the claims at issue;
`(3) the level of ordinary skill in the art; and (4) when in evidence, objective
`evidence of nonobviousness, i.e., secondary considerations.3 Graham v.
`John Deere Co., 383 U.S. 1, 17–18 (1966). The totality of the evidence
`submitted may show that the challenged claims would not have been
`obvious to one of ordinary skill in the art. In re Piasecki, 745 F.2d 1468,
`1471–72 (Fed. Cir. 1984).
`Petitioner bears the burden of proving unpatentability of the
`challenged claims, and the burden of persuasion never shifts to Patent
`Owner. Dynamic Drinkware, LLC v. Nat’l Graphics, Inc., 800 F.3d 1375,
`1378 (Fed. Cir. 2015). Petitioner must demonstrate unpatentability by a
`preponderance of the evidence. 35 U.S.C. § 316(e) (2018); 37 C.F.R. §
`
`
`3 Patent Owner does not present any objective evidence of nonobviousness
`in this case and, therefore, we do not address this Graham factor.
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`42.1(d); see also Harmonic Inc. v. Avid Tech., Inc., 815 F.3d 1356, 1363
`(Fed. Cir. 2016) (citing 35 U.S.C. § 312(a)(3) (2012) (requiring inter partes
`review petitions to identify “with particularity . . . the evidence that supports
`the grounds for the challenge to each claim”)).
`Level of Ordinary Skill in the Art
`B.
`Petitioner contends that a person of ordinary skill in the art “would
`have been a person having a Bachelor’s degree in Electrical Engineering,
`Physics or Materials Science with three to five years of industry experience
`in semiconductor IC design, layout or fabrication,” but that “[a]dditional
`education might compensate for less experience, and vice-versa.” Pet. 19–
`20 (citing Ex. 1002 ¶¶ 63–66).
`Patent Owner contends that a person of ordinary skill in the art
`“would have had: (1) a Bachelor’s degree in Electrical Engineering, with
`five years of experience in semiconductor layout technology and integrated
`circuit design; (2) a Master’s degree in Electrical Engineering, with three
`years of experience in the same field; or (3) comparable experience.” PO
`Resp. 20 (citing Ex. 2074 ¶ 78). Patent Owner also argues that the
`challenged claims are not obvious under either Petitioner’s or Patent
`Owner’s definition of the level of ordinary skill in the art. Id.
`Neither party argues that the outcome of this case would differ based
`on our adoption of any particular definition of one of ordinary skill in the art.
`On this record, we find that the differences in the parties’ contentions as to
`the level of ordinary skill are not consequential, in part because the levels of
`skill set forth by both Petitioner and Patent Owner are based on a Bachelor’s
`degree in Electrical Engineering and a length and type of experience that
`overlap. Accordingly, we adopt Patent Owner’s definition, which overlaps
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`that set forth by Petitioner, particularly regarding a Bachelor’s degree in
`Electrical Engineering, with five years of experience in semiconductor
`layout technology and integrated circuit design, and because it is consistent
`with the cited prior art. We further note that the prior art itself demonstrates
`the level of skill in the art at the time of the invention. See Okajima v.
`Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001) (explaining that “specific
`findings on the level of skill in the art . . . [are not required] ‘where the prior
`art itself reflects an appropriate level and a need for testimony is not
`shown’” (quoting Litton Indus. Prods., Inc. v. Solid State Sys. Corp., 755
`F.2d 158, 163 (Fed. Cir. 1985))).
`Claim Construction
`C.
`We apply the claim construction standard articulated in Phillips v.
`AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc). 37 C.F.R.
`§ 42.100(b) (2019). Under Phillips, claim terms are afforded “their ordinary
`and customary meaning.” Phillips, 415 F.3d at 1312. “[T]he ordinary and
`customary meaning of a claim term is the meaning that the term would have
`to a person of ordinary skill in the art in question at the time of the
`invention.” Id. at 1313. Only terms that are in controversy need to be
`construed, and only to the extent necessary to resolve the controversy. Vivid
`Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999).
`Petitioner notes that there are disputed claim terms in the NDCA
`Action—namely, the terms “gate electrode,” “gate structure(s),” and
`“contact structure(s)”—but asserts that Becker and Greenway render the
`challenged claims obvious under any of the proposed constructions.
`Pet. 31–32. In light of this, Petitioner states that the Board does not need to
`construe any claim term in order to evaluate the asserted prior art. Id.
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`Patent Owner provides the district court’s construction of the claim
`terms “gate electrode,” “gate structure(s),” and “contact structure(s)” in the
`NDCA Action, stating that Patent Owner “applies the District Court
`constructions” of these claim terms. PO Resp. 21–22. Patent Owner,
`however, does not expressly argue for those constructions, and states that
`“Petitioner’s obviousness arguments fail regardless of whether any of the
`above claims constructions are adopted by the Board.” Id. at 22.
`On the full record now before us, we determine it is not necessary to
`construe any claim term expressly to resolve the parties’ dispute. Vivid
`Techs., 200 F.3d at 803; Nidec Motor Corp. v. Zhongshan Broad Ocean
`Motor Co., 868 F.3d 1013, 1017 (Fed. Cir. 2017) (applying Vivid Techs. in
`an inter partes review).
`Asserted Prior Art
`D.
`Becker
`1.
`Becker is a patent titled “Dynamic Array Architecture,” issued on
`November 4, 2008. Ex. 1006, codes (54), (45). Like the ’335 patent, Becker
`claims priority to Provisional Application No. 60/781,288, which was filed
`Mar. 9, 2006. Pet. 33; Ex. 1006, code (60); Ex. 1001, code (60).4 Unlike
`the ’335 patent, Becker does not include what Petitioner characterizes as
`“new matter” added to the 2015 Application. Pet. 19, 33; Ex. 1008, 21–24,
`68–71. Petitioner states that, other “than the claimed dimensions, Becker
`discloses the very same 1D gridded regular layout and 1D structures found
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`4 Patent Owner does not challenge Becker’s status as prior art,
`notwithstanding Patent Owner’s arguments about the priority date of
`the ’335 patent.
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`in the ’335 Patent.” Pet. 33. Becker also has the same inventive entity as
`the ’335 patent. Ex. 1006, code (75); Ex. 1001, code (72).
`Becker is directed to “a dynamic array architecture . . . to address
`semiconductor manufacturing process variability associated with a
`continually increasing lithographic gap.” Ex. 1006, 4:11–14.
`Figure 5 of Becker, shown below, illustrates an exemplary layout of a
`dynamic array.
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`The dynamic array of Figure 5 includes a gate electrode layer, a diffusion
`contact layer, and a diffusion layer. Id. at 10:55–57, 11:13–16. The
`diffusion layer shows p-diffusion region 401 and n-diffusion region 403. Id.
`at 10:57–58. The gate electrode layer shows gate electrode features 501 that
`define the transistor gates. Id. at 11:16–18.
`Figure 8B of Becker, shown below, illustrates an exemplary layout of
`a dynamic array.
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`Figure 8B depicts a metal 1 layer of Figure 8A (not shown) with larger track
`widths for the metal 1 ground and power tracks. Id. at 3:30–32. Becker
`states that Figure 8A illustrates a metal 1 layer defined above the gate
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`electrode contact layer of Figure 6, which in turn depicts a gate electrode
`contact layer above and adjacent to the gate electrode layer of Figure 5. Id.
`at 12:38–40, 13:29–31. The metal 1 layer of Figure 8B includes a number of
`metal 1 tracks 801–821 defined to include linear shaped features extending
`in a parallel relationship across the dynamic array. Id. at 13:31–34. Becker
`discloses that the widths of metal 1 tracks 801 and 821 are the same as the
`other metal 1 tracks 803–819 in the embodiment of Figure 8A, but in the
`embodiment of Figure 8B, the widths of metal 1 tracks 801 and 821 are
`larger than the widths of metal 1 tracks 803–819. Id. at 14:1–7.
`Greenway
`2.
`Greenway is a publication titled “Interference Assisted Lithography
`for Patterning of 1D Gridded Design.” Ex. 1013, 1. Greenway discloses
`technical issues with Extreme Ultra Violet Lithography (EUVL), high-index
`immersion 193nm lithography, double patterning, and nano-imprinting, and
`that “[n]o satisfactory cost-effective solutions exist for the patterning of
`32nm half pitch features and beyond.” Id. In view of this, Greenway states
`that Interference Assisted Lithography (IAL) can be a promising cost-
`effective lithography solution. Id. Greenway further discloses that, because
`IAL does not need large, expensive lenses, IAL can be adopted for an
`interference lithography tool and is enabled to extend beyond the pitch limit
`of current Optical Projection Lithography (OPL). Id.
`Greenway states that IAL implementation requires converting 2D
`random layouts to highly regular 1D gridded designs. Id. at 2. According to
`Greenway, 1D “gridded design rules” (GDR) “refer to a layout style in
`which critical layers are drawn with 1D lines on a coarse grid.” Id. Figure 1
`of Greenway is shown below:
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`Figure 1 of Greenway depicts a 1D GDR layout (left side) and a 2D
`“complex design rules” (CDR) layout (right side). Id. at 3. Greenway states
`that the left side of Figure 1 shows vertical gate lines with a uniform pitch
`with dummy lines, as needed. Id. at 2. Horizontal first metal lines also have
`a uniform pitch with circuit line segments separated by uniform gaps with
`diffusion and gate contacts located at intersections of grid lines. Id.
`Greenway further discloses the design of a 6T SRAM bitcell using 1D
`regular-pitch gridded design rules. Id. at 3. Figure 4 of Greenway is shown
`below:
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`Figure 4 of Greenway illustrates candidate bitcell layouts. Id. at 5.
`Greenway discloses that Figure 4(A) illustrates one candidate for 1D regular
`pitch layout in which IAL was not applied to the diffusion layer, but has a
`smaller size. Id. at 4. Figure 4(B) depicts another candidate for a full
`layer 1-D regular pitch layout in which the diffusion layer is also IAL-
`compatible. Id. Greenway states “[i]n the present study, we consider 6 grids
`per poly pitch with 22nm per grid.” Id.
`Analysis of Priority Claim
`E.
`On its face, the ’335 patent claims priority to a number of
`applications, including U.S. Provisional Patent Application No. 60/781,288,
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`filed Mar. 9, 2006 (Ex. 1005, “the 2006 Provisional Application”), U.S.
`Application Ser. No. 11/683,402, filed Mar. 7, 2007 (Ex. 1007, “the 2007
`Original Application”), and U.S. Application Ser. No. 14/711,731, filed May
`13, 2015 (Ex. 1008, “the 2015 Application”). Ex. 1001, codes (60), (63).
`Petitioner challenges the ’335 patent’s claim of priority to the 2006
`Provisional Application, arguing that the ’335 patent’s priority date can be
`no earlier than 2015. Pet. 15–19, 20–31; Reply 4–13. Patent Owner argues
`that the ’335 patent is entitled to its claimed priority date of March 9, 2006,
`and, therefore, Becker and Greenway are not prior art. PO Resp. 27–60;
`Sur-Reply 4–13.
`Parties’ Arguments Regarding the ’335 Patent Itself and
`1.
`“Scalability”
`As Patent Owner notes, 35 U.S.C. § 112 ¶ 1 (pre-AIA) stands for the
`proposition that a patent specification “shall contain a written description of
`the invention, and of the manner and process of making and using it” and
`must “contain a written description of the invention . . . to enable any person
`skilled in the art . . . to make and use the same.” PO Resp. 27–28. Also,
`“the written description requirement may be satisfied by any combination of
`the words, structures, figures, formulas, etc., contained in the patent
`application.” Id. at 28 (citing Lockwood v. Am. Airlines, Inc., 107 F.3d
`1565, 1572 (Fed. Cir. 1997)).
`“It is elementary patent law that a patent application is entitled to the
`benefit of the filing date of an earlier filed application only if the disclosure
`of the earlier application provides support for the claims of the later
`application, as required by 35 U.S.C. § 112.” PowerOasis, Inc. v. T-Mobile
`USA, Inc., 522 F.3d 1299, 1306 (Fed. Cir. 2008); see also Research Corp.
`
`
`
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`IPR2019-01637
`Patent 10,141,335 B2
`
`Techs. v. Microsoft Corp., 627 F.3d 859, 871–72 (Fed. Cir. 2010) (holding
`the later-filed application, with claims that were not limited to a “blue noise
`mask,” was not entitled to the priority filing date of the parent application,
`which was “limited to a blue noise mask”); ICU Med., Inc. v. Alaris Med.
`Sys., 558 F.3d 1368, 1377–78 (Fed. Cir. 2009) (holding that “spikeless”
`claims “added years later during prosecution” were not supported by the
`specification which “describes only medical valves with spikes”); Tronzo v.
`Biomet, Inc., 156 F.3d 1154, 1158–60 (Fed. Cir. 1998) (holding the generic
`shaped cup claims of the later-filed child application were not entitled to the
`filing date of the parent application that “disclosed only a trapezoidal cup
`and nothing more”). “To satisfy the written description requirement the
`disclosure of the prior application must ‘convey with reasonable clarity to
`those skilled in the art that, as of the filing date sought, [the inventor] was in
`possession of the invention.’” PowerOasis, 522 F.3d at 1306 (alteration in
`original). The sufficiency of written description support is based on “an
`objective inquiry into the four corners of the specification from the
`perspective of a person of ordinary skill in the art.” Ariad Pharm., Inc. v. Eli
`Lilly & Co., 598 F.3d 1336, 1351 (Fed. Cir. 2010) (en banc). It is well
`settled that the written description requirement of § 112 requires the
`disclosure to convey that Patent Owner had possession of the entire range of
`claimed values. In re Lukach, 442 F.2d 967, 969 (CCPA 1971).
`Petitioner argues that the inventors were not in possession of
`semiconductor chips with the claimed dimensions at the time of the 2006
`Provisional Application and 2007 Original Application, and that those
`earlier applications did not enable the full claimed range of dimensions.
`Pet. 20–31. The claim to priority as a continuation is improper, Petitioner
`21
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`IPR2019-01637
`Patent 10,141,335 B2
`
`argues, because “the only gate pitch disclosed in the 2006 Provisional
`Application and the 2007 Original Application is 0.36 μm, or 360nm, well
`above the 193nm upper bound of the claimed gate pitch range.” Id. at 20
`(citing Ex. 1005, 8; Ex. 1007, 30–31; Ex. 1002 ¶ 68). Petitioner argues that
`new matter added to the 2015 Application “described for the first time a
`semiconductor chip that contains structures spaced apart with a ‘first pitch
`that is less than or equal to about 193 nanometers’ and having a width that is
`‘less than 45 nanometers.’” Id. at 20–21 (citing Ex. 1008, 21–23, 68–71;
`Ex. 1002 ¶ 69). Petitioner also argues that Patent Owner, by accusing
`Petitioner of infringing the challenged claims with Petitioner’s 10nm
`processors with a 36nm minimum metal pitch, admits that any lower bound
`of the “less than or equal to” 193nm range in the claims would be well
`below 36nm and in the single-digit nanometer range. Id. at 24–25 (citing
`Ex. 1025, 14 (Dr. Khatri testifying that the “expected lower bound is
`somewhere in the single digit nanometer range.”)). According to Petitioner,
`the inventors at the time of the 2006 Provisional Application and the 2007
`Original Application did not have possession of the claimed subject matter
`down to the single-digit nanometer range or even as low as 36 nm, nor did
`those applications teach one of ordinary skill in the art how to achieve those
`dimensions. Id. at 26. In sum, Petitioner argues that the challenged claims
`are not entitled to the priority date of the 2006 Provisional Application
`(March 9, 2006) or of the 2007 Original Application (March 7, 2007).
`Instead, Petitioner argues that the earliest possible priority date for the
`challenged claims is May 13, 2015, the date the new matter was added to the
`application that ultimately led to the issuance of the ’335 patent. Id. at 30
`(citing Ex. 1002 ¶¶ 41–42, 89).
`
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`IPR2019-01637
`Patent 10,141,335 B2
`
`
`Patent Owner argues that the 2006 Provisional Application provides
`written description support for the disputed claimed limitations “each of the
`gate structures having a width of less than or equal to about 45 nanometers”
`(Ex. 1001, 30:17–18) (“Claim Element A”) and “adjacently positioned ones
`of the gate structures are separated from each other by a gate pitch of less
`than or equal to about 193 nanometers” (Ex. 1001, 30:14–17) (“Claim
`Element B”). PO Resp. 32.
`Regarding Claim Element A, Patent Owner argues that the ’335 patent
`and the 2006 Provisional Application teach a “scalable layout” technique,
`and, therefore, “the end-product, i.e., the semiconductor chip formed, would
`be scalable in the same manner.” Id. at 33–34. Thus, Claim Element A is
`supported by the 2006 Provisional Application, argues Patent Owner,
`because the “predictability of the layout designs claimed in the ’335 Patent”
`is “sufficient to demonstrate that the inventor