Case 3:18-cv-02848-WHO Document 175 Filed 11/04/19 Page 1 of 24
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`UNITED STATES DISTRICT COURT
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`NORTHERN DISTRICT OF CALIFORNIA
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`INTEL CORPORATION,
`Plaintiff,
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`v.
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`TELA INNOVATIONS, INC.,
`Defendant.
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`Case No. 3:18-cv-02848-WHO
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`CLAIM CONSTRUCTION ORDER
`Re: Dkt. No. 163
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`Before me are six patents from the same patent family, all assigned to declaratory
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`judgment defendant Tela Innovations, Inc., and all asserted against plaintiff Intel Corporation.
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`The patented technology aims to improve the design and manufacturability of integrated circuits
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`by ameliorating difficulties associated with the lithographic gap, or the size difference between
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`ever-shrinking semiconductor features and the wavelength of light used to fabricate them. The
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`parties have asked me to construe seven terms from the asserted claims. My constructions are
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`below.
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`BACKGROUND
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`Between November 4, 2008 and January 22, 2019, the United States Patent and Trademark
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`Office (“PTO”) issued United States Patent Nos. 7,446,352 (“the ’352 Patent”), 7,943,966 (“the
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`’966 Patent”), 7,948,012 (“the ’012 Patent”), 10,141,334 (“the ’334 Patent”), 10,141,335 (“the
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`’335 Patent”), and 10,186,523 (“the ’523 Patent”) (collectively, the “patents in suit”). See
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`Declaration of Frank Liu (“Liu Decl.”), Exs. 1-6 [Dkt. Nos. 166-2, 166-3, 166-4, 166-5, 166-6,
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`166-7]. All of the patents in suit are part of the same patent family, all claim priority to
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`Provisional Application No. 60/781,288, filed on March 9, 2006, and all list Tela as the sole
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`assignee.
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`TELA 2093
`Intel v Tela
`IPR2019-01520, -1521, -1522, -1637, -1637
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`Case 3:18-cv-02848-WHO Document 175 Filed 11/04/19 Page 2 of 24
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`Intel filed this declaratory judgment action on May 15, 2018.1 Dkt. No. 1. Since that time,
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`I have resolved a motion to transfer, several motions to dismiss and strike, a disputed motion for a
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`protective order, and several discovery disputes. See Dkt. Nos. 64, 70, 86, 162. The parties
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`briefed claim construction starting on June 13, 2019, and each submitted an electronic technology
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`tutorial in advance of the claim construction hearing. See Dkt. Nos. 163, 173. After providing the
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`parties with my tentative opinions, I heard argument on September 27, 2019. Dkt. Nos. 172, 173.
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`LEGAL STANDARD
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`Claim construction is a matter of law. See Markman v. Westview Instruments, Inc., 517
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`U.S. 370, 372 (1996); Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576, 1582 (Fed. Cir. 1996).
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`“Generally, a claim term is given its ordinary and customary meaning—the meaning that a term
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`would have to a person of ordinary skill in the art in question at the time of the invention.”
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`Howmedica Osteonics Corp. v. Zimmer, Inc., 822 F.3d 1312, 1320 (Fed. Cir. 2016) (internal
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`quotation marks and citation omitted). In determining the proper construction of a claim, a court
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`begins with the intrinsic evidence of record, consisting of the claim language, the patent
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`specification, and, if in evidence, the prosecution history. Phillips v. AWH Corp., 415 F.3d 1303,
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`1313 (Fed. Cir. 2005); see also Vitronics, 90 F.3d at 1582. “A claim term used in multiple claims
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`should be construed consistently . . . .” Inverness Med. Switzerland GmbH v. Princeton
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`Biomeditech Corp., 309 F.3d 1365, 1371 (Fed. Cir. 2002).
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`“The appropriate starting point . . . is always with the language of the asserted claim itself.”
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`Comark Commc’ns, Inc. v. Harris Corp., 156 F.3d 1182, 1186 (Fed. Cir. 1998). “[T]he ordinary
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`and customary meaning of a claim term is the meaning that the term would have to a person of
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`ordinary skill in the art in question at the time of the invention, i.e., as of the effective filing date
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`of the patent application.” Phillips, 415 F.3d at 1312. “There are only two exceptions to this
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`general rule: 1) when a patentee sets out a definition and acts as his own lexicographer, or 2) when
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`the patentee disavows the full scope of a claim term either in the specification or during
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`prosecution.” Thorner v. Sony Computer Entm’t Am. LLC, 669 F.3d 1362, 1365 (Fed. Cir. 2012).
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`1 The patents at issue in the case have evolved since it was initiated.
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`Case 3:18-cv-02848-WHO Document 175 Filed 11/04/19 Page 3 of 24
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`Such redefinition or disavowal need not be express to be clear. Trustees of Columbia Univ. in City
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`of New York v. Symantec Corp., 811 F.3d 1359, 1364 (Fed. Cir. 2016).
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`Courts read terms in the context of the claim and of the entire patent, including the
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`specification. Phillips, 415 F.3d at 1313. The specification is “the single best guide to the
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`meaning of a disputed term.” Vitronics, 90 F.3d at 1582. “The construction that stays true to the
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`claim language and most naturally aligns with the patent’s description of the invention will be, in
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`the end, the correct construction.” Renishaw PLC v. Marposs Societa’ per Azioni, 158 F.3d 1243,
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`1250 (Fed. Cir. 1998). The court may also consider the prosecution history of the patent, if in
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`evidence. Markman, 52 F.3d at 980. The prosecution history may “inform the meaning of the
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`claim language by demonstrating how the inventor understood the invention and whether the
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`inventor limited the invention in the course of prosecution, making the claim scope narrower than
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`it would otherwise be.” Phillips, 415 F.3d at 1317 (citing Vitronics, 90 F.3d at 1582-83); see also
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`Chimie v. PPG Indus., Inc., 402 F.3d 1371, 1384 (Fed. Cir. 2005) (“The purpose of consulting the
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`prosecution history in construing a claim is to exclude any interpretation that was disclaimed
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`during prosecution.”) (internal quotations omitted).
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`In most situations, analysis of the intrinsic evidence alone will resolve claim construction
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`disputes, Vitronics, 90 F.3d at 1583; however, a court can further consult “trustworthy extrinsic
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`evidence” to compare its construction to “widely held understandings in the pertinent technical
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`field,” Pitney Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1309 (Fed. Cir. 1999).
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`Extrinsic evidence “consists of all evidence external to the patent and prosecution history,
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`including expert and inventor testimony, dictionaries, and learned treatises.” Markman, 52 F.3d at
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`980. All extrinsic evidence should be evaluated in light of the intrinsic evidence, Phillips, 415
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`F.3d at 1319, and courts should not rely on extrinsic evidence in claim construction to contradict
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`the meaning of claims discernible from examination of the claims, the written description, and the
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`prosecution history, Pitney Bowes, 182 F.3d at 1308 (citing Vitronics, 90 F.3d at 1583).
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`Case 3:18-cv-02848-WHO Document 175 Filed 11/04/19 Page 4 of 24
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`I.
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`THE TECHNOLOGY
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`DISCUSSION
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`The patents at issue aim to improve the design and manufacturability of integrated circuits
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`by creating solutions to manage the lithographic gap. ’352 Patent 1:49-51. Integrated circuit
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`chips are the building blocks of devices like computers, smart phones, and tablets, and transistors
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`are the building blocks of integrated circuit chips. Today, a single integrated circuit chip includes
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`billions of transistors, which form the bottom layer of the chip, connected to the layers above by
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`metal interconnects. Transistors are effectively switches that control the flow of electrical current
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`through a circuit.
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`Transistors are made up of a substrate, a source region, a drain region, and a gate. A
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`semiconductor material forms the substrate. The source and drain regions have the same charge,
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`either positive or negative, which is created by introducing impurities during the fabrication
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`process. The transistor gate can be made of metal or polysilicon. Voltage applied to the transistor
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`gate determines whether a channel forms underneath the gate, allowing charge to flow between the
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`source and drain regions. When the opposite charge is applied to the gate, a current begins to flow
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`through the substrate between the source and drain regions (i.e., the transistor is “on”).
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`Fabrication of integrated circuits occurs one layer at a time, beginning with the bottom
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`transistor layer, known as the front end. To fabricate transistors, different materials are added,
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`altered, and removed until the desired features are present. The Asserted Patents are primarily
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`directed to one tool used during fabrication, called photolithography, or lithography. Lithography
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`is used to create a specific pattern of gates on the substrate. Once the gate material has been
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`deposited onto the substrate, a material called photoresist, which is sensitive to light, is placed on
`top.2 A light is shone through a patterned mask, altering the chemical nature of the photoresist
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`that it reaches and creating the desired pattern. When the photoresist is developed, depending on
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`what type of photoresist was used, either the parts that were exposed to light or the parts that were
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`not exposed to light will remain. The exposed gate material, i.e. without photoresist on top, is
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`2 This account given in this Order does not detail every step involved in semiconductor
`fabrication.
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`Case 3:18-cv-02848-WHO Document 175 Filed 11/04/19 Page 5 of 24
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`chemically etched away, leaving the desired gate pattern. Finally, ashing removes the remaining
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`photoresist.
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`When transistors are too close, they can electrically interfere with one another. With up to
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`billions of transistors on a single chip, they might be separated by only the space of only one one-
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`hundredth of a human hair. Despite this proximity, there are a few ways to prevent transistors
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`from interfering with one another. Dummy gates, which lack source and drain regions, can
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`separate transistors. In addition, field oxide can be used as an insulator to cover the portions of the
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`substrate that do not have active transistors, and gates can be formed on top of the field oxide.
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`At the time of the ’352 Patent, transistor feature sizes had decreased and were approaching
`45 nm (nanometers).3 ’352 Patent 1:27-30. Because those feature sizes are smaller than the
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`wavelength of light, unintended interactions can occur between neighboring features during
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`lithography. See id. at 1:24-27. Specifically, unwanted shapes may be created (constructive
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`interference) or desired shapes may be removed (destructive interference). Id. 1:35-41. The
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`patented technology aims to create a solution “for managing lithographic gap issues as technology
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`continues to progress toward smaller semiconductor device features sizes.” Id. at 1:49-51.
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`II.
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`CLAIM CONSTRUCTION
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`The parties agree on the construction of the following two terms:
`Claim Term
`Agreed Construction
`“diffusion region”
`selected portions of the substrate within which
`impurities have been introduced to form the
`source or drain of a transistor
`plain and ordinary meaning, i.e., a process by
`which a pattern is imprinted on a resist or
`semiconductor wafer using light using a mask
`Joint Claim Construction and Prehearing Statement [Dkt. No. 163] 2. The parties dispute seven
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`“a lithography process”
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`terms, and I construe them as follows.
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`3 Also at the time of the ’352 Patent, improvement in chemical mechanical polishing (CMP)
`allowed more interconnect layers to be stacked together. Id. at 1:21-23. The topology of the
`different interconnect layers can limit how many layers can be stacked together because “islands,
`ridges, and troughs can cause breaks in the interconnect lines that cross them.” Id. at 17:13-22.
`CMP can help flatten the surface of the semiconductor wafer to facilitate stacking. Id. at 17:23-
`28.
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`Case 3:18-cv-02848-WHO Document 175 Filed 11/04/19 Page 6 of 24
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`A. “linear gate electrode segment, linear conductor segment(s), linear conductive
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`segment(s), and (interconnect) linear conductive structures”
`Tela’s Proposal
`Intel’s Proposal
`Court’s Ruling
`a 3D conductive structure
`having a consistent vertical
`extending in a single
`having a rectangular shape of
`cross-section shape and
`direction over the substrate
`a given width defined in a
`extending in a single
`plane parallel to a top surface
`direction over the substrate
`of the substrate and defined to
`have a length that extends in
`one direction
`ʼ352: 1, 17; ʼ966: 2, 31, 33; ’012: 2, 8, 11, 13, 28
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`The parties first dispute the term “linear,” which is found in the ’352, ’966, and ’012
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`Patents. Tela argues that “linear” is to be defined and understood from the top-down view, while
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`Intel counters that it should be understood in terms of a cross-section view. Because the claims
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`themselves do not support the limitation Intel seeks to place on the term, nor does the specification
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`clearly do so, I agree with Tela’s position on the term “linear.”
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`1.
`The plain and ordinary meaning of the claim language
`I begin by analyzing the language of the claims themselves. Claim 2 of the ’966 Patent
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`reads in part, “wherein the gate electrode level region includes a plurality of linear conductive
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`segments each formed to have a respective length and a respective width as measured parallel to
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`the substrate region . . . .” ’966 Patent 27:45-48. Claim 2 of the ’012 Patent reads, “wherein the
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`gate electrode level region includes a plurality of linear conductive segments each formed to have
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`a respective length and a respective width as measured parallel to the substrate region . . . .” ’012
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`Patent 33:3–6.
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`This language shows—and the parties agree—that “linear” at the very least means free of
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`bends on the x-y axis. Op’g 10; Resp. 11. Indeed, that is the plain and ordinary meaning of the
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`term: a straight line. According to Tela, this understanding is enough to construe the term
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`because “linear” is properly understood according to the x-y axis, from the top-down view.
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`Because the patents are directed to layout files, and features in a layout file are defined from a top
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`view, this term too should be understood from the top view. See Liu Decl. Ex. 7, Declaration of
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`Daniel Foty (“Foty Decl.”) [Dkt. No. 166-8] ¶ 83 (asserting that the patentee used “linear” from
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`Case 3:18-cv-02848-WHO Document 175 Filed 11/04/19 Page 7 of 24
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`the top view).
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`The difficulty with construing this term arises from the fact that—despite the patents’
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`focus on the x- and y-axes rather than the z-axis—“linear features” are three-dimensional. The
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`specifications of the Asserted Patents do not describe or represent linear features only from the top
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`view, although Tela rightly points out that most figures show that perspective. See Reply 3. But
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`the patents do include and describe some three-dimensional figures. Because the claim language
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`does not expressly address the z-axis of linear-shaped features, it is necessary to review the
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`intrinsic evidence to determine whether it clearly communications anything about the z-axis. My
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`review of the intrinsic evidence is guided by this admonition from the Federal Circuit:
`[E]ven where a particular structure makes it ‘particularly difficult’ to
`obtain certain benefits of the claimed invention, this does not rise to
`the level of disavowal of the structure. It is likewise not enough that
`the only embodiments, or all of the embodiments, contain a particular
`limitation. We do not read limitations from the specification into
`claims; we do not redefine words. Only the patentee can do that. To
`constitute disclaimer, there must be a clear and unmistakable
`disclaimer.
`Thorner v. Sony Computer Entm’t Am. LLC, 669 F.3d 1362, 1366–67 (Fed. Cir. 2012) (internal
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`citation omitted).
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`2.
`The intrinsic evidence
`The specification serves as “the single best guide to the meaning of a disputed term.” See
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`Phillips, 415 F.3d at 1315. The specification of the patents at issue primarily discusses linear
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`features by reference to the x and y directions. For example, the ’352 Patent reads, “It should be
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`appreciated that the linear-shaped feature may be oriented to have its length 305 extend in either
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`the first reference direction (x), the second reference direction (y), or in diagonal direction defined
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`relative to the first and second reference directions (x) and (y). . . . Also, it should be understood
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`that the linear-shaped feature is free of bends, i.e., change in direction, in the plane defined by the
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`first and second reference directions.” ’352 Patent 9:4–9, 14–17.
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`Case 3:18-cv-02848-WHO Document 175 Filed 11/04/19 Page 8 of 24
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`One part of the specification of the ’352 Patent provides:
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`The dynamic array is defined such that layers (other than the diffusion
`region layer 203) are restricted with regard to layout feature shapes
`that can be defined therein. Specifically, in each layer other than the
`diffusion region layer 203, only linear-shaped layout features are
`allowed. A linear-shaped layout feature in a given layer is
`characterized as having a consistent vertical cross-section shape
`and extending in a single common direction over the substrate.
`Thus, the linear-shaped layout features define structures that are on-
`dimensionally varying.
`’352 Patent 7:1–10 (emphasis added). Although Intel relies on this language to support its
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`proposed construction, the language does not carry the dispositive weight Intel assigns to it. First,
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`it is telling that the description specifically omits the diffusion region from the requirement that
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`only linear-shaped features are allowed. The arrows below point to the diffusion region.
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`’352 Patent, Figure 6. As is clear in the image above, the diffusion region does not run in a
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`straight line on the x-y axis; instead, it has bends and direction changes. By contrast, the darker
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`gate electrode features are linear—they run in straight, parallel lines.
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`It is not completely clear that the consistent-cross-section description above is limited to
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`Case 3:18-cv-02848-WHO Document 175 Filed 11/04/19 Page 9 of 24
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`just one embodiment, and Intel argues that following language shows that it applies broadly to all
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`linear-shaped features: “The specific configurations and associated requirements of the linear-
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`shaped features in the various layers 207-223 are discussed further with regard to FIGS. 3-15C.”
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`’352 Patent 7:23-26. Intel argues that with this language, the specification expands the cross-
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`sectional definition to apply to all of the figures. I disagree. That language instead serves to
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`clarify that other embodiments of linear-shaped features will have different “associated
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`requirements”; they will not necessarily be required to have a consistent cross-sectional shape.
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`Next Intel contends that Figures 3C and 3D support its construction because those figures
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`show three-dimensional features with consistent cross-sectional shapes. But the specification
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`describes these figures as “exemplary linear-shaped feature[s]” that are “defined to be compatible
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`with the dynamic array, in accordance with one embodiment of the present invention.” ’352
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`Patent 8:58–60, 9:18–20. Accordingly, the figures are limited to just one embodiment.
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`In addition, the
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`specification clarifies that
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`while Figures 3C and 3D have rectangular and trapezoidal cross-sections, “it should be understood
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`that the linear shaped features having other types of cross-sections can be defined within the
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`dynamic array.” Id. at 9:45–49 (emphasis added). Indeed, “essentially any suitable cross-
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`sectional shape of the linear-shaped feature can be utilized so long as the linear-shaped feature
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`is defined to have a length that extends in one direction . . . .” Id. at 9: 49–52 (emphasis
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`added). I agree with Tela that this language shows that “irrespective of the cross-sectional shape,
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`the defining characteristic of a linear feature is whether its length extends in one direction in an x-
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`y plane and has consistent width (i.e., free of bends).” See Op’g 13–14. While all linear features
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`in that embodiment must have a consistent cross-sectional shape, that shape is not limited to a
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`rectangle or a trapezoid as long as it is consistent across the feature. Figures 3C and 3D are
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`accompanied by arrows that point in the x and y directions rather than the z direction, confirming
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`that the x-y plane is the focus.
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`Figures 101A, 101B, and 101C, while showing rectangular shapes, do not support Intel’s
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`construction for a two reasons. First, they are limited to a single embodiment. See ’966 Patent
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`11:28-31 (“FIG. 1 is an illustration showing a number of neighboring layout features and a
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`representation of light intensity used to render each of the layout features, in accordance with one
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`embodiment of the present invention.”). Second, they are layout features in a mask used during
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`the lithography process rather than three-dimensional conductive structures. See id. at 11:31-34
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`(“Specifically, three neighboring linear-shaped layout features (101A-101C) are depicted as being
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`disposed in a substantially parallel relationship within a given mask layer.”). These figures do not
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`support Intel’s argument that all linear features necessarily have consistent cross-sections.
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`The patents’ description of some benefits of the dynamic array, on the other hand, do seem
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`to favor Intel’s proposed construction. The dynamic array architecture aims in part to achieve
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`substantially uniform topologies in order to facilitate the stacking of more interconnect layers, to
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`improve the effectiveness of the CMP procedure, and to reduce the unpredictability of light
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`interaction during lithography. ’352 Patent 17:13-18:49; see Foty Decl. ¶¶ 75-77. As the
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`specification lays out the difficulties of these processes, widely varying topologies would prevent
`the realization of these benefits.4 But this is not enough to support the narrowing of the claim
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`language that Intel proposes. See Thorner, 669 F.3d at 1366–67 (“[E]ven where a particular
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`4 Tela notes the difficulty of achieving a uniform topology: “A skilled artisan would understand
`that, in such a standard CMOS process, as features traverse across the substrate, there will be
`variations in the cross-sectional shape, particularly when traversing across shallow trench isolation
`regions.” Reply 4.
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`structure makes it ‘particularly difficult’ to obtain certain benefits of the claimed invention, this
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`does not rise to the level of disavowal of the structure.”). As Tela argued at the hearing, the
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`primary benefit of the technology is related to lithography, and those benefits are realized by
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`placing layout features in a mask in a way that makes light interactions more predictable. See ’352
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`Patent 18:32-35 (“The regular architecture implemented within the dynamic array allows the light
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`interaction unpredictability in the via lithography to be removed . . . .”).
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`The plain meaning of “linear” is a straight line. As Tela argued at the hearing, depth is
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`simply not a defining characteristic of the technology claimed in the patents. Intel’s proposed
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`construction would improperly limit otherwise broad claim language. Because Tela indicated at
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`the hearing that it was comfortable with the second half of Intel’s proposal, and because I
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`conclude that its wording would be more helpful to the jury, I adopt the following construction of
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`linear: “extending in a single direction over the substrate.”
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`B. “gate structure(s) and gate electrode feature(s)”
`Court’s Ruling
`Tela’s Proposal
`Intel’s Proposal
`feature comprising a gate(s)
`feature that can form a gate(s)
`linear-shaped feature
`of a transistor(s) or a dummy
`of a transistor(s) defined
`comprising a gate(s) of a
`gate
`below the gate contact
`transistor(s) or a dummy gate
`ʼ334: 1, 2, 4, 10, 20, 22; ʼ335: 1, 2, 4, 10, 20, 22; ’523: 1, 2, 4, 10, 18, 22, 26
`The parties next dispute the terms “gate structure” and “gate electrode feature,” which are
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`found in the ’334, ’335, and ’523 Patents. There are three main disputes here. First is the question
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`of whether to define these terms as being “linear-shaped features.” To support its proposal that the
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`structures should be construed as linear, Intel relies on specification language that describes a
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`“rectangular shape,” arguing that the specification was referring to rectangular cross-sections.
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`Resp. 14-15. I cannot agree. Not only does Intel’s argument depend on my acceptance of its
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`construction of linear—which I rejected—but the claims themselves provide no indication that
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`gate structures/ gate electrode features must be linear. It would be improper to impose this new
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`requirement during claim construction.
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`The parties next dispute how to communicate the fact that gate structures/electrode features
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`can, but may not necessarily, form the gate of a transistor. If gate structures/electrode features do
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`not cross an active portion of the substrate, no transistor is formed; in other words, the gate is a
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`Case 3:18-cv-02848-WHO Document 175 Filed 11/04/19 Page 12 of 24
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`dummy gate. Below is Figure 5 from the ’334 Patent, which Tela excerpts and annotates in its
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`Opening Brief.
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`The parties substantially agree, but I will adopt Intel’s proposal for three reasons. First, I
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`agree with Intel that the language “comprising” is more accurate. A single gate structure can form
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`one or more transistor gates without its entirety being a transistor gate, as Tela’s annotations above
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`acknowledge. Second, I agree with Intel’s critique that Tela’s language improperly suggests that
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`dummy gates “can form a gate(s) of a transistor(s).” See Resp. 16. Instead, dummy gates are
`incapable of forming the gate of a transistor because they lack a source or drain.5 In addition, even
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`within the same gate electrode feature/ gate structure, some parts are not capable of forming a
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`transistor because they are not above diffusion regions. Third, importantly, Tela does not dispute
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`that the term “dummy gate” is an inaccurate way to describe the portions of a gate structure/ gate
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`electrode contact that do not form transistor gates.
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`Finally, Tela seeks a construction that would require gate electrode features / gate
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`5 Intel further notes, “To the extent Tela’s construction means ‘[does or does not] form a gate of a
`transistor,’ this language is meaningless and imposes no limitation at all—everything on earth
`does or does not form a gate of a transistor.” Resp. 16.
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`Case 3:18-cv-02848-WHO Document 175 Filed 11/04/19 Page 13 of 24
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`structures to be defined below the gate contact, while Intel argues that dummy gates are generally
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`not defined below a gate contact. I agree with Intel. Figure 6 of the ’352 Patent shows two
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`dummy gates (the dark rectangles on the right-hand side), neither of which is below a gate contact
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`(labeled as 601).
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`To the extent that there is a contact gate, it should be defined as above the gate it contacts—but
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`because some gate structures/ gate electrode features do not have associated gate contacts, it does
`not make sense to include that requirement as part of their construction.6 See Resp. 16 (“Thus,
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`while it makes sense to define a gate contact as above the gate that it contacts—as Intel does in
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`Section III.D—it does not make sense to define a gate structure as below a contact that may or
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`may not exist.”).
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`6 If Tela’s proposal defined gate structures/ gate electrode features as below the layer of gate
`contacts, perhaps its construction would be appropriate. But given the singular construction—
`“the gate contact”—despite the absence of gate contacts with some gate structures/ gate electrode
`features, Tela’s proposal is not precise.
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`Case 3:18-cv-02848-WHO Document 175 Filed 11/04/19 Page 14 of 24
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`Intel’s Proposal
`a portion of the conductive
`shape in the gate layer that
`extends over and parallel with
`a diffusion region to form a
`transistor gate
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`C. “gate electrode”
`Tela’s Proposal
`portion of the [linear gate
`electrode segment (’352
`Patent) / linear conductive
`segment (’966 and ’012
`Patents) / gate structure (’334
`and ’335 Patents) / gate
`electrode feature (’523
`Patent)] used to control the
`flow of electrical current
`between the source and drain
`regions of a transistor
`’352: 1, 16, 17; ’966: 2; ’012: 2 , 8, 11, 13; ’334: 1, 4, 22; ’335: 1, 4, 22; ’523: 1, 4, 22, 26
`The parties next dispute the term “gate electrode,” which is found in all six patents at issue.
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`Court’s Ruling
`a portion of the conductive
`shape that extends over the
`diffusion region and is used
`to control the flow of
`electrical current between the
`source and drain regions of a
`transistor
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`The parties dispute (i) whether to construe gate electrode as extending over and parallel with a
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`diffusion region and (ii) whether to describe its structure (as forming a transistor gate) or its
`function (as controlling the flow of electrical current).7
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`At the hearing, Tela generally expressed agreement that the gate electrode extends over the
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`diffusion region, and language in the patents supports this understanding. See ’352 Patent at
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`Abstract (“Each linear gate electrode track . . . extends over . . . a diffusion region . . . .”); ’966
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`Patent at Abstract (providing that the “diffusion region layout shapes to be formed within a portion
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`of a substrate . . . a gate electrode level above the portion of the substrate”); id. at 8:20-29
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`(describing “gate electrode portions which exte