Trials@uspto.gov
`571-272-7822
`
`Paper 36
`Entered: December 1, 2021
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________
`
`MICRON TECHNOLOGY, INC.,
`Petitioner,
`v.
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`____________________
`
`IPR2020-01007
`Patent 6,424,041 B1
`____________________
`
`
`Before JUSTIN T. ARBES, DAVID C. MCKONE,
`and AMBER L. HAGY, Administrative Patent Judges.
`
`MCKONE, Administrative Patent Judge.
`
`
`JUDGMENT
`Final Written Decision
`Determining All Challenged Claims Unpatentable
`35 U.S.C. § 318(a)
`
`
`
`
`
`
`
`

`

`IPR2020-01007
`Patent 6,424,041 B1
`
`I.
`INTRODUCTION
`A. Background and Summary
`Micron Technology, Inc. (“Petitioner”) filed a Corrected Petition
`(Paper 7, “Pet.”)1 requesting inter partes review of claims 1–17 of
`U.S. Patent No. 6,424,041 B1 (Ex. 1001, “the ’041 patent”). Pet. 1. Godo
`Kaisha IP Bridge 1 (“Patent Owner”) filed a Preliminary Response (Paper 9,
`“Prelim. Resp.”). Pursuant to our authorization (Paper 10), Petitioner filed a
`Preliminary Reply (Paper 11) and Patent Owner filed a Preliminary
`Sur-reply (Paper 12). Pursuant to 35 U.S.C. § 314, we instituted this
`proceeding. Paper 15 (“Dec.”).
`Patent Owner filed a Patent Owner’s Response (Paper 20,
`“PO Resp.”), Petitioner filed a Reply to the Patent Owner’s Response
`(Paper 24, “Reply”), and Patent Owner filed a Sur-reply to the Reply
`(Paper 29, “Sur-reply”). An oral argument was held in this proceeding on
`September 15, 2021. Paper 35 (“Tr.”).
`We have jurisdiction under 35 U.S.C. § 6. This Decision is a final
`written decision under 35 U.S.C. § 318(a) as to the patentability of claims 1–
`17. Based on the record before us, Petitioner has proved, by a
`preponderance of the evidence, that claims 1–17 are unpatentable.
`
`
`
`1 Petitioner filed an original Petition in this proceeding as Paper 1. The
`parties jointly requested that Petitioner be permitted to file a corrected
`Petition deleting certain material to remedy an alleged violation of the
`maximum word count. Given the parties’ agreement, we authorized the
`filing of the corrected Petition by e-mail on July 28, 2020. See Ex. 1026
`(redline comparison between the original Petition and corrected Petition).
`
`2
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`IPR2020-01007
`Patent 6,424,041 B1
`B. Related Matters
`The parties indicate that the ’041 patent has been asserted in Godo
`Kaisha IP Bridge 1 v. Micron Technology, Inc., Case No. 6:20-cv-00178
`(W.D. Tex.2) (“the Texas case”). Pet. 5; Paper 5, 1. Petitioner also has filed
`petitions for inter partes review of two other patents in IPR2020-01008 and
`IPR2020-01009. Pet. 5; Paper 5, 1. The patents challenged in those two
`petitions also are asserted in the Texas case. Pet. 5. The ’041 patent
`previously was challenged in Intel Corp. v. Godo Kaisha IP Bridge 1,
`IPR2018-00664. Pet. 5. A panel of the Board instituted a trial in that
`proceeding. Ex. 1004. It later was terminated due to settlement. Ex. 1005;
`Pet. 5.
`
`C. The ’041 Patent
`The ’041 patent describes semiconductor devices designed to prevent
`copper from diffusing from wiring into memory storage regions. Ex. 1001,
`Abstract. The patent explains that, as demand has increased for smaller
`semiconductor devices, aluminum wiring has been replaced with copper
`wiring, which has reduced electrical resistance, power consumption, and
`heat generation. Id. at 1:10–34. On the other hand,
`copper atoms have a property of easily diffusing into silicon
`and a silicon oxide film. Therefore, a copper bridge is formed
`between copper wires, causing short-circuit thereof. Moreover,
`the copper atoms get into an active region of the silicon
`substrate, resulting in unsatisfactory characteristics and
`malfunctioning.
`
`
`2 We refer to the United States District Court for the Western District of
`Texas, Waco Division, as “the Texas court.”
`
`3
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`IPR2020-01007
`Patent 6,424,041 B1
`Id. at 1:35–40. The patent describes a solution employing a “copper
`diffusion blocking means provided in a region surrounding the memory
`storage portion for blocking copper diffusion from the wiring portion toward
`the memory storage portion.” Id. at 2:60–63. Figure 1, reproduced below,
`illustrates an example:
`
`
`Figure 1 is a cross-sectional view of a semiconductor device. Id. at 5:66–67.
`As shown in Figure 1, a semiconductor device includes substrate 1
`and is divided into memory cell portion 30 and peripheral circuit portion 40.
`Id. at 7:2–5. The semiconductor device also includes wiring layer region 50
`that includes insulating film 15 and copper wires 16a, 16b formed in
`insulating film 15. Id. at 7:16–19.
`As to memory cell portion 30, the ’041 patent states:
`Gates 4 and source/drain regions 17 with the corresponding
`gate interposed therebetween are formed in the memory cell
`portion 30. A lift pad 8 is formed on each source/drain region
`17. A bit-line contact and bit line 9a are formed on the lift pads
`
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`IPR2020-01007
`Patent 6,424,041 B1
`8 that are not connected to a capacitor. A capacitor 12 is
`provided on the other lift pads 8 with respective capacitor
`contacts 11 interposed therebetween.
`Id. at 7:5–12. Patent Owner contends that gates 4 and source/drain regions
`17, together, form an access transistor that controls charge entering and
`leaving capacitor 12. PO Resp. 6–9 (citing Ex. 1001, 3:24–30, 7:3–12).
`Between memory cell portion 30 and wiring layer region 50 is ceiling
`film 14, formed from a non-conductive silicon nitride (Si3N4) film.
`Ex. 1001, 7:25–26. According to the ’041 patent, “[t]his ceiling film is
`located away from the copper wires, i.e., at a position where the driving
`force for copper diffusion is small. Therefore, even a slight amount of
`copper diffusion can be prevented.” Id. at 7:26–30. The patent also explains
`that
`
`[c]opper-diffusion preventing films 9b and 13b extending like a
`vertical wall are formed at the boundary between the memory
`cell portion 30 and peripheral circuit portion 40 so as to
`surround the side surface of the memory cell portion. This
`vertical-wall-like copper-diffusion preventing films 9b and 13b
`are formed from a tungsten film.
`Id. at 7:39–45. According to the patent, “[t]he ceiling film 14 and vertical
`walls 9b and 13b block diffusion of copper atoms from the copper wires 16,
`so that copper atoms no longer reach the capacitors 12 of the memory cells
`even in a slight amount.” Id. at 8:3–6.
`Claim 1, reproduced below, is illustrative of the claimed subject
`matter:
`
`A semiconductor device, comprising:
`1.
`a semiconductor substrate,
`a memory storage portion on a main surface of said
`semiconductor substrate,
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`IPR2020-01007
`Patent 6,424,041 B1
`a wiring portion including a copper wire positioned on
`the main surface of said semiconductor substrate
`and apart from said memory storage portion, and
`copper-diffusion blocking means provided in a region
`surrounding the memory storage portion for
`blocking copper diffusion from said wiring portion
`toward said memory storage portion.
`
`Date
`
`July 1995
`
`Exhibit
`No.
`1006
`
`
`
`D. Evidence
`Petitioner relies on the references listed below.
`Reference
`
`Ryan
`
`Liang
`
`J.G. Ryan et al., The evolution of
`interconnection technology at IBM,
`VOL. 39, NO. 4, IBM J. RES. DEVELOP.
`371–81
`US 6,368,952 B1
`
`El-
`Kareh
`
`Kishii
`
`B. El-Kareh et al., The evolution of
`DRAM cell technology, VOL. 40, NO. 5,
`SOLID STATE TECHNOLOGY 89–101
`JP H5-198769
`
`Apr. 9,
`2002
`(filed
`Aug. 15,
`2000)
`May 1997
`
`Aug. 6,
`1993
`
`1009
`
`1010
`
`10133
`
`
`Petitioner also relies on the Declaration of John Bravman, Ph.D.
`(Ex. 1003, “Bravman Decl.”) and the Reply Declaration of Dr. Bravman
`(Ex. 1029, “Bravman Reply Decl.”).
`Patent Owner relies on the Declaration of Kelin Kuhn, Ph.D.
`(Ex. 2027, “Kuhn Decl.”).
`
`3 We refer to Exhibit 1013, a certified translation of the Japanese language
`publication of Exhibit 1012.
`
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`IPR2020-01007
`Patent 6,424,041 B1
`E. The Asserted Grounds
`We instituted on the following grounds of unpatentability (Dec. 7):
`Reference(s)
`Basis
`Claims Challenged
`§ 103(a)5
`1–12, 15–17
`
`Liang4
`
`Liang, El-Kareh
`
`Kishii, Ryan
`
`
`
`§ 103(a)
`
`§ 103(a)
`
`13, 14
`
`1–17
`
`
`4 Petitioner also asserts that each of its grounds is “in view of the knowledge
`of a person of ordinary skill in the art.” Pet. 6–7. As explained in the
`Institution Decision, we do not include the general knowledge of a person of
`ordinary skill in the art in listing the grounds themselves, recognizing that
`such knowledge is considered in every obviousness analysis. See Dec. 7 n.4;
`35 U.S.C. § 311(b) (inter partes review “only on the basis of prior art
`consisting of patents or printed publications”); Koninklijke Philips N.V. v.
`Google LLC, 948 F.3d 1330, 1337 (Fed. Cir. 2020) (“Although the prior art
`that can be considered in inter partes reviews is limited to patents and
`printed publications, it does not follow that we ignore the skilled artisan’s
`knowledge when determining whether it would have been obvious to modify
`the prior art. . . . Regardless of the tribunal, the inquiry into whether any
`‘differences’ between the invention and the prior art would have rendered
`the invention obvious to a skilled artisan necessarily depends on such
`artisan’s knowledge.”); Randall Mfg. v. Rea, 733 F.3d 1355, 1362–63 (Fed.
`Cir. 2013) (“[T]he knowledge of [an ordinarily skilled] artisan is part of the
`store of public knowledge that must be consulted when considering whether
`a claimed invention would have been obvious.”); Dow Jones & Co. v.
`Ablaise Ltd., 606 F.3d 1338, 1349 (Fed. Cir. 2010) (“[The obviousness]
`analysis requires an assessment of the . . . ‘background knowledge possessed
`by a person having ordinary skill in the art.’” (citing KSR, Int’l Co. v.
`Teleflex Inc., 550 U.S. 398, 401 (2007))).
`5 The Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284
`(2011) (“AIA”), amended 35 U.S.C. § 103. Because the ’041 patent has an
`effective filing date before the effective date of the relevant provision of the
`AIA, we cite to the pre-AIA version of § 103.
`
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`IPR2020-01007
`Patent 6,424,041 B1
`
`II. ANALYSIS
`
`A. Claim Construction
`We construe a claim
`using the same claim construction standard that would be used
`to construe the claim in a civil action under 35 U.S.C. 282(b),
`including construing the claim in accordance with the ordinary
`and customary meaning of such claim as understood by one of
`ordinary skill in the art and the prosecution history pertaining to
`the patent.
`37 C.F.R. § 42.100(b) (2019); see also Phillips v. AWH Corp., 415 F.3d
`1303 (Fed. Cir. 2005) (en banc).
`In the Institution Decision, we preliminarily construed “a wiring
`portion . . . apart from said memory storage portion,” as recited in claim 1, to
`mean “a copper wire that ‘is not a part of’ or ‘not a component of’ the
`memory storage portion.” Dec. 30–31. The parties do not challenge that
`construction in their papers filed after the Institution Decision, and we
`maintain that construction on the complete record.
`Below, we discuss constructions proposed by the parties for “memory
`storage portion” and “copper-diffusion blocking means,” both recited in
`claim 1. Based on the record before us, we do not find it necessary to
`provide express claim constructions for any other terms. See Nidec Motor
`Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013, 1017 (Fed.
`Cir. 2017) (noting that “we need only construe terms ‘that are in
`controversy, and only to the extent necessary to resolve the controversy’”)
`(quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803
`(Fed. Cir. 1999)).
`
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`IPR2020-01007
`Patent 6,424,041 B1
`1. “memory storage portion”
`Claim 1 recites “a memory storage portion on a main surface of said
`semiconductor substrate.” Petitioner did not propose a construction for this
`term in the Petition. In the Preliminary Response, Patent Owner contended
`that a “memory storage portion” is “a portion of a semiconductor device that
`includes at least a storage element (e.g., a capacitor) and access circuitry
`(e.g., a transistor) that together form a memory.” Prelim. Resp. 17. We
`authorized further briefing, in which Petitioner contended that a “memory
`storage portion” is “the region where at least the components that are used
`for the storage of information are located.” Reply 1 n.1. In the Institution
`Decision, we agreed with Petitioner that “‘memory storage portion’ refers to
`components that are used to store information, and need not include access
`circuitry.” Dec. 26. Patent Owner requested rehearing of our Institution
`Decision, continuing to press its arguments on the construction of “memory
`storage portion.” Paper 17, 10–14. We denied the rehearing request.
`Paper 19, 9–12. The parties continue to dispute this limitation in the post-
`institution briefing.
`The primary dispute is whether a “memory storage portion” must
`contain more than just the element that stores information (in the context of
`a dynamic random access memory (DRAM) cell, a capacitor) and, in
`particular, whether it must contain “access circuitry” (in the context of a
`DRAM cell, a transistor).
`Petitioner contends that “memory storage portion, “[b]y its very
`words, . . . requires only the ‘portion’ of a ‘memory’ that ‘stores.’ It does
`not require any of the other components needed to operate as a complete
`‘memory,’ or the components needed to access the memory’s storage
`component.” Reply 3. Consistent with Petitioner’s statement, the plain
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`meaning of “memory storage portion” only requires a portion of a
`semiconductor device that stores information. The words used in the claim
`do not suggest additional components such as access circuitry.
`Patent Owner contends that “memory storage portion” has no
`established ordinary meaning outside the ’041 patent. PO Resp. 20, 32.
`Instead, Patent Owner relies heavily on the Specification to support its
`proposal. PO Resp. 20. Apart from the claims, the term “memory storage
`portion” is used primarily in the “Summary of the Invention” section of the
`Specification. The “Background of the Invention” and “Description of the
`Preferred Embodiments” sections primarily use related, but different, terms,
`such as “memory cell portion” and “memory storage region” in describing
`the background art and preferred embodiments.
`The Summary of the Invention provides the clearest indication as to
`what “memory storage portion” means, stating as follows:
`The memory storage portion as used herein mainly indicates a
`memory storage portion of the type that stores information
`corresponding to presence/absence of charges. However, the
`present invention is not limited to this. Semiconductor devices
`for storing information corresponding to presence/absence of
`charges include a DRAM (Dynamic Random Access Memory),
`EPROM (Erasable Programmable Read Only Memory)
`including a flash memory, EEPROM (Electrically Erasable
`Programmable Read Only Memory), and charge-transfer
`sequential access memory. When copper gets into the memory
`storage portion of this type, the amount of accumulated charges
`therein is significantly varied. In other words, such
`semiconductor devices are highly sensitive to copper as
`impurities. Semiconductor devices having the highest copper
`sensitivity include a DRAM for storing information
`corresponding accumulated charges in a capacitor. The
`DRAM stores 1-bit information according to presence/absence
`of accumulated charges in a capacitor provided for each
`transistor. More specifically, in the DRAM, capacitors in a
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`IPR2020-01007
`Patent 6,424,041 B1
`memory cell portion, i.e., in the memory storage portion, share
`the information storage function.
`Ex. 1001, 3:9–30 (emphases added).
`We take from this description that a memory storage portion is the
`part of a semiconductor device that stores information corresponding to the
`presence or absence of electrical charge. Id. at 3:9–11. A DRAM is an
`example of a semiconductor device that would include a memory storage
`portion, but is not the only semiconductor device within the scope of the
`invention. Id. at 3:12–18. In other words, a memory storage portion is not
`limited to a portion of a DRAM, such as a DRAM memory cell, and could
`be a portion of a different type of semiconductor memory device. However,
`in a DRAM cell, the portion that stores information according to
`accumulated charges is a capacitor. Id. at 3:22–30. There is no description
`in this passage suggesting that access circuitry stores information. Rather,
`information is stored “in a capacitor provided for each transistor.” Id. at
`3:26–27. In general, this description supports Petitioner’s position that a
`memory storage portion is the region of a semiconductor device where at
`least the components that are used for the storage of information are
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`located—in the context of a DRAM semiconductor device, the region where
`the capacitor is located.6
`Patent Owner argues that the Specification’s use of “i.e.” is
`definitional in that the Specification equates “memory cell portion” to
`“memory storage portion,” at least in the context of DRAM. PO Resp. 36–
`37 (citing Ex. 1001, 3:7–29), 50–51 (“The specification explains the
`memory cell portion is (‘i.e.,’) ‘a memory storage region’ (7:1–10), and
`DRAM capacitors in a memory cell portion are (‘i.e.,’) ‘in the memory
`storage portion’ (3:7–29).”). We do not read the Specification to equate or
`define a memory storage portion as a memory cell portion. Rather, the
`Specification states that a capacitor that is “in a memory cell portion” of a
`DRAM is “in the memory storage portion” and that such a capacitor
`“share[s] the information storage function.” Ex. 1001, 3:27–30. This does
`not suggest that other components of a memory cell also must be included in
`
`
`6 Patent Owner argues that “Petitioner intends its construction to cover just a
`DRAM capacitor (‘capacitors only’) and to exclude a DRAM’s access
`transistor.” PO Resp. 49–50 (citing Paper 11, 3); see also id. at 25, 52;
`Sur-reply 29 (“The Reply (at 7–8) ignores that the patent never
`limits/equates/defines [memory storage portion] as just a ‘capacitor.’”). This
`is a mischaracterization of Petitioner’s proposed construction. Petitioner
`contends that “the correct construction is ‘the region where at least the
`components that are used for the storage of information are located.’”
`Paper 11, 1 n.1. Thus, Petitioner argues that a memory storage portion is the
`portion that includes at least the storage elements (e.g., a capacitor), not that
`it contains only the storage elements, or that it is otherwise limited to “just a
`‘capacitor.’” The arguments to which Patent Owner points simply contend
`(correctly) that the Specification, at 5:26–43, describes a capacitor as
`sufficient to be a memory storage portion, not that a memory storage portion
`is coextensive with a capacitor. Paper 11, 1–2. In any case, we do not limit
`our construction of “memory storage portion” to just a storage element, such
`as just a capacitor.
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`the memory storage portion, although it does not preclude other components
`from being in the memory storage portion, either. Rather, this passage is
`consistent with the memory storage portion being the portion of a
`semiconductor device that stores information.
`The Summary of the Invention in the Specification also provides as
`follows:
`In the semiconductor device of the present invention, the
`memory storage portion may be, for example, a memory
`storage portion for accumulating and releasing charges
`according to information.
`The memory storage portion for accumulating and releasing
`charges according to information includes a memory cell
`portion of the DRAM. The DRAM accumulates and releases
`the charges in and from capacitors so as to store 1-bit
`information per capacitor. These capacitors are highly
`conveniently formed at a high density. By providing the
`copper-diffusion preventing film, the conveniently formed
`high-density capacitors can be used as memory cells in a
`dimensionally shrunk semiconductor device having the benefits
`of copper wiring. Moreover, since a flash memory such as
`EPROM and EEPROM also accumulates and releases charges
`to store information according to presence/absence of the
`charges, the same effects as those of the DRAM can be
`obtained.
`Ex. 1001, 5:26–44 (emphases added). Here, the Specification describes a
`memory storage portion in terms of storing information by accumulating and
`releasing electrical charge from capacitors, and does not suggest a
`requirement that a transistor or other access circuitry be included in the
`memory storage portion. The Specification states that high-density
`capacitors can be used as memory cells, without mention of the circuitry that
`might be used to control or access those capacitors. Id. at 5:37–38. This
`further suggests that the information storage element of a cell (in DRAM,
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`the capacitor) is the pertinent “portion” of the semiconductor device to
`consider in interpreting “memory storage portion.”
`Patent Owner argues that the Specification’s description at 5:31–33 is
`“explicit” that when the semiconductor device is a DRAM, the memory
`storage portion includes a DRAM memory cell portion. PO Resp. 21–22;
`see also id. at 23 (“‘[M]emory storage portion’ must be construed to cover at
`least a complete DRAM memory cell, which Petitioner’s expert conceded
`includes a capacitor and transistor.”), 34 (“The specification confirms a
`DRAM’s ‘memory storage portion . . . includes a memory cell portion of the
`DRAM’ (5:31–33), which indisputably comprises a capacitor and a
`transistor.”), 35–36, 38–39 (“The specification is clear that the ‘memory
`storage portion. . . includes a memory cell portion of the DRAM,’ which
`includes transistors 4/17 in FIG. 1.”), 50 (“[T]he specification expressly
`states that the claimed ‘memory storage portion’ of a DRAM includes a
`DRAM memory cell, which Petitioner’s expert concedes includes a
`transistor as well as a capacitor.”), 51 (“[The Specification] discloses that for
`a DRAM, the ‘memory storage portion’ surrounded by the blocking means
`includes at least one entire DRAM memory cell (including a capacitor and
`transistor), not a DRAM capacitor alone as Petitioner alleges.”); Sur-reply
`30 (“[T]he intrinsic evidence is clear that for a DRAM, the [memory storage
`portion] includes at least a full memory cell.”). In these arguments, Patent
`Owner is reading “includes” to mean that a memory storage portion must at
`least have all components of the preferred embodiment DRAM memory cell,
`specifically a capacitor and an access transistor. PO Resp. 22 (“[T]he
`intrinsic evidence is explicit that ‘memory storage portion . . . includes’ a
`DRAM memory cell (5:31–33), and thus the ‘memory storage portion’
`includes transistors as well as capacitors.”).
`
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`Patent Owner argues that, in the context of a DRAM, we are not
`permitted to read “memory storage portion” to be broader than the
`components described as part of the ’041 patent’s DRAM memory cell,
`which has a capacitor and an access transistor. Id. at 22 (Patent Owner “asks
`the Board to follow Federal Circuit law (e.g., the above-cited Indacon,
`Honeywell and Profoot cases) requiring ‘memory storage portion’ be
`construed consistent with the specification and not ‘broader’ given this term
`had no known meaning.”).7 In other words, Patent Owner argues that, if the
`semiconductor device is a DRAM, the claimed memory storage portion must
`at least have the capacitor and transistor shown in the DRAM memory cell
`depicted in Figure 1 of the ’041 patent. Patent Owner argues that it is not
`limiting “memory storage portion” to a DRAM memory cell; however,
`Patent Owner “focuses on the DRAM embodiment because the construction
`of ‘memory storage portion’ must be consistent with that ‘preferred’
`(Ex. 1001, 6:63–9:52) embodiment.” Id. at 50–52. Similarly, Patent Owner
`argues that Petitioner’s construction, which does not require access circuitry,
`is “impermissibly inconsistent with the specification’s above-cited
`disclosure (e.g., 5:31–33), which makes clear the ‘memory storage portion’
`of a DRAM includes the ‘memory cell portion’ (i.e., a capacitor and a
`transistor).” Id. at 25.
`
`
`7 At PO Response page 20, Patent Owner cites Indacon, Inc. v. Facebook,
`Inc., 824 F.3d 1352, 1357 (Fed. Cir. 2016) (claim terms “hav[ing] no plain
`or established meaning . . . ordinarily cannot be construed broader than the
`disclosure in the specification”); Honeywell Int’l Inc. v. Universal Avionics
`Systems Corp., 488 F.3d 982, 991 (Fed. Cir. 2007) (“Without a
`customary meaning of a term within the art, the specification usually
`supplies the best context for deciphering claim meaning.”); and Profoot, Inc.
`v. Merck & Co., 663 F. App’x 928 (Fed. Cir. 2016).
`
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`We disagree with Patent Owner’s reading of the word “includes” in
`the Specification at 5:26–43. The Specification describes a DRAM memory
`cell as an example included within the scope of a memory storage portion,
`not as a minimum set of structural features that must be part of any memory
`storage portion. Ex. 1001, 5:31–33. In other words, a DRAM memory cell
`is an example of a memory storage portion, as it is a portion of a DRAM
`device that stores information in the form of electrical charge in a capacitor.
`This passage does not place a limitation on “memory storage portion” such
`that the memory storage portion of a DRAM device is coextensive with or
`limited to the DRAM memory cell described as the preferred embodiment.
`See Phillips, 415 F.3d at 1313 (“[A]lthough the specification often describes
`very specific embodiments of the invention, we have repeatedly warned
`against confining the claims to those embodiments.”); Reply 7 (“[T]he
`passage states that the structure discussed is an ‘example,’ and thus
`unsurprisingly, the specification says that memory storage portion ‘includes’
`this example. There is no limiting definition of ‘memory storage portion.’”).
`This is consistent with our preliminary ruling, in the Institution Decision,
`that “[t]his description states that a memory storage portion may be a portion
`for accumulating and releasing charges according to information and, in an
`example, could be a memory cell portion of a DRAM,” but that “[n]othing in
`this description, however, limits a memory storage portion to the memory
`cell portion of a DRAM or requires that a memory storage portion include
`access circuitry.” Dec. 23.
`Patent Owner repeatedly argues that the preferred embodiment shown
`in Figure 1 of the ’041 patent includes a memory cell portion with both a
`capacitor and an access transistor. PO Resp. 21 (citing Ex. 1001, 7:3–12),
`23 (citing Ex. 1001, 7:1–12), 26 (citing Ex. 1001, 7:1–5), 35–36 (citing
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`Patent 6,424,041 B1
`Ex. 1001, 7:5–7), 50 (citing Ex. 1001, 7:1–10), 52 (citing Ex. 1001, 7:1–7).
`Petitioner concedes that the Specification “does include an embodiment,
`shown in Figure 1, where both a DRAM storage capacitor and an access
`transistor are part of a ‘memory cell portion 30’ located within a copper-
`diffusion blocking means,” but argues that “this does not equate ‘memory
`cell portion’ with ‘memory storage portion.’” Reply 6 (citing Ex. 1001, 7:2–
`7, Fig. 1).
`The portion of the Specification Patent Owner relies on reads as
`follows:
`(Embodiment 1)
`In FIG. 1, trench separation bands 2 are formed at a surface of a
`semiconductor substrate 1, and a memory cell portion 30, i.e., a
`memory storage region, and a peripheral circuit portion 40 are
`provided. Gates 4 and source/drain regions 17 with the
`corresponding gate interposed therebetween are formed in the
`memory cell portion 30. A lift pad 8 is formed on each
`source/drain region 17. A bit-line contact and bit line 9a are
`formed on the lift pads 8 that are not connected to a capacitor.
`A capacitor 12 is provided on the other lift pads 8 with
`respective capacitor contacts 11 interposed therebetween.
`Ex. 1001, 7:1–12. Here, rather than using the term “memory storage
`portion,” the Specification describes “a memory cell portion 30, i.e., a
`memory storage region.” Id. at 7:3–4.
`Patent Owner appears to argue that the terms “memory storage
`portion,” “memory cell portion,” and “memory storage region” are
`synonymous, and that this would support the argument that a memory
`storage portion must have all components of a DRAM memory cell.
`PO Resp. 50–51 (“The specification explains the memory cell portion is
`(‘i.e.,’) ‘a memory storage region’ (7:1–10), and DRAM capacitors in a
`memory cell portion are (‘i.e.,’) ‘in the memory storage portion’ (3:7–
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`Patent 6,424,041 B1
`29).”). In the Institution Decision, we noted that similar arguments revealed
`an attempt by Patent Owner to read this preferred embodiment into the
`claims. Dec. 23–24; see also Paper 19, 11 (noting that Patent Owner asked
`us to “conditionally read the preferred embodiment (a DRAM) into the
`claims whenever we are evaluating prior art that describes a DRAM”).
`Petitioner argues that Patent Owner still attempts to read this embodiment
`into the claims. Reply 5–6. We agree that Patent Owner’s Response
`argument appears to be at odds with its repeated assertion that it is not
`advocating limiting “memory storage portion” to memory cell portion 30
`described as a preferred embodiment. PO Resp. 6, 45–47, 51, 54.
`Despite that “memory cell portion” and “memory storage region” are
`used somewhat interchangeably in the Specification’s Description of the
`Preferred Embodiments, nothing in the ’041 patent suggests that the two
`terms are the same or that either one should be equated to “memory storage
`portion” recited in the claims. Figure 1 is a depiction of “Embodiment 1,”
`and is not intended to be commensurate in scope with the invention.
`Ex. 1001, 5:66–67. As explained above, a memory cell is merely an
`example of a memory storage portion. Id. at 5:31–33. Thus, memory cell
`portion 30, sometimes also referred to as memory storage region or (yet
`another similar term) “memory cell region 30,” is a non-limiting example of
`a memory storage portion. Nothing in the description of the preferred
`embodiments limits a memory storage region to the specific components
`described and depicted for memory cell region 30.
`In response to Petitioner’s arguments that a capacitor is the element in
`a DRAM that stores information, Patent Owner argues that access circuitry
`(a transistor) also is used to store information. According to Patent Owner,
`“[a] transistor (e.g., 4/17 in FIG. 1) is part of the ‘portion’ of a DRAM that
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`stores information.” PO Resp. 28 (citing Ex. 2027 ¶ 74). Dr. Kuhn testifies
`that access circuitry is part of the portion of a DRAM that stores information
`because it is “commonly used to represent the technology used to read-from
`and write-to the storage element (e.g., the capacitor).” Ex. 2027 ¶ 74.
`Patent Owner argues that “[w]hen a bit of information is written to the
`memory cell, the access transistor controls the storing of charge on the
`capacitor so the cell (capacitor and transistor) can store the bit of
`information.” PO Resp. 24–25 (citing Ex. 2027 ¶¶ 82–83; Ex. 2029, 202:1–
`5, 251:13–20).
`Patent Owner argues that “‘[a]ccess circuitry’ is [a] term of art for a
`component (e.g., DRAM memory-cell transistor) needed to form a memory
`that stores information.” Id. at 33 (citing Ex. 2027 ¶ 86). According to
`Dr. Kuhn, without access circuitry, a DRAM “cannot store information (i.e.,
`it cannot function as memory).” Ex. 2027 ¶ 137. Similarly, Patent Owner
`argues that “[w]ithout its associated transistor, a capacitor cannot store a
`‘bit’ of information.” PO Resp. 36 (citing Ex. 1001, 3:25–27); see also
`id. at 39 (“‘[A]ccess circuitry’ refers to a c