Trials@uspto.gov
`571-272-7822
`
` Paper 31
`Entered: December 6, 2021
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`MICRON TECHNOLOGY, INC.,
`Petitioner,
`v.
`GODO KAISHA IP BRIDGE 1,
`Patent Owner.
`
`IPR2020-01008
`Patent 6,445,047 B1
`
`
`
`
`
`
`
`
`
`Before JUSTIN T. ARBES, DAVID C. McKONE, and AMBER L. HAGY,
`Administrative Patent Judges.
`ARBES, Administrative Patent Judge.
`
`JUDGMENT
`Final Written Decision
`Determining All Challenged Claims Unpatentable
`35 U.S.C. § 318(a)
`
`INTRODUCTION
`I.
`A. Background and Summary
`Petitioner Micron Technology, Inc. (“Petitioner”), filed a Petition
`(Paper 7, “Pet.”) requesting inter partes review of claims 1–4 of U.S. Patent
`No. 6,445,047 B1 (Ex. 1001, “the ’047 patent”) pursuant to 35 U.S.C.
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`IPR2020-01008
`Patent 6,445,047 B1
`§ 311(a). On December 7, 2020, we instituted an inter partes review as to
`all challenged claims on all grounds of unpatentability asserted in the
`Petition. Paper 10 (“Decision on Institution” or “Dec. on Inst.”). Patent
`Owner Godo Kaisha IP Bridge 1 (“Patent Owner”) subsequently filed a
`Patent Owner Response (Paper 15, “PO Resp.”), Petitioner filed a Reply
`(Paper 18, “Reply”), and Patent Owner filed a Sur-Reply (Paper 22,
`“Sur-Reply”). An oral hearing was held on September 15, 2021, and a
`transcript of the hearing is included in the record (Paper 30, “Tr.”).
`We have jurisdiction under 35 U.S.C. § 6. This Final Written
`Decision is issued pursuant to 35 U.S.C. § 318(a). For the reasons that
`follow, we determine that Petitioner has shown by a preponderance of the
`evidence that claims 1–4 are unpatentable.
`
`
`B. Related Matters
`The parties indicate that the ’047 patent is the subject of the following
`pending district court case: Godo Kaisha IP Bridge 1 v. Micron Technology,
`Inc., Case No. 20-cv-00178 (W.D. Tex.) (“the district court case”).
`See Pet. 5; Paper 5, 1. Petitioner also filed petitions challenging claims of
`other patents asserted in the district court case in Cases IPR2020-01007 and
`IPR2020-01009.
`
`
`C. The ’047 Patent
`The ’047 patent discloses a semiconductor device including two
`different surface-channel-type metal-oxide-semiconductor field-effect
`transistors (MOSFETs) with different threshold voltages. Ex. 1001, col. 1,
`ll. 5–10. According to the ’047 patent, “it is very important to form
`surface-channel-type MOSFETs of multiple types on a semiconductor chip”
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`IPR2020-01008
`Patent 6,445,047 B1
`to enhance performance in a large-scale integration (LSI) system. Id. at
`col. 1, ll. 11–17. The ’047 patent states that it was known to use, in the same
`semiconductor device, MOSFETs in a “logic circuit block” that “enhance
`their driving power by lowering the threshold voltage and increasing the
`saturated current value” and MOSFETs in a “memory cell block” that
`“increase a data retention time by raising the threshold voltage value and
`minimizing the leakage current.” Id. at col. 1, ll. 18–27. Further, to form
`multiple types of surface-channel-type MOSFETs with different threshold
`voltages, it was known to “mak[e] the dopant concentrations in the channel
`regions different by implanting dopant ions at mutually different doses into
`the channel regions.” Id. at col. 1, ll. 47–52. Setting a higher implant dose
`for the memory cell block MOSFET results in a higher threshold voltage.
`Id. at col. 1, ll. 52–57. Also, as gate insulating films become thinner due to
`the need for miniaturization, the dopant concentration needed to realize a
`certain threshold voltage increases. Id. at col. 1, ll. 58–62. The ’047 patent
`discloses that “performance degrades . . . as the dopant concentration in the
`channel region gets higher” due to, for example, increased “leakage current
`flowing through the pn junction.” Id. at col. 1, l. 63–col. 2, l. 12.
`The ’047 patent seeks to solve these problems using a first-surface-
`channel-type MOSFET in a “logic circuit block” “with a threshold voltage
`of a relatively small absolute value” and a second-surface-channel-type
`MOSFET that “controls power to be supplied to the logic circuit block”
`“with a threshold voltage of a relatively large absolute value.” Id. at col. 2,
`ll. 20–24, 58–62. To increase the threshold voltage “without raising the
`dopant concentration,” the second-surface-channel-type MOSFET includes a
`gate electrode “formed out of a refractory metal film made of a refractory
`metal or a compound thereof” (e.g., titanium nitride, tungsten, molybdenum,
`
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`IPR2020-01008
`Patent 6,445,047 B1
`tantalum). Id. at col. 2, ll. 28–48, col. 3, ll. 61–63, col. 6, ll. 46–51. The
`second-surface-channel-type MOSFET also has a thicker gate insulating
`film to “enhance its OFF-state leakage current characteristics” and improve
`storage ability. Id. at col. 3, ll. 4–16.
`Figures 4(a)–4(c) of the ’047 patent are reproduced below.
`
`
`Figures 4(a)–4(c) depict the later steps of a fabrication process for a
`semiconductor device with “a first [n-type metal-oxide-semiconductor
`(NMOS)] transistor . . . formed in a peripheral circuit region on the left side,
`while second NMOS transistors are formed in a memory cell region on the
`right side.” Id. at col. 6, ll. 60–67. The first-surface-channel-type NMOS
`transistor has first gate electrode 207A, which is “made of an n-type
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`IPR2020-01008
`Patent 6,445,047 B1
`polysilicon film” and has “a threshold voltage with a relatively small
`absolute value,” formed on first gate insulating film 206A “with a relatively
`small thickness of 2.5 nm.” Id. at col. 8, ll. 15–20, 26–30. The second-
`surface-channel-type NMOS transistors each have second gate electrode
`218, which is made of a refractory metal (tungsten) and has “a threshold
`voltage with a relatively large absolute value,” formed on second gate
`insulating film 206B “with a relatively large thickness of 5 nm.” Id. at
`col. 8, ll. 20–25, 30–35. P-type doped region 205 in the channel region of
`the second-surface-channel-type NMOS transistors has a “relatively low
`dopant concentration” as compared to p-type doped region 203 of the
`channel region of the first-surface-channel-type NMOS transistor, which has
`a “relatively high dopant concentration.” Id. at col. 7, ll. 6–22, col. 8,
`ll. 36–40.
`
`
`D. Illustrative Claim
`Challenged claim 1 of the ’047 patent is independent. Claims 2–4
`depend from claim 1. Claim 1 recites:
`1. A semiconductor device comprising:
`a first-surface-channel-type MOSFET with a first
`threshold voltage; and
`a second-surface-channel-type MOSFET with a second
`threshold voltage having an absolute value greater than an
`absolute value of said first threshold voltage,
`wherein the first-surface-channel-type MOSFET includes:
`a
`first gate
`insulating
`film
`formed on a
`semiconductor substrate; and
`a first gate electrode, which has been formed out of
`a poly-silicon film formed directly on the first gate
`insulating film, and
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`Patent 6,445,047 B1
`wherein
`includes:
`
`the
`
`second-surface-channel-type MOSFET
`
`a second gate insulating film formed on the
`semiconductor substrate; and
`a second gate electrode, which has been formed out
`of a refractory metal film formed directly on the second
`gate insulating film, the refractory metal film being made
`of a refractory metal or a compound thereof.
`
`
`
`E. Evidence
`The pending grounds of unpatentability in the instant inter partes
`review are based on the following prior art:
`U.S. Patent No. 6,424,016 B1, filed May 23, 1997, issued
`July 23, 2002 (Ex. 1006, “Houston”);
`U.S. Patent No. 6,165,849, filed Dec. 4, 1998, issued
`Dec. 26, 2000 (Ex. 1007, “An”); and
`Fumihiko Yanagawa et al., A 1-µm Mo-Poly 64-kbit MOS
`RAM, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-27,
`NO. 8 (Aug. 1980) (Ex. 1004, “Yanagawa”).1
`Petitioner filed a declaration from John C. Bravman, Ph.D. (Ex. 1003) with
`its Petition and a reply declaration from Dr. Bravman (Ex. 1042) with its
`Reply. Patent Owner filed a declaration from Kelin Kuhn, Ph.D. (Ex. 2004)
`with its Response. Also submitted as evidence are transcripts of the
`depositions of Dr. Bravman (Exs. 2043, 2048) and Dr. Kuhn (Ex. 1041).
`
`
`
`
`
`
`1 When citing non-patent references filed by Petitioner, such as Yanagawa,
`we refer to the page numbers in the bottom-right corner added by Petitioner.
`See 37 C.F.R. § 42.63(d)(2).
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`
`35 U.S.C. §
`
`Reference(s)/Basis
`
`F. Asserted Grounds
`The instant inter partes review involves the following grounds of
`unpatentability:
`Claim(s)
`Challenged
`1, 2, 4
`1, 2, 4
`
`102(b)2
`103(a)
`
`Yanagawa
`Yanagawa3
`
`
`2 The Leahy-Smith America Invents Act, Pub. L. No. 112-29, 125 Stat. 284
`(2011) (“AIA”), amended 35 U.S.C. §§ 102 and 103. Because the
`challenged claims of the ’047 patent have an effective filing date before the
`effective date of the applicable AIA amendments, we refer to the pre-AIA
`versions of 35 U.S.C. §§ 102 and 103.
`3 Petitioner asserts for some of its obviousness grounds that the challenged
`claims would have been obvious over the cited references and the
`“knowledge” or “ordinary knowledge” of a person of ordinary skill in the
`art. See Pet. 9 n.3, 12, 47, 53, 59, 76. As explained in the Decision on
`Institution, we do not include the general knowledge of a person of ordinary
`skill in the art in listing the grounds themselves, recognizing that such
`knowledge is considered in every obviousness analysis. See Dec. on Inst. 7
`n.5; 35 U.S.C. § 311(b) (inter partes review “only on the basis of prior art
`consisting of patents or printed publications”); Koninklijke Philips N.V. v.
`Google LLC, 948 F.3d 1330, 1337 (Fed. Cir. 2020) (“Although the prior art
`that can be considered in inter partes reviews is limited to patents and
`printed publications, it does not follow that we ignore the skilled artisan’s
`knowledge when determining whether it would have been obvious to modify
`the prior art. . . . Regardless of the tribunal, the inquiry into whether any
`‘differences’ between the invention and the prior art would have rendered
`the invention obvious to a skilled artisan necessarily depends on such
`artisan’s knowledge.”); Randall Mfg. v. Rea, 733 F.3d 1355, 1362–63
`(Fed. Cir. 2013) (“[T]he knowledge of [an ordinarily skilled] artisan is part
`of the store of public knowledge that must be consulted when considering
`whether a claimed invention would have been obvious.”); Dow Jones & Co.
`v. Ablaise Ltd., 606 F.3d 1338, 1349 (Fed. Cir. 2010) (“[The obviousness]
`analysis requires an assessment of the . . . ‘background knowledge possessed
`
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`IPR2020-01008
`Patent 6,445,047 B1
`Claim(s)
`Challenged
`3
`1, 2, 4
`3
`
`
`
`35 U.S.C. §
`
`Reference(s)/Basis
`
`103(a)
`103(a)
`103(a)
`
`Yanagawa, An4
`Houston
`Houston, An
`
`II. ANALYSIS
`A. Level of Ordinary Skill in the Art
`In determining the level of ordinary skill in the art for a challenged
`patent, we look to “1) the types of problems encountered in the art; 2) the
`prior art solutions to those problems; 3) the rapidity with which innovations
`are made; 4) the sophistication of the technology; and 5) the educational
`level of active workers in the field.” Ruiz v. A.B. Chance Co., 234 F.3d 654,
`666–667 (Fed. Cir. 2000). “Not all such factors may be present in every
`case, and one or more of them may predominate.” Id.
`Petitioner states that it treats the ’047 patent as having an effective
`filing date of October 26, 1999, and argues that a person of ordinary skill in
`the art at that time would have had “a degree in electrical engineering,
`
`
`by a person having ordinary skill in the art.’” (citing KSR Int’l Co. v.
`Teleflex Inc., 550 U.S. 398, 401 (2007))).
`4 Petitioner includes two sections of its Petition for this ground, asserting
`that claim 3 would have been obvious over Yanagawa, An, and the
`“knowledge of a [person of ordinary skill in the art],” relying on its previous
`arguments that Yanagawa anticipates parent claim 1, Pet. 47–53, and over
`Yanagawa and An, relying on its previous arguments that Yanagawa renders
`obvious parent claim 1, id. at 58–59. As explained in the Decision on
`Institution, we consider these to be a single asserted ground of obviousness
`based on Yanagawa and An, with alternative theories as to how the prior art
`teaches the limitations of parent claim 1. Dec. on Inst. 8 n.6.
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`Patent 6,445,047 B1
`physics, materials science, or a similar discipline, along with [two] years of
`experience in the development, design, or implementation of semiconductor
`devices,” and would have been “aware of and generally knowledgeable
`about the structure and operation of [dynamic random-access memory
`(DRAM)].” Pet. 9, 29 (citing Ex. 1003 ¶¶ 34–37). Patent Owner does not
`address the level of ordinary skill in the art in its Response or Sur-Reply.
`Based on the full record developed during trial, including our review of the
`’047 patent and the types of problems and solutions described in the
`’047 patent and cited prior art, we agree with Petitioner’s assessment of the
`level of ordinary skill in the art and apply it for purposes of this Decision.
`
`
`B. Claim Interpretation
`We interpret the claims of the challenged patent
`using the same claim construction standard that would be used to
`construe the [claims] in a civil action under 35 U.S.C. 282(b),
`including construing the [claims] in accordance with the ordinary
`and customary meaning of such [claims] as understood by one of
`ordinary skill in the art and the prosecution history pertaining to
`the patent.
`37 C.F.R. § 42.100(b) (2019). “In determining the meaning of [a] disputed
`claim limitation, we look principally to the intrinsic evidence of record,
`examining the claim language itself, the written description, and the
`prosecution history, if in evidence.” DePuy Spine, Inc. v. Medtronic
`Sofamor Danek, Inc., 469 F.3d 1005, 1014 (Fed. Cir. 2006). Claim terms
`are given their plain and ordinary meaning as would be understood by a
`person of ordinary skill in the art at the time of the invention and in the
`context of the entire patent disclosure. Phillips v. AWH Corp., 415 F.3d
`1303, 1313 (Fed. Cir. 2005) (en banc). “There are only two exceptions to
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`this general rule: 1) when a patentee sets out a definition and acts as his own
`lexicographer, or 2) when the patentee disavows the full scope of a claim
`term either in the specification or during prosecution.” Thorner v. Sony
`Comput. Entm’t Am. LLC, 669 F.3d 1362, 1365 (Fed. Cir. 2012).
`In its Petition, Petitioner proposed the following interpretation for the
`claim term “surface-channel-type MOSFET”: “a MOSFET (metal-oxide-
`semiconductor field-effect transistor) in which the channel forms near the
`top surface of the semiconductor substrate.” Pet. 15, 18–21. Petitioner also
`stated that the terms “logic circuit block” and “memory cell block” do not
`require express interpretation, but argued that certain structures fall “within
`[the] scope” of each term. Id. at 21–22. Patent Owner disagreed with
`Petitioner’s proposed interpretation of “surface-channel-type MOSFET” in
`its Preliminary Response, but did not propose an alternative interpretation.
`Paper 9, 12–22. Both parties argued that “surface-channel-type MOSFET”
`is a “known term of art.” See Pet. 19; Paper 9, 14.
`In the Decision on Institution, we preliminarily interpreted
`“surface-channel-type MOSFET” to mean “a MOSFET in which the channel
`forms at the surface of the semiconductor substrate, rather than slightly
`under the surface,” and concluded that no other claim terms required express
`interpretation. Dec. on Inst. 24–30. We found that the claims and written
`description of the ’047 patent do not define or otherwise shed light on what
`is meant by the term “surface-channel-type,” and based our interpretation
`primarily on the description of surface-channel and buried-channel
`MOSFETs in a textbook, John Y. Chen, CMOS Devices and Technology for
`VLSI (1990) (Ex. 1014, “Chen”), on which Petitioner relied for its analysis
`in the Petition. See Dec. on Inst. 26–30; Pet. 18–20.
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`Subsequent to that Decision, the district court in the district court case
`construed “surface-channel-type MOSFET” to have its “[p]lain-and-ordinary
`meaning” and stated: “Note for the jury: The channel in a surface-channel-
`type MOSFET is immediately below the MOSFET gate oxide / insulator.”
`Ex. 3004, 2; see Ex. 2027, 61:19–66:10 (Petitioner arguing that the district
`court should adopt the Board’s preliminary interpretation “because it
`precisely tracks what all the parties agree is the proper meaning of the
`surface-channel transistor”).
`Patent Owner in its Response argues that Petitioner’s asserted grounds
`based on Yanagawa fail under either the interpretation Petitioner proposed in
`the Petition or the Board’s preliminary interpretation, but insists “Petitioner
`should be held to demonstrating unpatentability under the Board’s
`construction.” PO Resp. 18–19. Petitioner applies our preliminary
`interpretation. Reply 3 n.1, 11. The parties disagree as to whether
`Yanagawa discloses a “surface-channel-type MOSFET” under our
`preliminary interpretation and as to how Yanagawa should be analyzed to
`determine whether it discloses a “surface-channel-type MOSFET,” but do
`not otherwise dispute our preliminary interpretation or offer any different
`interpretation. See PO Resp. 16–55; Reply 3–20; Sur-Reply 1–23;
`Tr. 47:11–18 (Patent Owner arguing that our preliminary interpretation is
`“correct”); infra Section II.D.2.(b).
`Based on the full record developed during trial, we see no reason to
`deviate from the preliminary interpretation adopted in the Decision on
`Institution, and incorporate our previous analysis herein. See Dec. on Inst.
`24–30. We also note that the district court’s note for the jury is generally
`consistent with our preliminary interpretation, but has a different focus. The
`district court’s note focuses on where the channel forms relative to the gate
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`IPR2020-01008
`Patent 6,445,047 B1
`oxide/insulator (i.e., immediately “below” the gate oxide/insulator), whereas
`our interpretation focuses on where the channel forms relative to the
`semiconductor substrate (i.e., “at the surface” of the semiconductor
`substrate). Claim 1 recites that each of the two surface-channel-type
`MOSFETs has a gate insulating film formed “on” the semiconductor
`substrate; thus, a channel that forms at the surface of the semiconductor
`substrate would be immediately below the gate insulating film. Further,
`dependent claim 2 recites relative dopant concentrations “in the channel
`region” of each surface-channel-type MOSFET. Given the pertinent
`extrinsic evidence cited in the Decision on Institution, particularly the Chen
`textbook, we are persuaded that the focus on where the channel forms
`relative to the recited semiconductor substrate is correct.
`We interpret “surface-channel-type MOSFET” to mean “a MOSFET
`in which the channel forms at the surface of the semiconductor substrate,
`rather than slightly under the surface,” and conclude that no other terms
`require express interpretation to determine whether Petitioner has met its
`burden to prove unpatentability of the challenged claims. See Nidec Motor
`Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013, 1017 (Fed.
`Cir. 2017) (“Because we need only construe terms ‘that are in controversy,
`and only to the extent necessary to resolve the controversy,’ we need not
`construe [a particular claim limitation] where the construction is not
`‘material to the . . . dispute.’” (citations omitted)).
`
`
`C. Legal Standards
`“Anticipation requires that every limitation of the claim in issue be
`disclosed, either expressly or under principles of inherency, in a single prior
`art reference,” Corning Glass Works v. Sumitomo Elec. U.S.A., Inc.,
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`868 F.2d 1251, 1255–56 (Fed. Cir. 1989), and that the claim limitations be
`“arranged or combined in the same way as recited in the claim,”
`Net MoneyIN, Inc. v. VeriSign, Inc., 545 F.3d 1359, 1371 (Fed. Cir. 2008).
`However, “the reference need not satisfy an ipsissimis verbis test,” meaning
`identity of terminology between the prior art reference and the claim is not
`required. In re Gleave, 560 F.3d 1331, 1334 (Fed. Cir. 2009); In re Bond,
`910 F.2d 831, 832–833 (Fed. Cir. 1990). “In an anticipation analysis, the
`dispositive question is whether a skilled artisan would ‘reasonably
`understand or infer’ from a prior art reference that every claim limitation is
`disclosed in that single reference.” Acoustic Tech., Inc. v. Itron Networked
`Solutions, Inc., 949 F.3d 1366, 1373 (Fed. Cir. 2020) (citation omitted).
`Whether a reference anticipates is assessed from the perspective of an
`ordinarily skilled artisan. Finisar Corp. v. DirecTV Group, Inc., 523 F.3d
`1323, 1336 (Fed. Cir. 2008) (“[T]he meaning of a prior art reference requires
`analysis of the understanding of an artisan of ordinary skill.”). “Expert
`testimony may shed light on what a skilled artisan would reasonably
`understand or infer from a prior art reference.” Acoustic, 949 F.3d at 1373;
`accord Dayco Prods., Inc. v. Total Containment, Inc., 329 F.3d 1358,
`1368–69 (Fed. Cir. 2003) (“Typically, testimony concerning anticipation
`must be testimony from one skilled in the art and must identify each claim
`element, state the witnesses’ interpretation of the claim element, and explain
`in detail how each claim element is disclosed in the prior art reference.”
`(citation omitted)).
`A claim is unpatentable for obviousness if, to one of ordinary skill in
`the pertinent art, “the differences between the subject matter sought to be
`patented and the prior art are such that the subject matter as a whole would
`have been obvious at the time the invention was made.” KSR, 550 U.S. at
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`406 (quoting 35 U.S.C. § 103(a) (2006)). The question of obviousness is
`resolved on the basis of underlying factual determinations, including “the
`scope and content of the prior art”; “differences between the prior art and the
`claims at issue”; and “the level of ordinary skill in the pertinent art.”
`Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966). Additionally,
`secondary considerations, such as “commercial success, long felt but
`unsolved needs, failure of others, etc., might be utilized to give light to the
`circumstances surrounding the origin of the subject matter sought to be
`patented. As indicia of obviousness or nonobviousness, these inquiries may
`have relevancy.”5 Id. When conducting an obviousness analysis, we
`consider a prior art reference “not only for what it expressly teaches, but also
`for what it fairly suggests.” Bradium Techs. LLC v. Iancu, 923 F.3d 1032,
`1049 (Fed. Cir. 2019) (citation omitted).
`A patent claim “is not proved obvious merely by demonstrating that
`each of its elements was, independently, known in the prior art.” KSR,
`550 U.S. at 418. An obviousness determination requires finding “both ‘that
`a skilled artisan would have been motivated to combine the teachings of the
`prior art references to achieve the claimed invention, and that the skilled
`artisan would have had a reasonable expectation of success in doing so.’”
`Intelligent Bio-Sys., Inc. v. Illumina Cambridge Ltd., 821 F.3d 1359,
`1367–68 (Fed. Cir. 2016); see KSR, 550 U.S. at 418 (for an obviousness
`analysis, “it can be important to identify a reason that would have prompted
`a person of ordinary skill in the relevant field to combine the elements in the
`way the claimed new invention does”).
`
`
`5 Patent Owner has not presented any evidence of secondary considerations
`of nonobviousness in this proceeding.
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`“Although the KSR test is flexible, the Board ‘must still be careful not
`to allow hindsight reconstruction of references . . . without any explanation
`as to how or why the references would be combined to produce the claimed
`invention.’” TriVascular, Inc. v. Samuels, 812 F.3d 1056, 1066 (Fed. Cir.
`2016) (alteration in original). Further, an assertion of obviousness “cannot
`be sustained by mere conclusory statements; instead, there must be some
`articulated reasoning with some rational underpinning to support the legal
`conclusion of obviousness.” KSR, 550 U.S. at 418 (quoting In re Kahn,
`441 F.3d 977, 988 (Fed. Cir. 2006)); accord In re NuVasive, Inc., 842 F.3d
`1376, 1383 (Fed. Cir. 2016) (stating that “conclusory statements” amount to
`an “insufficient articulation[] of motivation to combine”; “instead, the
`finding must be supported by a ‘reasoned explanation’”); In re Magnum Oil
`Tools Int’l, Ltd., 829 F.3d 1364, 1380 (Fed. Cir. 2016) (“To satisfy its
`burden of proving obviousness, a petitioner cannot employ mere conclusory
`statements. The petitioner must instead articulate specific reasoning, based
`on evidence of record, to support the legal conclusion of obviousness.”).
`
`D. Anticipation Ground Based on Yanagawa (Claims 1, 2, and 4)
`1. Yanagawa
`Yanagawa is an IEEE article describing “a new 1-µm double-gate
`technology using molybdenum and polysilicon (Mo-poly technology).”
`Ex. 1004, 1. “In this technology, molybdenum is used for word lines and
`gate electrodes for MOSFET’s in memory cells. Polysilicon is used for gate
`electrodes for MOSFET’s in peripheral circuitry and storage capacitor
`electrodes.” Id. “Therefore, a high packing density and high-speed MOS
`[random-access memory (RAM)] is realized due to reduction in memory-cell
`size and in word-line propagation delay.” Id.
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`Yanagawa describes a design using “[s]hort-channel Si-gate and
`Mo-gate [field-effect transistors (FETs)].” Id. at 2. “Device parameters for
`1-µm Si-gate FET’s are optimized for peripheral circuitry where high
`performance is required.” Id. “Si-gate FET’s were used [for peripheral
`circuitry] because they have low threshold voltage due to their
`work-function values.” Id. Table I of Yanagawa is reproduced below.
`
`
`Table I lists various parameters and characteristics of the Si-gate and
`Mo-gate transistors, such as B+ dose, gate oxide thickness, and threshold
`voltage.6 Id. at 3. Yanagawa discloses that
`[i]n designing Mo-gate FET’s in memory cell[s], gate
`oxide thickness and effective channel length are important.
`Maximum gate voltage, applied to Mo-gate FET’s in memory
`cells, is 7 V to obtain higher signal level. Therefore, it was
`necessary to increase Mo-gate FET gate oxide thickness to
`
`6 “A voltage greater than the threshold voltage (typically abbreviated [as] Vt)
`inverts the region underneath the gate insulating film (e.g., . . . from p-type
`to n-type) to form a channel region between the source and drain that is
`conductive to allow current to flow between the source and drain regions.”
`Ex. 1003 ¶ 44; see Ex. 1014, 18–19.
`
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`40 nm. To avoid short-channel effect in Mo-gate FET’s, the
`effective channel length was increased to 1.5 µm. . . . Mo-gate
`FET characteristics [shown in Table I] are good enough for
`memory operation, because Mo-gate FET’s are used only in
`memory cells.
`Id. Figure 2 of Yanagawa is reproduced below.
`
`
`
`Figure 2 depicts “memory-cell structures” using the disclosed
`“molybdenum-polysilicon (Mo-poly) technology.” Id. at 1. A “[f]irst-level
`gate of polysilicon is used as the storage capacitor electrode, which does not
`significantly affect word-line delay or speed performance. The word line is
`made of molybdenum, that is, second-level gate.” Id. “These structures also
`provide[] . . . good intermediate insulating layers between two gate
`electrodes and [an] aluminum-molybdenum multilevel interconnection
`system.” Id. at 1–2.
`
`
`
`
`
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`
`2. Claim 1
`Petitioner argues that claim 1 is anticipated by Yanagawa7 under
`35 U.S.C. § 102(b), relying on the testimony of Dr. Bravman as support.
`Pet. 29–42 (citing Ex. 1003). Patent Owner makes various arguments in
`response, relying on the testimony of Dr. Kuhn. PO Resp. 16–55 (citing
`Ex. 2004); Sur-Reply 1–23.
`
`
`a) Undisputed Issues
`Petitioner contends that Yanagawa discloses a “semiconductor
`device” (i.e., MOS RAM) comprising a “first-surface-channel-type
`MOSFET” (i.e., Si-gate transistor) with a “first threshold voltage” (0.5 V)
`and a “second-surface-channel-type MOSFET” (i.e., Mo-gate transistor)
`with a “second threshold voltage” (i.e., 1.3 V) “having an absolute value
`greater than an absolute value of said first threshold voltage,” as recited in
`claim 1. Pet. 29–34. Petitioner provides an explanation as to why the
`Si-gate and Mo-gate transistors are “surface-channel-type MOSFET[s].” Id.
`at 18–21, 23–24, 31–32, 34.
`
`
`
`
`7 The three prior art references at issue in this proceeding (Yanagawa, An,
`and Houston) were not of record during prosecution of the ’047 patent. See
`Ex. 1001, code (56); Pet. 12. Petitioner also provides evidence supporting
`its contention that Yanagawa is a prior art printed publication under
`35 U.S.C. § 102(b). See Pet. 9–11 (citing Exs. 1004, 1005, 1008,
`1025–1037). Patent Owner does not assert otherwise in its Response, and
`we agree that Yanagawa is prior art for the reasons stated by Petitioner.
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`To illustrate how Yanagawa allegedly discloses the various MOSFET
`properties recited in claim 1, Petitioner provides the following annotated
`version of Table I of Yanagawa (id. at 23).
`
`
`
`Annotated Table I above lists various properties of the Si-gate transistor
`(shown in red) and Mo-gate transistor (shown in green), as argued by
`Petitioner. Petitioner argues that the Si-gate transistor includes a “first gate
`insulating film” (i.e., gate oxide film with 30 nm thickness) formed on the
`semiconductor substrate and a “first gate electrode” formed out of a
`“poly-silicon film” directly on top of the first gate insulating film, given that
`the polysilicon gate is formed immediately after forming the gate oxide
`layer. Id. at 35–37. Petitioner further contends that the Mo-gate transistor
`includes a “second gate insulating film” (i.e., gate oxide film with 40 nm
`thickness) formed on the semiconductor substrate and a “second gate
`electrode” formed out of a “refractory metal film” made of a “refractory
`metal” (i.e., molybdenum) directly on top of the second gate insulating film,
`as shown in Figure 2 of Yanagawa. Id. at 37–42.
`
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`Other than the issue of whether Yanagawa’s Si-gate transistor
`constitutes a “first-surface-channel-type MOSFET,” which we address
`below, Patent Owner does not dispute that Yanagawa discloses the
`remaining limitations of claim 1; therefore, any such arguments are waived.
`See Novartis AG v. Torrent Pharms. Ltd., 853 F.3d 1316, 1330 (Fed. Cir.
`2017); NuVasive, 842 F.3d at 1380–81; Paper 12, 8 (“Patent Owner is
`cautioned that any arguments not raised in the response may be deemed
`waived.”). Petitioner’s analysis for each of the limitations discussed above,
`supported by the testimony of Dr. Bravman, which we credit, is persuasive.
`See Pet. 29–42; Ex. 1003 ¶¶ 88–90, 94–106.
`
`b) Disputed Issue: Whether Yanagawa’s Si-Gate Transistor is a
`“Surface-Channel-Type MOSFET”
`The sole issue disputed by Patent Owner pertains to the limitation of
`claim 1 that the semiconductor device have a “first-surface-channel-type
`MOSFET.” Petitioner identifies Yanagawa’s Si-gate transistor as a
`“first-surface-channel-type MOSFET” and Yanagawa’s Mo-gate transistor
`as a “second-surface-channel-type MOSFET,” and explains why the
`transistors are “surface-channel-type.” Pet. 18–21, 23–24, 30–32, 34.
`Petitioner contends that both transistors “are N-MOSFETs, i.e., the
`source/drain regions are n-type and the substrate is p-type,” with the Si-gate
`transistor having a shallow boron (p-type) channel implant and the Mo-gate
`transistor having no channel implant. Id. at 23–24, 31–32 & n.11, 34 & n.12
`(citing Ex. 1004, 2 (discussing “source and drain n+ junction depth” for the