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`
`I 1111111111111111 11111 111111111111111 IIIII IIIII IIIII IIIII 111111111111111111
`
`
`
`
`
`US005459850A
`
`
`United States Patent
`[19]
`Clay et al.
`
`5,459,850
`Patent Number:
`[11]
`
`Date of Patent:
`Oct. 17, 1995
`[45]
`
`[54]FLASH SOLID STATE DRIVE THAT
`EMULATES A DISK DRIVE AND STORES
`VARIABLE LENGTH AND FIXED LENTH
`DATA BLOCKS
`
`Steven A.Donald [75]Inventors: W. Clay, Louisville;
`
`
`
`
`Anderson,
`
`Loveland, both of Colo.
`
`5,274,772
`12/1993 Dunn et al .............................. 395/275
`
`
`5,285,327
`
`
`2/1994 Hetzler ...................................... 360/48
`5,291,584
`
`
`3/1994 Challa et al. ........................... 395/500
`5,293,388
`
`3/1994 Monroe et al. ........................ 371/37.1
`5,293,565
`
`
`3/1994 Jaquette et al. ........................... 369/32
`5,301,304
`
`4/1994 Menon .................................... 395/500
`5,335,328
`
`
`8/1994 Dunn et al .............................. 395/275
`
`Conner Peripherals,
`[73]Assignee:
`Inc., San Jose,
`
`
`
`Calif.
`EDN, Feb. 18, 1993.
`
`"Flash Memory Challenges Disk Drives" by Gary Legg,
`
`OTHER PUBLICATIONS
`
`[21]Appl. No.: 19,860
`
`[56]
`
`
`
`References Cited
`
`Gossage
`Primary Examiner-Glenn
`J. Asta
`Assistant Examiner-Frank
`[22]Filed:Feb. 19, 1993
`
`or Finn-Fliesler, Dubb, Meyer & Lovejoy
`
`Attorney, Agent,
`[51]Int. Cl.6 .............................
`G06F 12/04
`G06F 12/06;
`[57]
`ABSTRACT
`
`[52]U.S. Cl ...................................... 395/497.02;
`371/37.1;
`
`
`
`
`
`
`A flash solid state drive, having a flash solid state memory
`
`
`
`
`364/260.6; 364/260.7; 364/245.1; 364/DIG. 1;
`
`
`
`
`compatible with ATA/IDE Interface standards to be con­
`
`395/442; 395/500
`
`
`
`
`nected to a host for storing or retrieving sectors of data,
`
`
`
`[58]Field of Search ......................... 395/425; 364/260.6,
`
`
`
`
`where each sector contains 512 bytes of data, each sector is
`
`371/37.1 364/260.7, 200 MS, 900 MS, 245.1;
`
`
`
`
`addressed by a cylinder, head and sector number CHS. The
`
`
`host provides, for a read or write operation, the number of
`
`
`
`sectors to be stored or retrieved, the CHS for each sector to
`
`
`
`be stored or retrieved and the data for the sectors to be
`
`
`
`
`stored. The solid state memory has stored therein a header
`
`
`6/1986 Kuroda et al. .......................... 340/347
`4,593,267
`
`
`for each CHS address that can be issued by the host, the
`4,675,809
`
`6/1987 Omoda et al. .......................... 395/400
`
`
`
`
`header having indicia identifying the data block and indi­
`
`8/1990 Bozman .................................. 395/700
`4,947,319
`
`
`cating where the data for the data block is stored in the solid
`
`
`
`............................ 395/425 4,958,315 9/1990 Balch ..........
`
`
`
`state memory. The flash solid state device comprises a
`
`
`7/1991 Osterlund ................................ 395/425
`5,034,914
`
`
`
`translator means for translating the CHS address into a logic
`
`
`12/1991 Tuma et al .............................. 395/500
`5,070,474
`
`
`
`
`sector number LSN for identifying sectors in the flash solid
`7/1992 Cole ........................................ 395/500
`5,131,089
`
`
`
`5,166,686 11/1992 Sugiyama ................................ 341/155
`
`
`
`
`state drive and a controller for converting sectors received
`
`
`12/1992 Hisatake et al. ........................ 358/426
`5,170,263
`
`
`
`
`from the host into variable length sectors to be stored in the
`
`
`4/1993 Yanai et al. ............................. 395/400
`5,206,939
`
`flash solid state memory.
`
`6/1993 Tuma et al. ............................. 395/500
`5,218,691
`
`
`8/1993 Miller et al. ................................ 360/8
`5,237,460
`
`
`9 Claims, 9 Drawing Sheets
`
`
`8/1993 Hannon, Jr . ............................. 395/425
`5,237,675
`
`U.S. PATENT DOCUMENTS
`
`49
`
`FLASH
`MEMORY
`51 27
`
`c!;] Q
`
`IPR2020-01288
`Sony EX1016 Page 1
`
`

`

`U.S. Patent
`Oct. 17, 1995 Sheet 1 of 9
`
`5,459,850
`
`-
`
`- ---
`
`20
`
`-so
`
`' I
`
`' Ir
`
`49�
`
`48
`� STATE MACHINES 10 - 7 -
`1- -SJ'
`BUFFER 13�
`+
`CONTROL &
`REGISTER
`�7 53 -
`DATA
`BUFFER
`MULTIPLEXOR
`-•7_-- -
`11
`12
`-5 9 r58
`ssi t£s �a
`IFIFO 82,
`-57 ECC
`54\ FIFO
`DETECTOR 16
`,._
`14
`HOST
`� ..
`15
`' .
`60
`,I,
`52..1 --63
`,9
`,. ,i, ,, 65
`READ
`SEQ -
`SEL
`..,::z
`INTERFACE 18 : 68�
`61 17
`as.::::::...
`:\64 66�1
`/
`' '
`CONTROL
`67--t
`19 � : COMPRESSOR r--: •
`-FLASH
`.-r+ CONTROLLER
`v-- 70 �
`21
`I I .. CRC 22
`GENERATOR -
`CRC v-71
`r-.f RAM 31 �
`CHECKER
`23 DECOMPRESSOR
`---
`
`, II , I 'II ' •
`
`� v-14
`7�
`, ' ',,, , ,
`
`r76
`
`--
`24
`
`11,-
`
`'.
`
`Q Q
`FLASH
`MEMORY
`27
`
`'.
`
`� Q
`Q Q
`
`69-..._
`� -�
`AT
`ECC
`- REGISTERSGENERATOR --- j ., Ir
`25
`26
`-
`V- 77
`v-78
`1:;:
`ROM RAM
`,,
`- - MICRO
`--
`- : PROCESSOR :. L 81
`28 29
`-
`30 :.72�
`t
`I -= a6�
`so�
`FIG. 1
`
`IPR2020-01288
`Sony EX1016 Page 2
`
`

`

`U.S. Patent Oct. 17, 1995 Sheet 2 of 9
`READ
`
`5,459,850
`
`INPUT CHS (CYCLINDER, HEAD AND
`
`SECTOR) AND SECTOR COUNT
`
`TRANSLATE CHS TO LS N
`
`(LOGICAL SECTOR NUMBER)
`
`SEND STATUS
`INVALID CHS
`
`YES
`READ NEXT SECTOR HEADER AFTER
`LAST STORED READ HEADER
`
`A
`
`.--------
`
`y
`READ HEADER
`ATTRIBUTE WORD
`
`�N_O_....,,
`
`READ OFFSET WORD
`
`.READ SECTOR
`TRANSLATION
`·TABLE FOR LSN
`PFA (PARTIAL
`SEND STATUE
`FLASH ADDRESS)
`SECTOR BAD
`
`SEND STATUS
`LSN NOT FOUND
`
`FIG. 2A
`
`IPR2020-01288
`Sony EX1016 Page 3
`
`

`

`U.S. Patent Oct. 17, 1995
`
`Sheet 3 of 9 5,459,850
`
`FA (FLASH ADDRESS)
`-PFA + APPENDED
`SCAN COUNT
`
`WRITE A SECTOR
`OF ZEROS INTO
`BUFFER
`
`NO
`
`ADD 1 TO
`SCAN COUNT
`
`WRITE A SECTOR
`OF COMPRESSED
`ZEROS INTO BUFFER
`
`FIG. 28
`
`IPR2020-01288
`Sony EX1016 Page 4
`
`

`

`U.S. Patent Oct. 17, 1995 Sheet 4 of 9 5,459,850
`
`READ SECTOR FROM FLASH
`MEMORY INTO BUFFER AND
`TO ECC DETECTOR
`
`SLOW DOWN ACCES
`AND RETRY READ
`
`NO
`
`NO
`
`YES
`
`TRY ERROR CORRECTION
`ROUTE SECTOR DAT
`
`DIRECTLY TO HOST
`
`.ROUTE SECTOR DATA
`THROUGH DECOMPRESSOR
`FLAG ERROR TO HOST
`TO THE HOST
`
`NO
`
`ROUTE SECTOR DATA
`TO CRC CHECKER
`
`YES-----------.
`>--� FLAG CRC ERROR TO HOST
`
`FIG. 2C
`
`IPR2020-01288
`Sony EX1016 Page 5
`
`

`

`U.S. Patent Oct. 17, 1995 Sheet 5 of 9 5,459,850
`
`WRITE
`
`INPUT CHS (CYCLINDER, HEAD AN
`
`SECTOR) AND SECTOR COUNT
`
`TRANSLATE CHS TO LSN
`
`(LOGICAL SECTOR NUMBER)
`
`SEND STATUS
`INVALID CHS
`
`YES
`
`ROUTE SECTOR
`
`DIRECTLY TO .,.._-<
`BUFFER
`
`ROUTE SECTOR YES
`BACK THROUGH
`DECOMPRESSOR
`TO BUFFER
`
`NO
`
`ROUTE
`SECTOR
`"">--1� THROUGH
`COMPRESSO
`TO BUFFER
`
`ROUTE SECTO
`THROUGH CRC
`GENERATOR
`
`CRC BYTE TO
`BUFFER
`
`SET SECTOR
`SET SECTOR
`ATTRIBUTE AS
`ATTRIBUTE AS
`UNCOMPRESSED
`COMPRESSED
`
`FIG. 3A
`
`IPR2020-01288
`Sony EX1016 Page 6
`
`

`

`Oct. 17, 1995 Sheet 6 of 9 5,459,850
`U.S. Patent
`
`A
`
`READ NEXT SECTOR HEADER AFTE
`LAST SECTOR MARKED AS DIRTY
`
`YES
`
`.READ SECTOR
`NO TRANSLATION
`TABLE FOR LSN
`PFA (PARTIAL
`FLASH ADDRESS)
`
`NO
`
`YES
`
`FA (FLASH ADDRESS
`-PFA + APPENDED
`SCAN COUNT
`
`SCAN COUNT • 0
`
`MARK
`HEADER
`DIRTY
`
`YE
`
`NO
`
`SEND STATUS
`STANDBY
`
`FIG. 38
`
`IPR2020-01288
`Sony EX1016 Page 7
`
`

`

`U.S. Patent
`Oct. 17, 1995
`
`Sheet 7 of 9
`
`5,459,850
`
`WRITE HEADER AT
`NEXT AVAILABLE
`ADDRESS IN BLOC
`
`UPDATE TRANSLATION TABL
`
`WITH NEW PFA FOR SECTO
`
`FO
`CLEANUP
`
`YES
`
`ALLOCATE INTO NEXT
`AVAILABLE BLOCK
`
`STOP
`
`POINT FLASH WRITE
`WINDOW TO THE
`
`BEGINNING OF THE
`DATA AREA AS
`
`INDICATED BY THE
`OFFESET IN HEADER
`
`CHANNEL SECTOR
`THROUGH ECC
`GENERATOR TO
`FORM ECC DATA
`
`WRITE SECTOR
`FROM BUFFER
`AND ECC DATA
`TO FLASH
`
`FIG. 3C
`
`IPR2020-01288
`Sony EX1016 Page 8
`
`

`

`U.S. Patent Oct. 17, 1995 Sheet 8 of 9
`
`5,459,850
`
`INITIALIZATION
`
`SET PFA FOR ALL SECTORS
`
`IN THE TRASLATION TABLE
`TO ADDRESS FFFF
`
`SET FREE, DIRTY, AND NUMBER
`
`
`OF SECTORS REGISTERS TO 0
`
`READ BAD BLOCK DATA FROM ROM
`
`UPDATE TOTAL FREE
`FLASH IN BLOCK,
`CHIP AND ARRAY
`
`YES
`
`GO TO NEXT BLOCK
`
`YES
`
`READ CYCLE COUN
`TABLE FOR BLOCK
`
`READ NEXT HEADE
`
`MAINTAIN MAXIMUM
`
`CYCLE COUNT
`
`FIG. 4A
`
`IPR2020-01288
`Sony EX1016 Page 9
`
`

`

`U.S. Patent Oct. 17, 1995 Sheet 9 of 9
`
`5,459,850
`
`HEADER
`LSN IN NO
`TRANSLATIO
`TABLE-=
`FFF6
`
`REV#>
`ANSLATI
`LE HEA
`
`YES
`
`.MARK OL
`STORE PFA I
`HEADER
`TRANSLATION
`DIRTY
`TABLE FOR
`HEADER LSN
`
`MARK
`HEADER
`DIRTY
`
`UPDATE TOTAL
`UPDATE TOTAL
`DIRTY IN
`DIRTY IN
`BLOCK & ARRAY
`BLOCK & ARRA
`
`FIG. 48
`
`IPR2020-01288
`Sony EX1016 Page 10
`
`

`

`1
`
`5,459,850
`
`2
`
`FLASH SOLID STATE DRIVE THAT
`EMULATES A DISK DRIVE AND STORES
`VARIABLE LENGTH AND FIXED LENTH
`D ATA BLOCKS
`
`weighed in selecting which solid state memory should and
`
`
`
`BACKGROUND OF THE INVENTION
`
`SUMMARY OF THE INVENTION
`
`
`
`
`
`could be used in a specific design.
`
`
`
`To have a solid state drive emulate a magnetic disk drive,
`
`
`
`the solid state storage media must be transparent to the host.
`
`
`5 Ideally, the solid state drive would accept the same com­
`
`mands and data formats as the magnetic disk drive such that
`
`
`
`
`no change in programming or system configuration need be
`
`
`
`done within the host. A disadvantage associated with most
`1.Field of the Invention
`
`
`
`solid state memories is the time necessary to write into the
`
`
`lO memory. The slow write speed is a major reason why the
`
`
`
`
`The present invention relates to digital data storage sys­
`
`
`tems in general and, in particular, to storage systems
`
`
`solid state drives emulating magnetic disk drives have not
`
`
`
`employing flash solid state memory devices as the storage
`
`
`been more widely accepted and marketed within the indus­
`
`
`
`
`
`media. More particularly still, the invention relates to a flash
`try.
`
`
`solid state memory system that emulates magnetic disk
`drives.
`15
`2.Description of the Related Art
`
`
`Accordingly, it is an object of the invention to provide a
`
`
`
`
`Magnetic disk drives have been widely accepted in the
`
`
`
`
`
`
`
`flash solid state drive which emulates a magnetic disk drive
`
`
`
`
`computer industry and are used for storing large amounts of
`
`and is transparent to the host system.
`
`
`
`
`data. Over the years, magnetic disk drives have decreased in
`20
`
`
`
`Another object of the invention to have a flash solid state
`
`
`size while increasing in operational speed and in the amount
`
`
`
`drive with improved speed for writing and reading data to
`
`of data that can be stored on the magnetic media. Magnetic
`
`and from the flash memory array.
`
`
`
`disk drives have associated with them a seek latency time
`
`
`which is associated with the time necessary to move the
`
`
`
`Another object of the invention is to have the flash solid
`
`
`
`
`desired transducer to the desired track or cylinder on the 25
`
`
`state drive include means for compressing data on a sector
`
`
`
`
`magnetic media for the purpose of recovering or writing data
`
`
`
`
`basis such that sectors of variable lengths are written into
`
`
`to and from the magnetic media. In addition, there is a
`and read from the flash memory array and where the
`
`
`
`
`rotational latency associated with waiting for the desired
`
`
`compression is transparent to the host system.
`
`
`
`data sector to pass underneath the transducer once the
`
`
`
`
`Still another object of the invention to have a flash solid
`
`
`
`
`
`transducer is located on the desired track. Magnetic disk
`
`
`state drive which dynamically allocates space in the flash
`30
`
`
`
`drives also have the associated problems of relying on
`
`
`
`memory array such that sequential sectors to be written need
`
`
`
`mechanical hardware for locating the transducer at a specific
`
`
`not be sequentially located in the flash m�mory array.
`
`
`
`location with regards to the magnetic media and for main­
`
`
`Briefly, the flash solid state drive is 100% hardware and
`
`
`
`taining the rotational speed of the magnetic media at some
`
`
`
`software compatible with ATA/IDE Interface standards and
`
`
`
`
`constant value. The mechanical hardware is affected by the
`
`
`
`
`supports all mandatory AT-Attachment standard commands.
`35
`
`
`normal wear and tear associated with mechanical devices.
`
`
`
`The flash solid state drive includes means for translating the
`
`
`
`
`
`Further, magnetic disk drives have employed various track
`
`
`
`
`cylinder, head and sector address received from the host into
`
`
`
`
`following servo systems for maintaining the transducer on a
`
`
`
`
`translation table is a logical sector number LSN. A sector
`
`
`
`
`desired track once the transducer reaches that desired track.
`
`
`
`
`maintained for providing the physical address in the flash
`
`
`
`
`Finally, the magnetic disk drive tracks are divided into a
`
`
`memory for the header associated with each logical sector
`40
`
`
`
`fixed number of sectors where each sector stores a fixed
`
`
`
`number. The flash memory is comprised of a plurality of
`
`
`
`number of data bytes. As a rule, magnetic disk drive systems
`
`flash memory chips arranged to form a flash memory array
`
`
`
`will write a complete sector each time a sector is written.
`
`
`where two flash chips are paired together to form flash chip
`
`Where the data is less than a full sector the data is padded
`
`
`
`
`pairs which the drive treats as a single addressable unit. A
`
`with zeros to fill up the sector. This is to say that if the sector
`45
`
`
`buffer is provided to receive data from the host and from the
`
`
`
`
`length is 512 bytes, whenever a sector is written 512 bytes
`
`
`
`flash memory. Data received from the host to be stored in the
`
`
`
`of data will be written into that sector. The requirements of
`
`
`
`flash memory may first be passed through a data compres­
`
`
`
`
`writing a full sector every time a sector is written means that
`
`
`
`sion unit and stored as compressed data in the buffer. Data
`
`
`
`
`a substantial portion of the magnetic surface may be allo­
`
`is written from the buffer into the flash memory as data word
`
`
`
`
`
`cated to contain filler data rather than useful data. Finally, it
`
`where a data word is made up of two bytes of data. The 16
`50
`
`
`can readily be realized that the data would also be recovered
`
`
`bits of data in a data word are written in parallel into the flash
`
`
`
`from the magnetic disk drive in sector lengths and, therefore,
`
`
`
`
`memory. Further, the received data, if compressed, is also
`
`
`a full sector must be read from the disk regardless of the
`
`
`
`
`passed through a cycle redundancy code CRC generator and
`
`
`actual amount of useful data that was recorded in that sector.
`
`
`the CRC data is appended to the end of the compressed data
`
`
`
`With the advent of solid state memories, attempts have 55
`
`
`
`
`stored in the buffer. The stored data and the CRC data, if the
`
`
`
`been made to emulate the magnetic disk drives by use of
`
`
`
`data was compressed, is passed through an ECC generator
`
`
`
`solid state memories in place of the magnetic media.
`
`
`
`before being stored in flash memory. The generated ECC
`
`
`Examples of such emulations are found in U.S. Pat. No.
`
`
`data is stored in the flash memory so as to be appended to
`
`
`
`
`4,642,759 entitled "Bubble Memory Disk Emulation Sys­
`the end of the data and CRC data, if any. Data is read from
`
`
`
`tem" and U.S. Pat. No. 5,131,089 entitled "Solid State Disk 60
`the flash memory as a data word (2 bytes at a time) and
`Drive Emulation".
`
`
`stored in the memory buffer as single bytes of data. A read
`
`The ideal system would use a solid state memory that is
`
`sequencer between the flash memory and the buffer changes
`
`
`nonvolatile bubble
`
`the data words in two sequential such as the above-referenced memory or data bytes for storage in the
`
`
`
`the solid state memory with its own power supply to
`
`
`
`
`buffer. The data from the read sequencer is passed through
`maintain the stored data even though power is turned off to
`
`
`
`
`
`
`65 an ECC detector to ascertain if an error has occurred. If an
`
`
`
`error was sensed the drive will try a reread operation at a
`
`
`
`
`
`the drive. However, each of these solid state memories each
`
`
`
`have their own advantages and disadvantages which must be
`
`
`
`slower speed. If the error is not corrected by the reread
`
`IPR2020-01288
`Sony EX1016 Page 11
`
`

`

`5,459,850
`
`4
`3
`Flash memory 27 is comprised of thirty Intel 28F008 flash
`
`
`
`operation, then a ECC correction is attempted to recover
`
`
`
`chips where the chip data size is 8 Mb and 8 bits of data are
`
`from the error. If the error was not corrected, the host is
`
`
`
`simultaneously written into or read from the flash chip. Two
`
`
`notified. If the data was not compressed, the data is chan­
`
`
`
`flash chips are paired together and addressed at the same
`
`neled from the buffer directly to the host. If the data was
`
`
`y 5 time such that 16 bits may be written or read simultaneous!
`
`
`
`
`compressed, the compressed data is routed through a decom­
`
`
`into or from the flash memory. To accomplish this flash
`
`
`
`pression unit and the decompressed data is channeled to the
`
`
`
`
`controller 21 is dual ported so as to provide both address and
`
`
`
`host. The uncompressed data is also routed through a CRC
`data to each flash chip of a chip pair by means of lines 73
`
`
`
`checker and if an error is detected the drive will notify the
`
`
`through 76. The flash solid state drive is controlled by
`
`
`
`host that the channeled data contained an error. The flash
`microprocessor
`
`
`30 in conjunction with an operating program
`
`
`memory is initialized to store a header for each LSN where
`10
`
`
`
`stored in ROM 28. Microprocessor 30 is also connected to
`
`
`the number of LSNs equal the number of sectors that would
`
`
`R AM 29 to allow the dynamic storing of data necessary for
`
`
`have been used in the magnetic disk drive being emulated.
`
`
`
`
`controlling the operation of the drive. Microprocessor 30 is
`
`
`
`
`A new header is written for a sector each time the sector is
`
`
`
`
`conriected to AT registers 25, to interface control circuitry
`
`
`written into the flash memory and the old header associated
`
`
`19, to flash control 21, to data multiplexer 12, to ECC
`
`
`with the same sector is marked as dirty or invalid. Each flash
`
`
`
`15generator 26, to buffer control and registers 13 and to ECC
`
`
`memory chip pair is broken down into blocks where a block
`
`detector 15.
`
`
`is the smallest area that can be erased. Means are provided
`For a write operation, data for a sector is received from the
`
`
`
`
`
`for ascertaining the usage of each block to obtain uniform
`
`
`
`host on bus 9 to interface control 19. If the sector data is to
`
`
`
`usage of blocks throughout the memory array. Blocks are
`
`
`
`be compressed, the sector data is transferred via line 64 to
`
`
`designated as bad if the block has a history of unrecoverable
`20
`
`
`
`compressor 20 for data compression and through CRC
`
`
`
`errors being generated from data read from that block. A bad
`
`
`
`
`generator 22 for generating CRC data. Data compressor 20
`
`
`block table .is maintained and updated in a flash ROM
`
`
`is a LEMPAUZIV type data compressor. The compressed
`
`
`
`associated with the microprocessor controlling the operation
`
`
`
`sector data, after being compressed, is stored in buffer 11.
`of the drive.
`
`
`
`in buffer 11 25 After the compressed sector data has been stored
`
`
`
`An advantage of the flash solid state drive is the increase
`
`the CRC data byte is stored in buffer 11 and made part of the
`in read and write speed to and from the flash memory
`
`
`data associated with the sector being stored.
`
`
`
`
`obtained by the parallel writing and reading of two bytes of
`
`
`If the sector data was not to be compressed, then the sector
`data.
`
`
`data would leave interface control 19 on line 65 and pass
`Another advantage of the flash solid state drive is the
`
`
`
`
`directly through selector 18 , FIFO 14 and data multiplexer
`
`
`increased efficiency obtained by compressing sector data 30
`
`
`
`
`12 into buffer 11. State machines 10 contains a write state
`
`
`
`
`such that variable sector lengths are stored in the flash
`
`
`
`
`
`machine which controls the sequence of operations during a
`memory.
`
`
`
`write operation. Once the data for the sector, either com­
`
`Another advantage is that the flash solid state drive is not
`
`
`
`
`pressed or uncompressed, has been stored in buffer 11, the
`
`subject to the seek and rotational latencies associated with
`
`
`
`
`
`
`the sector data from 35 write state machine will then transfer
`
`
`
`magnetic disk drives and are more reliable in that flash solid
`
`
`data multiplexer 12 to microprocessor 30. Microprocessor
`
`
`
`
`state drives do not have any mechanical components that can
`
`30 act as a dual port microprocessor where the ports are
`wear and fail.
`
`
`connected to data multiplexer 12 by means of buses 57 and
`
`
`
`Another advantage of the flash solid state drive is that the
`
`
`69.When sector data is transferred from buffer 11 to
`
`flash memory is transparent to the host so as not to require
`
`
`
`through 40 microprocessor 30 the sector data is also passed
`
`
`ECC generator 26 to generate the ECC data. The ECC data
`
`
`
`any reprogramming of the host operating system or changes
`
`
`
`
`to physical structure of the host thereby allow the flash solid
`
`
`
`is also provided to microprocessor 30. Microprocessor 30
`
`
`
`state drive to completely emulate the magnetic disk drive
`
`
`
`transfers the sector data and ECC data as data words, where
`
`previously used by the host.
`
`
`each data word consists of two bytes of data,to flash con-
`
`
`
`30 performs the task of taking 45 troller 21. Microprocessor
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`
`two sequential bytes of sector data from buffer 11 or ECC
`
`data and forming data words for flash controller 21. Flash
`
`
`
`The invention will be described with respect to the
`
`
`controller 21 then writes the data word into the flash memory
`
`
`
`
`particular embodiments thereof and references will be made
`
`to the drawings, in which:
`27.
`50 During a read operation, the read command is received
`
`
`FIG. 1 is a logic diagram of the flash solid state drive;
`
`
`from the host on bus 9 by interface control 19. State machine
`
`
`FIGS. 2A through 2C is a flow chart setting forth the
`
`
`
`10 includes a read state machine which controls the
`
`
`operation of the flash solid state drive for a read operation;
`
`
`
`
`sequence of operation during the read procedure. The data is
`
`
`FIGS. 3 A through 3C is a flow chart setting forth the
`
`read from flash memory 27 by flash controller 21 as data
`
`
`
`operation of the flash solid state drive for a write operation;
`
`
`
`55 word format. Read sequencer 17 receives the data word and
`and
`
`
`provides sequentially each of the two bytes of data making
`
`FIGS. 4A and 4B is a flow chart setting forth the operation
`
`
`up the received data word to speed matching buffer FIFO 16.
`
`
`
`of the flash solid state drive to initialize the sector translation
`
`
`Read sequencer 17 also routes the data bytes to ECC
`
`table during the power up sequence.
`
`
`
`detector 15 for the detection of an error in the read data. The
`
`
`
`
`60 output of FIFO 16 is routed through multiplexer 12 to buffer
`DESCRIPTION OF THE PREFERRED
`
`
`11.When the data for a sector has been stored in buffer 11
`
`EMBODIMENTS SYSTEM ARCHITECTURE
`
`
`and no data error was detected by ECC detector 15, the
`
`
`
`FIG. 1 is a logic diagram showing the components of the
`
`
`
`sector data is then directed from buffer 11 through data
`
`flash solid state drive. The flash solid state drive is 100%
`
`
`multiplexer 12 and speed matching buffer FIFO 14 to
`
`
`
`
`hardware and software compatible with ATA/IDE Interface
`
`
`
`65 selector 18. If the sector data was compressed, then the
`
`
`
`standards and will support all mandatory AT-Attachment
`
`
`
`
`sector data is routed from selector 18 through decompressor
`
`standard commands.
`
`
`
`24.The decompressed sector data from decompressor 24 is
`
`
`
`IPR2020-01288
`Sony EX1016 Page 12
`
`

`

`5,459,850
`
`6
`TASK FILE CYLINDER illGH REGISTER
`
`COMMA ND REGISTER
`
`
`
`SECTOR CONFIGURATION REGISTER
`
`
`
`This is a 8 bit register used to determine the sector wrap
`
`HEAD CONFIGURATION REGISTERS
`
`This is a 4 bit register used to determine the head wrap
`
`5
`routed to CRC checker 23 and to interface control 19 for
`
`
`
`
`
`
`
`transmission to the host. If CRC checker 23 detects a CRC
`
`
`
`error, a flag is raised to the host indicating that an error exists
`
`
`in the sector data that was transmitted for that sector. If the
`
`This register is used by the Host to communicate the
`
`
`
`
`
`read sector data was not compressed, selector 18 will route 5
`
`
`
`desired command. When either the Host or the drive write
`
`
`
`the sector data via line 65 to interface control 19 which will
`
`this register, the drive will become busy. When the drive is
`then route the data to the host via bus 9.
`busy, only the drive may write the task file. When the drive
`
`
`
`
`state a between sector State machines 10 also contains
`
`is not busy, only the Host may write the Task File unless the
`machine for updating the task file registers and a byte count
`
`
`
`
`
`
`
`drive writes OD bit 3 to enable the microprocessor access to
`
`
`
`state machine for maintaining of the number of bytes of data
`10
`the Task File registers.
`
`transfer during a read or write operation.
`
`
`
`AT registers 25 and buffer control registers 13 are used to
`
`
`
`
`control the sequence of operation in conjunction with the
`
`
`
`
`
`
`microprocessor performing the operation program as stored
`15 point for the Host values.
`
`in ROM 28 and the operation of the varies state machines.
`
`
`
`
`Buffer control and registers 13 include a tie breaking state
`
`
`
`
`
`machine for to resolve conflicts in the data multiplexer 12
`
`
`
`for access to buffer 11 and a buffer signal state machine for
`
`
`
`
`
`controlling the reading and writing of data into and out of
`20 point for the Host values.
`buffer 11.
`bit 3-Head bit 8
`
`
`
`bit 2-Head bit 4
`
`buffer registers 13 are as follows:
`bit I-Head bit 2
`bit 0-Head bit
`25
`1
`
`The function of and description of the AT registers 25 and
`
`AT REGISTERS
`
`TASK FILE ERROR REGISTER
`
`DIGITAL ADDRESS REGISTER
`
`35
`
`bit 0-Drive 0-
`
`This register is the same as that read at 3F7 by the Host
`
`
`
`
`with the exception that bit 7 is a one instead of tristate as it
`This register is the error indicating register to the Host. It
`
`
`
`30 is to the interface.
`
`
`has bit significance except at power on or during the
`
`
`
`diagnostic command. It is a read only register to the Host.
`bit 7-Always
`1
`bit 7-Bad Block
`bit 6-Always
`1
`bit 6-ECC Data Check
`bit 5-Head bit
`3-
`bit 4-ID Not Found
`bit 4-Head bit
`2-
`
`bit 2-Aborted Command
`bit 3-Head bit 1-
`
`bit I-Track O Not Found
`bit 2-Head bit O­
`
`bit 0-Address Mark Not Found
`bit I-Drive 1-
`
`40
`
`TASK FILE PRECOMP REGISTER
`
`AT CONTROL REGISTER
`
`This register contains status bits for use by the microcode.
`
`This register is a write only register to the Host. I t was
`
`
`
`
`
`
`
`
`previously used to indicate at what cylinder to begin pre­
`It is read only.
`compensation. It is used for other commands at this point in
`
`
`45 7-Sector>maximum logical sector
`
`
`time.
`
`
`
`This bit contains the result of a comparison of
`
`
`the Task File Sector Number register and the Sector
`
`configuration register.
`The register is used by the Host to indicate how many
`
`
`
`
`bit 6-Head>maximum logical head
`50
`
`
`sectors are to be transferred on a read or write command.
`This bit contains the result of a comparison of the Task
`
`
`
`
`File SDH register head value and the Head configuration
`register.
`bit 5-Count equal to 0
`
`to 0.
`bit 4-ECC Error
`This bit is when an ECC error is detected. The ECC is
`
`
`1
`
`
`
`60 should be reset by toggling AT Res 1 in the Microprocessor's
`
`
`reset register before continuing.
`bit 3-Byte count equal to 0
`This bit is one when the transfer count register that counts
`
`
`TASK FILE CYLINDER LOW REGISTER
`
`
`the number of bytes to be transferred on the interface is=0.
`65
`bit 2-IOR & I OW equal to 0
`
`This register and the following register contain the cyl­
`
`
`bit 4-Drive address
`bit 3-Head bit 8
`bit 2-Head bit 4
`bit I-Head bit 2
`bit 0-Head bit 1
`
`TASK FILE COUNT REGISTER
`
`TASK FILE SECTOR REGISTER
`
`TASK FILE SDH REGISTER
`
`55
`
`This bit is 1 when the Task File Count Register is equal
`
`
`
`
`
`inder requested by the Host.
`
`This bit is for use in PCM CIA interfaces. It is 1 when both
`
`IPR2020-01288
`Sony EX1016 Page 13
`
`

`

`5,459,850
`
`This bit sets the Host interrupt which is gated by the Host
`
`TASK FILE STATUS REGISTER
`
`20
`
`INTERFACE CONTROL REGISTER
`
`8
`BIT PULSES REGISTER
`
`7
`
`IOR &IOW are active low at the same time.
`
`
`bit I-Task file update state I
`This register is setup to allow bit operations to be done.
`
`
`
`
`
`This bit and bit O contain the status of the task file update
`
`
`
`When it is read, it always returns FFh. To pulse any of these
`
`
`state machine. It is triggered by the read or write state
`
`bits, a zero is written.
`
`
`machines and normally should not be able to be seen 5
`
`bit 7-Set Host IRQ.
`
`
`
`
`changing. It should always be in state 00.
`
`
`
`bit 0-Task file update state 0
`
`interrupt enable.
`
`bit 6-Reset Long.
`This reset is used to reset the Long bit, set by the Host
`10
`
`when it does either a read or write long.
`
`
`bit 5-Reset Read/Write Mode.
`This register which is a read/write register used to access
`
`
`
`
`This bit resets both read and write modes and the Data
`
`
`
`
`the Task File register which provides a summary status of
`
`Request bit.
`
`the drive. All bits are read/write.
`bit 4-Set Read Mode.
`15
`bit 7-Busy
`This bit sets read mode. It is the only bit required to kick
`
`bit 6-Ready
`
`
`off a read operation if all other initialization has been
`
`bit 5-Write Fault
`accomplished.
`bit 4-Seek Complete
`
`bit 3-Continue R/W.
`bit 3-Data Request
`This bit is used when the sector automation is disabled,
`
`
`
`bit 2-Corrected data
`
`
`register OD bit 4 set to 0. to allow the next sector to begin.
`
`bit 2-Increment Block Release
`bit I-Index
`
`This is the drive side pulse used to increment the Sectors
`bit 0-Error bit
`
`25 Available Register.
`35 on a read and to decrement it on a
`
`write.
`bit I-Increment Transfer Release.
`
`
`
`This is the Host side pulse used to decrement the Sectors
`bit 7-Host PDIAG Out
`
`
`it on a Available Register. 35 on a read and to increment
`
`write.
`30
`This bit, when set to 1, drives the Host PDIAG signal
`
`active low. It is bit settable.
`bit 0-Set Write Mode.
`Used to set Write Mode. This bit is used by the micro­
`
`bit 6-LED/Drive Slave Present
`
`
`
`processor to start any non-autowrite write operation.
`
`
`
`This bit, when set to 0, drives the DASP signal low to the
`interface.
`35
`bit 5-Processor Host Interrupt Enable
`
`
`This is a collection of bits that are useful for interface
`
`
`This bit may be set to 1 to force the Host interrupt to be
`operation.
`
`enabled. It should be reset to allow the Host to enable or
`
`
`bit 7-Host IRQ.
`
`disable the drive's interrupt.
`This is the Host IRQ bit just before it goes to the output
`bit 4-0K to continue
`40 drivers.
`
`
`This bit is used by the processor to allow a multiple sector
`
`bit 6-Host Interrupt Enable.
`
`
`
`read or write to continue. Normally it should be set to 1 at
`
`
`
`
`
`
`
`initialization. If sector automation is to be inhibited, this bit
`
`the output drivers.
`
`
`
`should be set to zero. Then, between sectors, the bit pulse,
`bit 5-Host PDIAG In.
`
`the R/W. 45
`CONTINUE R/W OE, bit 3, is pulsed to continue
`This bit comes from the PDIAG line just on the input side
`
`
`
`bit 3-Enable microprocessor access to the Task File
`of the Host input receivers.
`Registers.
`bit 4-Long
`
`
`
`
`This bit is used by the processor to enable it to access the
`This bit is the long bit set by the Host when it does either
`
`Task File even when the drive is not busy. Normally, this bit
`a read or write long operation.
`50
`is not ever used.
`bit 3-HI016
`bit 2-INDEX.
`This is the HIOI6 line just before it goes to the Host
`
`
`
`
`This bit is routed to the status register to simulate the
`interface.
`
`
`index of a drive. For the flash drive it should not be needed.
`
`bit 2-Write Mode
`55
`bit I-C-/D.
`The Write mode latch.
`The address bit of the drive. It is set to 0 for drive C or
`
`
`bit I-Read Mode
`0 and to 1 for drive I or D. This bit is used to route status
`
`
`and is compared to the bit in the SDH register to determine
`The Read Mode latch.
`
`the addressed drive.
`
`
`bit 0-Drive Slave Present In.
`60
`
`bit 0-Slave Present.
`
`
`This bit is used to indicate that a second drive is present.
`
`
`
`
`
`
`It is set during a reset sequence when dual drive is detected.
`
`
`
`It is used to route status because if the second drive is not
`This register and the following three registers are the
`
`
`
`
`
`
`
`
`to return 00 65 present, the master drive, drive 0, is responsible
`
`
`
`registers where the ECC Generator I result is stored. To
`
`
`
`
`for status. Setting this bit allows the hardware to return this
`
`
`
`
`
`produce the correct ECC value, the registers should be
`status.
`
`
`
`before the data is initialized to F0, OF, 00, FF respectively
`
`INTERFACE BITS REGISTER
`
`This is the Host Interrupt Enable bit just before it goes to
`
`The drive slave present line at the input receiver lines.
`
`
`
`ECC I GENERATION 4
`
`IPR2020-01288
`Sony EX1016 Page 14
`
`

`

`5,459,850
`
`
`
`ECC 1 GENERATION 3
`
`
`
`ECC 1 GENERATION 2
`
`
`
`ECC 1 GENE