I 1111111111111111 11111 111111111111111 lllll 111111111111111 1111111111 11111111
`
`US006904484 B 1
`
`(12)United States Patent
`
`
`Nelson
`
`US 6,904,484 Bl
`
`(10)Patent No.:
`
`Jun.7,2005
`(45)Date of Patent:
`
`
`
`5,784,611 A * 7/1998 Thantrakul ..................... 713/1
`
`
`
`
`
`(54)LOW PIN COUNT (LPC) FIRMWARE HUB
`RECOVERY
`
`
`
`
`
`6,188,602 Bl * 2/2001 Alexander et al. .. ... 365/185.04
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`6,291,976 Bl * 9/2001 Kaminski et al. ........... 323/283
`
`
`
`(75)Inventor:
`(US)
`
`
`
`Albert Rudy Nelson, Olympia, WA
`
`(73)Assignee: Intel Corporation,
`
`Santa Clara, CA
`(US)
`
`
`6,442,067 Bl * 8/2002 Chawla et al. ... ... ... 365/185.08
`
`
`710/126 2001/0018721 Al * 8/2001 McKenna et al. ..........
`
`
`
`
`709/201 ........... et al. 2002/0184297 Krancher Al * 12/2002
`
`
`
`
`709/250 et al. .......... 2003/0023761 Al * 1/2003 Jeansonne
`
`( *) Notice: Subject to any disclaimer, the term of this
`
`
`
`* cited by examiner
`
`
`
`patent is extended or adjusted under 35
`
`U.S.C. 154(b) by O days.
`
`(21)Appl. No.: 09/539,517
`
`Primary Examiner---Rupal Dharia
`
`
`
`
`(74)Attorney, Agent, or Firm-Paul E. Steiner
`
`(22) Filed:Mar. 30, 2000
`
`ABSTRACT
`(57)
`
`
`................................................ G06F 13/00 (51)Int. Cl.7
`
`A method and apparatus for low pin count firmware hub
`
`....................... 710/300; 710/305; 710/104; (52)U.S. Cl.
`
`
`
`
`
`recovery on a circuit board having a firmware hub includes
`
`713/1; 365/185.8; 365/185.11; 365/185.33
`
`
`
`coupling a firmware hub recovery module having a firmware
`(58)Field of Search .........................
`
`710/104, 300-304,
`
`
`
`
`program onto the circuit board, establishing communication
`
`
`
`710/305-317; 713/1; 365/185.08, 185.11,
`185.33
`
`
`between a central processing unit (CPU) and the firmware
`
`
`hub recovery module, and reprogramming the firmware hub
`
`by the firmware program.
`
`(56)
`
`
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`
`
`
`
`
`22 Claims, 3 Drawing Sheets
`
`
`
`5,600,801 A * 2/1997 Parks et al. ................. 710/104
`
`
`
`50
`�
`
`53
`
`POWER
`
`39
`
`57
`
`1h-l
`
`-
`
`FIRMWARE
`
`HUB
`MODULE
`
`,_
`
`,�
`
`LPC BUS
`
`52 ....,_____
`
`CONNECTOR
`
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`U.S. Patent Jun.7,2005 Sheet 1 of 3 US 6,904,484 Bl
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`27 ------------------------------------------
`- -------
`
`\j
`
`20
`
`CPU
`
`28 30
`
`35
`
`26
`
`
`
`CPU INTERFACE BUS
`
`CPU
`
`INTERFACE
`LOGIC
`
`MEMORY INTERFACE BUS
`
`37
`
`36
`
`
`
`SYSTEM EXPANSION BUS
`
`33
`
`0::::
`
`0::
`
`§ f:2
`
`c..>
`w
`
`w
`z
`z
`0
`(.)
`....I
`
`�
`
`w
`::c
`a..
`ii::
`w
`a..
`
`z
`0
`0
`....I
`
`w
`
`c:::
`CL
`
`I-c..>
`
`w
`SYSTEM BUS
`ISA PCI OR OTHER
`INTERFACE
`z
`z
`
`PERIPHERAL EXPANSION
`CONTROLLER
`0
`0
`BUS
`
`LPG 39
`BUS
`
`�
`:c
`
`41
`
`w
`
`JUMPER
`
`NON-VOL.A TILE
`SYSTEM BIOS
`24
`MEMORY
`
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`------------
`'-------------------------
`---------------
`
`HEADER
`
`25 25 25
`
`FIG. 1
`
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`U.S. Patent Jun.7,2005 Sheet 2 of 3 US 6,904,484 Bl
`
`50
`
`57
`
`1hJ
`
`-
`
`FIRMWARE
`
`53
`POWER �
`39
`
`HUB ,_
`MODULE
`
`LPG BUS
`
`52--...
`
`CONNECTOR
`
`FIG. 2
`
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`

`

`U.S. Patent Jun. 7, 2005
`
`
`US 6,904,484 Bl
`Sheet 3 of 3
`
`COUPLE FIRMWARE
`
`HUB RECOVERY MODULE
`TO MOTHERBOARD
`
`00
`
`, ,
`
`MOVE JUMPER TO
`ENABLE TO FIRMWARE
`
`HUB RECOVERY MODULE
`
`00
`
`, ,
`
`COMPUTER
`POWER�ON
`SYSTEM
`
`00
`
`,
`.
`
`00
`REPROGRAM FIRMWARE
`HUB
`
`. �
`
`00
`POWER OFF COMPUTER
`SYSTEM AND MOVE JUMPER
`
`FIG. 3
`
`IPR2020-01288
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`US 6,904,484 Bl
`
`1
`
`LOW PIN COUNT (LPC) FIRMWARE HUB
`RECOVERY
`
`
`
`FIELD OF THE INVENTION
`
`
`
`BACKGROUND OF THE INVENTION
`
`
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`2
`when programming corrections or upgrades are required.
`
`
`
`
`
`
`The EEPROM includes a read only memory device whose
`
`
`
`
`individual data storage locations (addresses) are erasable
`
`and can be reprogrammed by applying certain electrical
`
`
`5 signals to the chip. New firmware can thus be stored in the
`
`
`chip without removing the chip from the computing device.
`
`
`Embodiments of the present invention provide a method
`
`
`
`
`
`However, in situations where the computing device's firm­
`
`
`
`and apparatus for firmware hub programming on a circuit
`
`
`
`ware has been corrupted to an extent that the computing
`
`
`
`
`board. More particularly, embodiments of the present inven­
`
`
`
`
`device is unable to boot-up, the above mentioned method of
`
`
`tion provide methods and apparatus for low pin count (LPC)
`
`
`10 supplying new firmware is not available. In these cases,
`
`
`
`
`firmware hub recovery on a circuit board via a firmware hub
`
`there is no other solution but to replace the firmware chip.
`
`recovery module.
`
`
`In view of the foregoing, it can be appreciated that a
`
`
`substantial need exists for a method and apparatus for low
`
`pin count firmware hub recovery.
`
`
`Conventional computer systems include a variety of 15
`
`
`
`
`
`
`peripheral and memory devices that communicate with the
`
`
`systems's central processing unit (CPU) or chip-set proces­
`The features and advantages of the present invention will
`
`
`
`
`
`
`
`
`sor via an Industry Standard Architecture (ISA) bus or an
`
`
`become apparent from the following detailed description in
`
`
`Expansion bus (X-bus). The CPU or chip-set processor
`
`
`combination with the figures listed below.
`
`includes a large amount of pins ( e.g., approximately 50-70)
`20
`
`
`
`FIG. 1 is a block diagram of an circuit board including a
`
`
`and associated circuitry to support the ISA bus or X-bus
`
`
`
`
`low pin count (LPC) bus according to an embodiment of the
`
`
`signals that are used to interface the CPU or chip-set
`
`present invention.
`
`
`
`
`processor with the peripheral devices including input/output
`FIG. 2 is a block diagram of a firmware hub updating
`
`
`
`
`
`(1/0) or 1/0 controllers, floppy disk controller, keyboard
`
`
`
`module according to an embodiment of the present inven­
`
`
`controllers, and memory devices such as non-volatile
`25
`tion.
`
`
`
`memory devices that store, for example basis input-output
`FIG. 3 is a flow diagram illustrating a method for low pin
`
`
`
`system (BIOS) information.
`
`
`
`count (LPC) firmware hub recovery in accordance with an
`
`The large number of pins needed to support the ISA bus
`
`
`embodiment of the present invention.
`
`
`and X-bus standards generally increase the overall system
`DETAILED DESCRIPTION
`30
`
`
`
`cost. For example, larger packages are required for a CPU or
`
`
`
`chip-set. The development of the low pin count (LPC) bus
`Embodiments of methods and systems for low pin count
`
`
`
`
`
`
`
`
`has obviated to some extent the problem mentioned above.
`
`
`
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`(LPC) firmware hub recovery using a firmware hub recovery
`
`
`
`
`The LPC bus includes general purpose signal lines that carry
`module.
`
`
`
`substantially all time-multiplexed address, data and control
`In the following description, for purposes of explanation,
`
`35
`
`
`
`information to implement memory, 1/0, and bus transactions
`
`
`
`
`numerous specific details are set forth to provide a thorough
`
`
`
`between the CPU and other system devices.
`
`
`
`understanding of the present invention. It will be
`
`
`Presently there are no other peripheral components that
`
`
`
`
`appreciated, however, by one skilled in the art that the
`
`
`
`are connected to the LPC bus because the LPC bus is
`
`
`
`present invention may be practiced without these specific
`
`
`
`
`
`designed to be a "local bus" servicing the chip-set. The LPC 40
`
`
`
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`details. In other instances, structures and devices are shown
`
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`bus does not provide for expandability for add-on features
`
`
`
`in block diagram form. Furthermore, one skilled in the art
`
`
`like that provided for by a Peripheral Component Intercon­
`
`
`
`
`can readily appreciated that the specific sequence in which
`
`
`nect (PCI) (e.g., PCI Local Bus Specification, version 2.1, a
`
`
`
`methods are presented and performed are illustrative and it
`
`
`
`copy of which may be obtained from the PCI Special Interest
`
`
`
`is contemplated that the sequences can be varied and still
`
`
`Group) bus for example. In general the LPC bus may be
`
`
`remain within the spirit and scope of the present invention.
`45
`
`
`
`
`limited to being coupled to a system bus interface controller
`
`
`
`FIG. 1 illustrates a block diagram of a computer system's
`
`
`and one or more memory devices. As used herein, the term
`
`
`circuit board 27 including a low pin count (LPC) bus 39
`
`
`
`"firmware hub" refers to the memory devices coupled to a
`
`
`
`
`according to an embodiment of the present invention. Cir­
`LPC bus.
`
`
`
`cuit board 27 may be a mother board and typically includes
`
`
`
`The firmware in the firmware hub is a computer program
`
`
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`50 a processor such as a central processing unit or CPU 20. The
`
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`
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`including a series of instructions or statements arranged in a
`
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`
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`CPU is the "brains" or "engine" of the computer system
`
`
`
`
`
`specific sequence and written in a language executable by
`
`
`
`
`responsible for overseeing all execution of operations in the
`
`
`
`the processor of the computing device to achieve a certain
`
`
`
`
`computer. Motherboard 27 also includes CPU interface logic
`result.
`
`
`21, coupled to CPU 20 and interfacing CPU 20 with other
`
`
`
`
`Firmware, as used herein, refers to those computer pro­
`
`
`
`55 circuit components such as a system bus interface controller
`
`
`
`
`grams whose instructions and/or data are stored and main­
`
`33 and main memory 26. As shown, system bus interface
`
`
`
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`tained permanently in the computing device without the
`
`
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`controller 33 may be any type of expansion bus controller
`
`
`need for the continued application of power. One such
`
`
`such as a PCI bus or peripheral bus 1/0 controller. System
`
`computer program is the basic input/output system (BIOS).
`
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`
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`bus interface controller 33 is coupled to CPU interface logic
`
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`These computer programs, like the BIOS are typically stored
`
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`60 21 and is coupled to peripheral connectors 25 via expansion
`
`
`in non-volatile read only memory (ROM), programmable
`
`
`bus 38. A bus that complies with a Peripheral Component
`
`read only memory (PROM) or erasable programmable read
`
`
`Interconnect (PCT) standard ( e.g., PCI Local Bus
`(EPROM).
`
`
`
`only memory Use of a non-volatile memory
`
`
`
`
`Specification, version 2.1, a copy of which may be obtained
`
`
`
`obviates the need to reload the programming into the com­
`
`
`
`
`from the PCI Special Interest Group) is a example of such
`
`
`puting device in the event of a power loss or turn-off.
`
`
`
`65 an expansion bus. Main memory 26 may include random
`(EEPROM)
`
`
`Erasable programmable read only memory
`
`
`access memory (RAM) 28 and read only memory (ROM) 30
`
`
`
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`does not require replacing memory chips storing firmware
`
`
`which coupled to CPU interface logic 21.
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`US 6,904,484 Bl
`
`4
`3
`
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`the recovery connector 40 module with header connector 40 of the moth­
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`
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`
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`Also included on motherboard 27 is a header
`
`
`
`
`erboard (Step 100). This coupling provides an electrical as
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`and a jumper 41. Header connector 40 is an internal con­
`
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`well as a mechanical connection between firmware hub
`nector soldered to motherboard used to connect a firmware
`
`
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`
`
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`recovery module 50 and motherboard 27 such that power
`hub recovery module to the motherboard. Jumper 41 may be
`
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`
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`50 and information
`
`recovery module 5 will be supplied to the
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`
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`a strapping jumper for setting an identification (ID) for a
`
`
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`will be transmitted to and from the motherboard 27 and
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`Basic Input Output System (BIOS) firmware hub 24 as
`
`
`firmware hub recovery module 50. Strapping jumper 41 is
`
`
`described in detail below.
`
`
`
`moved from one pin location to another pin location such
`
`
`
`
`Firmware hub 24 includes a collection of software rou-
`
`
`that firmware hub 24 is no longer recognized as the booting
`
`
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`tines and functions that communicate directly with the
`
`firmware hub. Instead, firmware hub recovery module 50,
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`
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`hardware of motherboard 27. The BIOS of firmware hub 24 10
`
`
`
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`once connected to motherboard 27, is now recognized as the
`
`
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`includes code that performs a limited diagnostic of the
`
`
`
`booting firmware hub (Step 200). The computer system is
`computer system during the power-on stage know as the
`
`
`
`
`then powered on (Step 300). The CPU out an ID for the
`
`"Power On Self Test (POST)." When power is applied to the
`
`
`
`booting firmware hub. Since strapping jumper 41 changed
`
`
`
`computer system, BIOS firmware is executed by the CPU 20
`
`
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`
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`the booting firmware hub ID from firmware hub 24 to
`
`
`
`15 firmware hub recovery module 50, the system is booted by
`before the computer system's operating system is activated.
`
`
`
`
`
`
`Firmware hub 24 further includes ID pins which require
`
`
`firmware hub module 51 on the recovery module 50. After
`
`
`the computer has been booted up, the firmware hub module
`
`
`configuration to have CPU 20 recognize it as the booting
`
`51 is used along with CPU to reprogram the firmware hub
`
`firmware hub. Strapping jumper 41 is added to the mother­
`
`
`24 on the motherboard (Step 400). After the firmware hub
`
`
`board to allow the ID for the booting firmware hub to
`
`
`
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`20 has been reprogrammed, the computer system is powered off
`
`
`
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`changed. This enables an alternative firmware hub, beside
`
`and jumper 41 is moved back to its original pin position,
`
`
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`firmware hub 24, to be recognized by the CPU as the booting
`
`
`assigning firmware hub 24 as the booting firmware hub
`
`firmware hub, by simply moving the strapping jumper 41
`
`
`(Step 500). Thus, the next time the computer system is
`
`
`
`
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`from one location to another location. In the event the
`
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`powered on, firmware hub 24 is used for the booting process.
`
`
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`firmware located on firmware hub 24 has become corrupted,
`
`
`
`
`In the foregoing, detailed descriptions of the apparatus
`
`
`strapping jumper 24 can be moved such that another firm-25
`
`
`
`
`
`
`accordance with embodiments of the present invention have
`
`
`
`
`ware hub can be recognized as the booting firmware.
`
`
`
`
`been described with reference to specific exemplary embodi­
`
`
`
`According to an embodiment of the present invention and
`
`
`
`
`ments. Accordingly, the present specification and figures are
`
`described in detail below, firmware hub 24 can be repro­
`
`
`
`
`to be regarded as illustrative rather than restrictive.
`
`
`grammed by a firmware hub recovery module.
`
`
`
`
`
`described to or hardware are 30 Moreover, although software
`
`
`
`Referring back to FIG. 1, the hardware components of
`
`
`
`
`control the certain functions, such functions may be per­
`motherboard 27 communicate along data pathway or busses
`
`
`
`
`
`
`formed using either software, hardware, or a combination of
`
`
`
`35, 36, 37, 38 and 39 which is included on motherboard 27
`
`
`software and hardware, as is well know in the art.
`which houses the CPU 20, main memory 26, and other
`
`
`What is claimed is:
`
`
`components including BIOS firmware chip 24 and bus and
`
`
`1. A method for low pin count firmware hub recovery on
`
`
`
`
`1/0 controller 33. Several types of busses shown in FIG. 1 35
`
`
`
`
`
`
`
`a circuit board of a computer system having a firmware hub
`
`
`
`
`may include for example, CPU Interface Busses, Memory
`comprising:
`
`
`Interface Busses, System Expansion Busses and Industry
`coupling a firmware hub recovery module having a firm­
`
`
`
`
`Standard Architecture (ISA) Buses.
`
`
`ware program to said circuit board;
`
`FIG. 2 is a block diagram of a firmware hub recovery
`
`
`
`establishing communication between a central processing
`40
`module according to an embodiment of the present inven­
`
`
`
`
`
`
`unit (CPU) and the firmware hub recovery module via
`tion. Firmware hub recovery module 50 may be imple­
`
`
`
`
`a low pin count (LPC) bus; and
`
`mented as an external card coupled to header connector 40
`
`
`
`booting the computer.
`
`
`which communicates with LPC bus 39 on motherboard 27.
`2.The method for low pin count firmware hub updating
`
`
`
`
`
`
`According to an embodiment of the present invention,
`
`
`
`
`45 according to claim 1 further comprising reprogramming said
`
`
`
`firmware hub recovery module requires no external connec­
`firmware hub.
`
`
`
`
`tions via cable, etc. All necessary signals are presented on
`3.The method for low pin count firmware hub updating
`
`
`
`
`the LPC bus 39. Firmware hub recovery module 50 includes
`
`
`according to claim 1, wherein said establish communication
`
`
`
`firmware hub module 51 and a connector 52. Connector 52
`
`
`
`between the central processing unit (CPU) and the firmware
`
`
`is plugged into connector 40 on motherboard 27 to connect
`
`
`
`
`hub recovery module includes assigning said firmware hub
`50
`
`
`
`the module with the motherboard. Firmware hub module 51
`
`
`
`recovery module as a firmware booting program.
`
`
`may be stored on an erasable programmable read only
`
`
`4.The method for low pin count firmware hub recovery
`memory (EPROM).
`
`
`
`according to claim 1, wherein said reprogramming said
`
`
`
`Firmware hub module 51 is powered by motherboard 27
`
`
`
`firmware hub includes reading the firmware hub recovery
`
`through connectors 40 and 52 as shown by power line 53,
`
`
`
`55 module firmware program and writing the firmware hub
`
`
`
`
`and communicates with the other system components of
`
`
`recovery module firmware program into the firmware hub to
`
`
`motherboard 27 via LPC bus 39. Firmware hub module 51
`
`
`
`replace a program in said firmware hub.
`
`provides firmware so that CPU 20 can perform various
`
`
`
`5.The method for low pin count firmware hub recovery
`
`
`
`functions of compensating for an inadequate BIOS found on
`
`
`
`according to claim 1, further comprising powering said
`
`firmware hub 24. Such functions may include booting
`
`
`
`60 computer system before reprogramming said firmware hub.
`
`
`operations, system diagnostics and system reprogramming.
`
`
`6.The method for low pin count firmware hub recovery
`
`
`
`By way of further illustration, FIG. 3 illustrates a method
`
`
`
`
`according to claim 3, further comprising reassigning said
`
`
`for a low pin count (LPC) firmware hub recovery that may
`
`
`firmware hub as the firmware booting hub after said firm­
`
`
`
`
`
`be implemented using the structures described with refer­ware hub has been reprogrammed.
`
`
`
`
`
`ence to the embodiments in FIGS. 1 -2. In accordance with 65 7.The method for low pin count firmware hub recovery
`this embodiment, the firmware hub recovery
`
`
`
`
`according module 50 is to claim 1 further comprising supplying power to
`
`
`
`
`
`coupled to the motherboard
`
`
`
`said firmware hub 27 by mating connector 52 of recovery module by said circuit board.
`
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`US 6,904,484 Bl
`
`6
`5
`8. A low pin count firmware hub recovery system for a
`
`
`
`17.The method according to claim 1, futher comprising:
`
`
`
`
`
`
`circuit board of a computer system having a firmware hub
`
`
`
`before booting the computer, sending an identification
`comprising:
`
`
`from the CPU for a desired booting firmware hub over
`
`
`
`a connector for coupling a firmware hub recovery module
`
`the LPC bus; and
`
`to said circuit board;
`5
`recognizing the firmware hub recovery module as the
`
`
`
`
`
`a central processing unit (CPU) communicating with said
`
`
`
`booting firmware hub in accordance with the identifi­
`
`firmware hub recovery module via a low pin count
`
`cation sent from the CPU.
`(LPC) bus; and
`18.The system according to claim 8, wherein the CPU
`
`
`
`
`
`a jumper for enabling said firmware hub recovery module
`
`
`
`10 communicates with firmware hub recovery module only via
`
`as a booting firmware hub.
`
`the LPC bus.
`
`9.The low pin count firmware hub recovery system
`19.The system according to claim 8, wherein the CPU is
`
`
`
`
`according to claim 8, further comprising firmware program­
`
`
`
`adapted to send an indentification for the booting firmware
`
`
`ming located on said firmware hub recovery module for
`
`hub over the LPC bus, and wherein the firmware hub
`
`
`reprogramming said firmware hub.
`15
`
`
`10.The low pin count firmware hub recovery system
`
`
`
`
`recovery module is enabled as the booting firmware hub in
`
`
`
`
`according to claim 8, further comprising a power supply to
`
`
`accordance with the identification sent from the CPU.
`
`
`supply power to said circuit board.
`
`
`
`20.The system according to claim 8, further comprising:
`
`11.The low pin count firmware hub recovery system
`
`
`
`
`
`according to claim 10, wherein power is supplied to said 20
`
`interface bus;
`
`
`
`firmware hub recovery module by said circuit board.
`
`
`
`
`
`12.The low pin count firmware hub recovery system
`
`memory interface bus;
`
`
`
`according to claim 8, wherein said firmware hub recovery
`
`
`
`module includes an erasable programmable read only
`a system bus interface controller connected to the CPU
`
`
`
`
`memory (EPROM).
`
`
`
`interface logic by a system expansion bus; and
`25
`
`
`13.The low pin count firmware hub recovery system
`
`
`
`
`at least one peripheral connector connected to the system
`
`
`according to claim 8, wherein said jumper is a strapping
`
`
`
`
`bus interface controller by a peripheral expansion bus,
`jumper.
`
`
`
`
`
`wherein the LPC bus provides connections between the
`14. A firmware hub recovery module for a circuit board of
`
`
`
`
`firmware hub recovery module and the system bus
`
`
`a computer system having a firmware hub comprising:
`30
`
`interface controller.
`
`
`a connector for coupling said firmware hub recovery
`21. The firmware recovery hub module according to claim
`
`
`
`
`
`
`module to said circuit board; and
`
`14, wherein the firmware hub module communicates with
`
`
`a firmware hub module communicating with a central
`
`
`the CPU only via the LPC bus.
`
`
`processing unit (CPU) via a low pin count (LPC) bus,
`22. The firmware recovery hub module according to claim
`
`
`
`
`
`such that said firmware hub module is capable of 35
`
`
`
`
`14, wherein the CPU is adapted to send an identification for
`
`
`functioning as a booting firmware hub.
`
`
`
`
`the booting firmware hub over the LPC bus, and wherein the
`
`
`
`15. The firmware hub recovery module according to claim
`
`
`
`firmware hub module is adapted to function as the booting
`
`
`
`14, wherein said firmware hub recovery module is powered
`
`
`
`
`firmware hub in accordance with the identification sent from
`
`by said circuit board.
`40 the CPU.
`
`
`16.The method according to claim 1, wherein the CPU
`
`
`
`communicates with the firmware hub recovery module only
`
`via the LPC bus.
`
`CPU interface logic connected to the CPU by a CPU
`
`main memory connected to the CPU interface logic by a
`
`* * * * *
`
`IPR2020-01288
`Sony EX1021 Page 7
`
`