Paper 34
`Trials@uspto.gov
`Date: March 2, 2022
`571-272-7822
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`XILINX, INC.,
`Petitioner,
`
`v.
`
`ARBOR GLOBAL STRATEGIES, LLC,
`Patent Owner.
`____________
`
`IPR2020-015671
`Patent 7,126,214 B2
`____________
`
`
`
`Before KARL D. EASTHOM, BARBARA A. BENOIT, and
`SHARON FENICK, Administrative Patent Judges.
`
`BENOIT, Administrative Patent Judge.
`
`
`
`JUDGMENT
`Final Written Decision
`Determining All Challenged Claims Unpatentable
`35 U.S.C. § 318(a)
`
`
`
`
`
`
`
`1 Taiwan Semiconductor Manufacturing Co. Ltd. filed a petition in
`IPR2021-00735 and has been joined as a party to IPR2020-01567.
`
`

`

`IPR2020-01567
`Patent 7,126,214 B2
`Xilinx, Inc. (“Petitioner”) filed a Petition (Paper 2, “Pet.”) requesting
`an inter partes review of claims 1–6 and 26–31 (the “challenged claims”) of
`U.S. Patent No. 7,126,214 B2 (Ex. 1001, “the ’214 patent”). Pet. 1.
`Petitioner filed a Declaration of Paul Franzon, Ph.D. (Ex. 1002) with its
`Petition. Arbor Global Strategies LLC (“Patent Owner”) filed a Preliminary
`Response (Paper 9, “Prelim. Resp.”). We determined that the information
`presented in the Petition established that there was a reasonable likelihood
`that Petitioner would prevail with respect to at least one of the challenged
`claims, and on March 5, 2021, we instituted this proceeding as to all
`challenged claims and all grounds of unpatentability. Paper 13 (“Institution
`Decision” or “Inst. Dec.”).
`After institution, Taiwan Semiconductor Manufacturing Co. Ltd.
`(“TSM”) filed a Petition seeking inter partes review of the claims
`challenged in this proceeding and a Motion for Joinder. IPR2021-00735,
`Papers 1, 3, 5.2 We instituted an inter partes review in IPR2021-00735 and
`joined TSM as a party to this proceeding. Paper 20.
`Subsequently, Patent Owner filed a Patent Owner Response
`(Paper 19, “PO Resp.”) and a declaration of Shukri Souri, Ph.D. in support
`thereof (Ex. 2011); Petitioner filed a Reply (Paper 23, “Pet. Reply”) and a
`supplemental declaration of Dr. Franzon in support thereof (Ex. 1070); and
`Patent Owner filed a Sur-reply (Paper 27, “PO Sur-reply”). Thereafter, the
`parties presented oral arguments, and the Board entered a transcript into the
`record. Paper 33 (“Tr.”).
`
`
`2 The petition in IPR2021-00735 (Paper 1) filed on April 5, 2021 was
`replaced by a corrected petition (Paper 5), which was accepted by the Board
`(Paper 7).
`
`2
`
`

`

`IPR2020-01567
`Patent 7,126,214 B2
`We have jurisdiction under 35 U.S.C. § 6(b)(4). For the reasons set
`forth in this Final Written Decision pursuant to 35 U.S.C. § 318(a), we
`determine that Petitioner demonstrates by a preponderance of evidence that
`the challenged claims are unpatentable.
`
`I. BACKGROUND
`
`A. Real Parties-in-Interest
`As the real parties-in-interest, Petitioner identifies itself (Pet. 48) and
`TSM identifies itself and TSMC North America (IPR2021-00735, Paper 5,
`48). Patent Owner identifies Arbor Global Strategies LLC. Papers 4, 1;
`6, 1.
`
`B. Related Proceedings
`The parties identify Arbor Global Strategies LLC v. Xilinx, Inc., 1:19-
`cv-1986-MN (D. Del.) (filed October 18, 2019) as a related proceeding. See
`Pet. 48; Papers 4, 1; 6, 1.
`Concurrent with the instant Petition, Petitioner filed petitions
`challenging claims in three related patents, respectively IPR2020-01568
`challenging U.S. Patent No. 7,282,951 (“the ’951 patent”), IPR2020-01570
`challenging U.S. Patent No. RE42035, and IPR2020-01571 challenging U.S.
`the 6,781,226 patent. See, e.g., Pet. 48. These three patents also have been
`challenged by a different petitioner in IPR2020-01020, IPR2020-01021
`(“IPR-1021”), and IPR2020-01022. The joined party here (TSM) also was
`joined as a party to each of those proceedings.
`
`C. The ’214 patent
`The ’214 patent describes a stack of integrated circuit (“IC”) die
`elements including a field programmable gate array (FPGA) on a die, a
`
`3
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`

`IPR2020-01567
`Patent 7,126,214 B2
`memory on a die, and a microprocessor on a die. Ex. 1001, code (57),
`Fig. 4. Multiple contacts traverse the thickness of the die elements of the
`stack to connect the gate array, memory, and microprocessor. Ex. 1001,
`code (57), Fig. 4. According to the ’214 patent, this arrangement “allows for
`a significant acceleration in the sharing of data between the microprocessor
`and the FPGA element while advantageously increasing final assembly yield
`and concomitantly reducing final assembly cost.” Ex. 1001, code (57),
`Fig. 4.
`Figure 4 follows:
`
`
`Figure 4 above depicts a stack of dies including FPGA die 68, memory die
`66, and microprocessor die 64, interconnected using contact holes 70.
`Ex. 1001, 4:59–5:2.
`
`The ’214 patent explains that an FPGA provides known advantages as
`part of a “reconfigurable processor.” See Ex. 1001, 1:23–39. Reconfiguring
`the FPGA gates alters the “hardware” of the combined “reconfigurable
`processor” (e.g., the processor and FPGA) making the processor faster than
`
`4
`
`

`

`IPR2020-01567
`Patent 7,126,214 B2
`one that simply accesses memory (i.e., “the conventional ‘load/store’
`paradigm”) to run applications. See Ex. 1001, 1:23–39. A “reconfigurable
`processor” provides a known benefit of flexibly providing the specific
`functional units needed for applications to be executed. See Ex. 1001, 1:23–
`39.
`
`D. Illustrative Claim
`The Petition challenges claims 1–6 and 26–31, of which claims 1, 2,
`26, and 27 are independent claims. Each of the challenged claims are
`directed toward a programmable array module. See, e.g., Ex. 1001, 7:56
`(independent claim 1), 8:2 (independent claim 2), 9:41 (independent claim
`26), 9:52. Claim 1, reproduced below with bracketed numbering added for
`reference, illustrates the challenged claims at issue:
`1. A programmable array module comprising:
`[1.1] at least a first integrated circuit functional element
`including a field programmable gate array; and
`[1.2] at least a second integrated circuit functional element
`including a memory array stacked with and electrically
`coupled to said field programmable gate array of said
`first integrated circuit functional element
`[1.3] wherein said field programmable gate array is
`programmable as a processing element, and
`[1.4] wherein said memory array is functional to accelerate
`reconfiguration of said field programmable gate array as
`a processing element.
`
`
`Ex. 1001, 7:56–67.
`Among the differences recited by the independent claims, independent
`claims 2 and 27 recite “said first and second integrated circuit functional
`elements being coupled by a number of contact points distributed throughout
`
`5
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`IPR2020-01567
`Patent 7,126,214 B2
`the surfaces of said functional elements.” Ex. 1001, 8:1–15, 9:58–61.
`Independent claims 26 and 27 recite “wherein said memory array is
`functional to accelerate external memory references to said processing
`element.” Ex. 1001, 9:49–51, 10:2–4.
`
`E. The Asserted Grounds
`Petitioner challenges claims 1–6 and 26–31 of the ’214 patent on the
`following grounds (Pet. 1):
`
`Claims Challenged
`
`35 U.S.C.
`§
`1, 2, 4, 6, 26, 27, 29, 31 1033
`
`3, 28
`
`103
`
`References
`
`Zavracky4, Chiricescu5,
`Akasaka6
`Zavracky, Chiricescu,
`Akasaka, Satoh7
`
`
`3 The Leahy-Smith America Invents Act (“AIA”), Pub. L. No. 112-29, 125
`Stat. 284, 287–88 (2011), amended 35 U.S.C. § 103. For purposes of
`institution, the ’214 patent contains a claim with an effective filing date
`before March 16, 2013 (the effective date of the relevant amendment), so the
`pre-AIA version of § 103 applies.
`4 Zavracky, US 5,656,548, issued Aug. 12, 1997 (Ex. 1003).
`5 Silviu M. S. A. Chiricescu and M. Michael Vai, A Three-Dimensional
`FPGA with an Integrated Memory for In-Application Reconfiguration Data,
`Proceedings of the 1998 IEEE International Symposium on Circuits and
`Systems, May 1998, ISBN 0-7803-4455-3/98 (Ex. 1004).
`6 Yoichi Akasaka, Three-Dimensional IC Trends, Proceedings of the IEEE,
`Vol. 74, Issue 12, pp. 1703–14, Dec. 1986, ISSN 0018-9219 (Ex. 1005).
`7 Satoh, PCT App. Pub. No. WO00/62339, published Oct. 19, 2000.
`(Ex. 1008 (English translation)).
`
`6
`
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`IPR2020-01567
`Patent 7,126,214 B2
`
`Claims Challenged
`
`5, 30
`
`35 U.S.C.
`§
`
`103
`
`References
`
`Zavracky, Chiricescu,
`Akasaka, Alexander8
`
`Petitioner contends that each of the asserted references is prior art to each of
`the challenged claims. Pet. 1–3.
`
`II. ANALYSIS
`Petitioner challenges claims 1–6 and 26–31 as obvious based on the
`grounds listed above. Patent Owner disagrees.
`
`A. Legal Standards
`To prevail in challenging Patent Owner’s claims, Petitioner must
`demonstrate by a preponderance of the evidence that the claims are
`unpatentable. 35 U.S.C. § 316(e) (2012); 37 C.F.R. § 42.1(d) (2017). “In an
`[inter partes review], the petitioner has the burden from the onset to show
`with particularity why the patent it challenges is unpatentable.” Harmonic
`Inc. v. Avid Tech., Inc., 815 F.3d 1356, 1363 (Fed. Cir. 2016) (citing 35
`U.S.C. § 312(a)(3) (requiring inter partes review petitions to identify “with
`particularity . . . the evidence that supports the grounds for the challenge to
`each claim”)); see also 37 C.F.R. § 42.104(b) (requiring a petition for inter
`partes review to identify how the challenged claim is to be construed and
`where each element of the claim is found in the prior art patents or printed
`publications relied on).
`
`
`8 Michael J. Alexander et al., Three-Dimensional Field-Programmable Gate
`Arrays, Proceedings of Eighth International Application Specific Integrated
`Circuits Conference, Sept. 1995 (Ex. 1009).
`
`7
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`IPR2020-01567
`Patent 7,126,214 B2
`A claim is unpatentable under 35 U.S.C. § 103 if the differences
`between the claimed subject matter and the prior art are such that the subject
`matter, as a whole, would have been obvious at the time the invention was
`made to a person having ordinary skill in the art to which said subject matter
`pertains. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007).
`Tribunals resolve obviousness on the basis of underlying factual
`determinations, including (1) the scope and content of the prior art; (2) any
`differences between the claimed subject matter and the prior art; (3) the level
`of skill in the art; and (4) where in evidence, so-called secondary
`considerations.9 See Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
`Prior art references must be “considered together with the knowledge of one
`of ordinary skill in the pertinent art.” In re Paulsen, 30 F.3d 1475, 1480
`(Fed. Cir. 1994) (citing In re Samour, 571 F.2d 559, 562 (CCPA 1978)).
`To demonstrate obviousness, “there must be some articulated
`reasoning with some rational underpinning to support the legal conclusion of
`obviousness.” KSR, 550 U.S. at 418. More specifically, Petitioner must
`demonstrate by a preponderance of evidence that “a skilled artisan would
`have had reason to combine the teaching of the prior art references to
`achieve the claimed invention, and that the skilled artisan would have had a
`reasonable expectation of success from doing so.” PAR Pharm., Inc. v. TWI
`Pharm., Inc., 773 F.3d 1186, 1193 (Fed. Cir. 2014).
`
`
`9 No argument or evidence regarding secondary considerations has been
`presented in this proceeding.
`
`8
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`IPR2020-01567
`Patent 7,126,214 B2
`
`B. Level of Ordinary Skill in the Art
`The parties dispute the level of ordinary skill in the art. The level of
`ordinary skill in the art is “a prism or lens through which . . . the Board
`views the prior art and claimed invention” to prevent hindsight bias.
`Okajima v. Bourdeau, 261 F.3d 1350, 1355 (Fed. Cir. 2001). In determining
`the level of ordinary skill, various factors may be considered, including the
`“types of problems encountered in the art; prior art solutions to those
`problems; rapidity with which innovation are made; the sophistication of the
`technology; and educational level of active workers in the field.” In re
`GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995) (internal quotation and
`citation omitted). Generally, it is easier to establish obviousness under a
`higher level of ordinary skill in the art. Innovention Toys, LLC v. MGA
`Entm’t, Inc., 637 F.3d 1314, 1323 (Fed. Cir. 2011) (“A less sophisticated
`level of skill generally favors a determination of nonobviousness . . . while a
`higher level of skill favors the reverse.”).
`Relying on the declaration testimony of Dr. Franzon, Petitioner
`contends that
`[a] person of ordinary skill in the art (“POSITA”) at the time of
`the alleged invention of the ’214 patent would have been a person
`with a Bachelor’s Degree in Electrical Engineering or Computer
`Engineering, with at least two years of industry experience in
`integrated circuit design, packaging, or fabrication. Ex. 1002 ¶¶
`58–60.
`Pet. 7 (citing Ex. 1002 ¶¶ 58–60).
`Patent Owner asserts that
`[a] person of ordinary skill in the art (“POSITA”) around
`December 5, 2001 (the earliest effective filing date of the ’214
`Patent) would have had a Bachelor’s degree in Electrical
`Engineering or a related field, and either (1) two or more years
`
`9
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`

`IPR2020-01567
`Patent 7,126,214 B2
`of industry experience; and/or (2) an advanced degree in
`Electrical Engineering or related field. Souri Decl., ¶ 25.
`PO Resp. 8–9 (citing Ex. 2011 ¶ 25).
`We adopt Petitioner’s proposed level of ordinary skill in the art as we
`did in the Institution Decision, which comports with the teachings of the
`’214 patent and the asserted prior art. See Inst. Dec. 7. Patent Owner’s
`proposed level largely overlaps with Petitioner’s proposed level while
`lacking some specificity found in Petitioner’s proposed level. Even if we
`adopted Patent Owner’s proposed level, the outcome would remain the
`same. See Pet. Reply 1 (indicating Dr. Franzon confirmed his opinions
`under Patent Owner’s proposed level of ordinary skill).
`
`C. Claim Construction
`In an inter partes review, the Board construes each claim “in
`accordance with the ordinary and customary meaning of such claim as
`understood by one of ordinary skill in the art and the prosecution history
`pertaining to the patent.” 37 C.F.R. § 42.100(b). Under this standard, which
`is the same standard applied by district courts, claim terms take their plain
`and ordinary meaning as would have been understood by a person of
`ordinary skill in the art at the time of the invention and in the context of the
`entire patent disclosure. Phillips v. AWH Corp., 415 F.3d 1303, 1313 (Fed.
`Cir. 2005) (en banc). “There are only two exceptions to this general rule:
`1) when a patentee sets out a definition and acts as his own lexicographer, or
`2) when the patentee disavows the full scope of a claim term either in the
`specification or during prosecution.” Thorner v. Sony Comput. Entm’t Am.
`LLC, 669 F.3d 1362, 1365 (Fed. Cir. 2012).
`
`10
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`

`IPR2020-01567
`Patent 7,126,214 B2
`In its Petition, Petitioner did not provide an express construction for
`any claim term. Pet. 13. Nor did Patent Owner in either its Preliminary
`Response or its Response to the Petition. Prelim. Resp. 5; PO Resp. 9
`(quoting 37 C.F.R. § 42.100(b)). In our Institution Decision, we agreed that
`no terms require explicit construction. Inst. Dec. 11–12 (citing Pet. 13;
`Prelim. Resp. 4, 5).
`In that decision, we also noted and addressed the claim construction
`issue raised by Patent Owner in its Preliminary Response based on similar
`terms we construed in instituting trial in IPR-1021. Inst. Dec. 8–11.
`Specifically, Patent Owner argued the proper scope of the claim terms “said
`memory array is functional to accelerate reconfiguration of said field
`programmable gate array as a processing element” recited in independent
`claims 1 and 2 and “said memory array is functional to accelerate external
`memory references to said processing element” recited in independent
`claims 26 and 27 (collectively, “the functional to accelerate” limitations).
`Inst. Dec. 8–11. We did not agree with Patent Owner’s arguments and noted
`that the instituted trial would afford both parties an opportunity for further
`briefing the issue. Inst. Dec. 10–11.
`During trial, the parties have disputed the scope of the “the functional
`to accelerate” limitations in the context of the purported teachings of the
`prior art and in their respective Reply and Sur-reply. See, e.g., PO Resp. 19,
`Pet. Reply 2–3; PO Sur-reply 1–2. Patent Owner contends that the plain
`language of the challenged claims requires “that a memory array is
`responsible for the claimed acceleration of data references.” PO Sur-reply 1.
`Each of the challenged independent claims recites “said memory array is
`functional to accelerate” either “reconfiguration of said field programmable
`
`11
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`

`IPR2020-01567
`Patent 7,126,214 B2
`gate array as a processing element” (claims 1 and 2) or “external memory
`references to said processing element” (claims 26 and 27). Ex. 1001, 7:56–
`67 (claim 1), 8:1–15 (claim 2), 9:41–51 (claim 26), 10:2–4 (claim 27).
`Patent Owner further contends that the structure within the memory
`array responsible for accelerating is the wide configuration data port
`disclosed in the ’214 patent. PO Resp. 19 (“Rather, as the claims themselves
`require, it is a structure provided within the memory array (i.e. the wide
`configuration data port disclosed in the ’214 Patent) that is responsible for
`accelerating the programmable array’s accelerated memory references.”
`(citing Ex. 2011 ¶ 53)); PO Sur-reply 2 (repeats statement that the wide
`configuration data port is the structure provided within the memory array
`that is responsible for the claimed acceleration (quoting PO Resp. 18–19)).
`Thus, Patent Owner equates (by using “i.e.”) the requisite structure within
`the memory array to be the wide configuration data port disclosed in the
`’214 patent.
`The challenged claims recite a function of the memory array and that
`that the memory array structurally is “stacked with and electrically coupled
`to” the FPGA. Ex. 1001, 7:59–60 (claim 1); see also Ex. 1001, 7:56–8:30
`(claims 1, 2), 9:41–10:21 (claims 26, 27). None of the claims recite a wide
`configuration data port or any structure within the memory array.
`For support, Patent Owner relies on Dr. Souri’s declaration testimony.
`PO Resp. 19 (citing Ex. 2011 ¶ 53 (concluding that “it is the structure
`provided within the memory array (i.e. the wide configuration data port
`disclosed in the ’214 Patent) that is responsible for accelerating the
`programmable array’s accelerated external memory references”)). Prior to
`this conclusion, at the cited paragraph, Dr. Souri quotes a passage from the
`
`12
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`IPR2020-01567
`Patent 7,126,214 B2
`’214 patent specification, but that passage describes nothing about a memory
`array, and Dr. Souri provides no explanation for how he reaches this
`conclusory position. See Ex. 2011 ¶ 53 (quoting Ex. 1001, 5:16–26).
`When explaining that position “[i]n more detail,” Dr. Souri describes
`a wide configuration data port as interconnecting the two elements of a
`memory die and a programmable array die. Ex. 2011 ¶ 54 (describing the
`inventors as solving the problem of “unacceptably long reconfiguration
`times” “by stacking a memory die with a programmable array die” and “by
`interconnecting those two elements with a ‘wide configuration data port’
`that employs through-silicon contacts, with the potential for even further
`acceleration where the memory die is ‘tri-ported.’” (citing Ex. 1001, 5:16–
`26) (emphasis added here)). As such, Dr. Souri describes the wide
`configuration data port as interconnecting a memory die and a
`programmable array die. Although Dr. Souri describes the wide
`configuration data port as interconnecting two dies, Dr. Souri does not
`describe the wide configuration data port as being within the memory array.
`Because Dr. Souri does not adequately explain how a wide configuration
`data port interconnecting a memory die with another element shows a wide
`configuration data port within a memory array, we give little weight to
`Dr. Souri’s testimony that the claims require a wide configuration data port
`within the memory array.
`The weight we accord Dr. Souri’s testimony in this regard is further
`supported by Patent Owner’s expert Krishnendu Chakrabarty, Ph.D. who
`indicates the very wide configuration data port shown in Figure 5 of the ’214
`
`13
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`IPR2020-01567
`Patent 7,126,214 B2
`patent connects the memory die and FPGA die.10 Ex. 1075, 157:23–158:7;
`Ex. 1075, 156:7–1011; see Ex. 1075, 163:8–21 (describing a data port as
`“just an interface to send data from one place to another” and a configuration
`data port as “just a data port used for configuration”); see also Pet. Reply 9
`(quoting 1075, 157:23–158:3, 163:8–163:21). Patent Owner argues its own
`prior expert’s testimony contradicts the ’214 patent description of “the wide
`configuration data port with buffer cells.” PO Sur-reply 8 (citing Pet. Reply
`9; Ex. 1001, 5:27–36) (emphasis added). For the reasons explained below,
`we do not agree that the ’214 patent requires a wide configuration data port
`to include buffer cells and so do not agree with Patent Owner that Dr.
`Chakrabarty’s description of a wide configuration data port contradicts the
`’214 patent.
`Furthermore, the disclosure of a wide configuration data port in
`Figure 5 of the ’214 patent does not support Patent Owner’s position that the
`claims require such a structure within the memory array. The ’214 patent
`depicts a “VERY WIDE CONFIGURATION DATA PORT 82” as a “black
`box” in Figure 5 and is not clear on its face how the wide configuration data
`port 82 in Figure 5 relates structurally to a memory die or memory array.
`Ex. 1001, 5:27–37, Fig. 5. Additionally, Figure 5 of the ’214 patent includes
`structures (specifically, buffer cells) described as preferably being within the
`
`
`10 Dr. Chakrabarty is Patent Owner’s expert in the IPR2020-01020,
`IPR2020-01021, and IPR2020-01022 that challenge other patents of Patent
`Owner that have a substantially similar written description with regard to the
`cited portions of the ’214 patent. See IPR2020-01020, Ex. 1001, Figs. 4–5;
`IPR2020-01021, Ex. 1001, Figs. 4–5; IPR2020-01022, Ex. 1001, Figs. 4–5.
`11 “Q: So in this system [referencing Fig. 4], the configuration data port has
`wires that connect the memory die to the FPGA die. Right? A: Yes.”
`
`14
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`IPR2020-01567
`Patent 7,126,214 B2
`memory die and structures (specifically logic cells) as being part of the
`FPGA. Thus, Figure 5 of the ’214 patent does not depict the wide
`configuration data port 82 as being within a memory array.
`Specifically, Figure 5 follows:
`
`
`Figure 5 shows a very wide configuration data port 82 on the left side
`of the figure that is connected to each buffer cell depicted to the right of very
`wide configuration data port 82. See Ex. 1001, Fig. 5, 5:33–37. In turn,
`each buffer cell is connected to an associated configuration memory cell 86,
`which is adjacent to a logic cell 84. See Ex. 1001, Fig. 5, 5:33–37. The ’214
`patent indicates that “[t]he buffer cells 88 are preferably a portion of the
`memory die 66 (FIG. 4)” but is silent as to the wide configuration data port’s
`structural relationship to the memory die. Figure 5, however, depicts very
`wide configuration data port 82 as being separate from the buffer cells.
`Moreover, the ’214 patent indicates that “the FPGA 68 compris[es] the logic
`
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`IPR2020-01567
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`cells 84,” which are depicted in Figure 5 as being separate from the very
`wide configuration data port 82. Ex. 1001, 5:38.
`Therefore, the ’214 patent in Figure 5 and its corresponding
`description do not describe the wide configuration data port as being within
`the memory array. Ex. 1001, Fig. 5, 5:27–47. To the extent the claims
`implicate any portion of a wide configuration data port, it is the numerous
`via connections associated with that port connected to a memory die that
`supports a “memory array [] functional to accelerate” data references. This
`is consistent with the testimony of Patent Owner’s experts Dr. Souri and
`Dr. Chakrabarty as outlined above.
`Moreover, the ’214 patent further indicates that Figure 5 is a
`“functional block diagram of the configuration cells” through which the
`FPGA 70 shown in Figure 4 is updated “in one clock cycle by updating all
`of the configuration cells in parallel.”12 Ex. 1001, 5:27–33. Notably, the
`reconfigurable processor module 60 depicted in Figure 4 comprises “a die
`package 62 to which is coupled a microprocessor die 64, memory die 66 and
`FPGA die 68, all of which have a number of corresponding contact points,
`
`
`12 The ’214 patent specification also states that “[f]urther disclosed herein is
`an FPGA module that uses stacking techniques to combine it with a memory
`die for the purpose of accelerating FPGA reconfiguration.” Ex. 1001, 2:61–
`63. This, and other disclosures, indicate that reconfiguration may occur by
`using the significant number of vias of the stacking technique (i.e., without
`necessarily requiring any other structure of Figure 5’s wide configuration
`data port (whatever it is)). See id. at 5:41–47 (“Other methods for taking
`advantage of the significantly increased number of connections to the cache
`memory die 66 (FIG. 4) may include its use to totally replace the
`configuration bit storage on the FPGA die 68 as well as to provide larger
`block random access memory (“RAM” than can be offered within the FPGA
`die 68 itself.”)).
`
`16
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`IPR2020-01567
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`or holes 70 formed throughout the area of the package 62 and the various die
`64, 66, and 68.” Ex. 1001, 4:64–5:2. Thus, even in the embodiment
`describing the wide configuration data port 82 as part of Figure 4’s
`reconfigurable processor module 60 that includes elements outside of
`memory die 66, the ’214 patent does not indicate the wide configuration data
`port 82 is within a memory array. A wide configuration data port is not
`otherwise described in the ’214 patent.
`For these reasons, we find Figure 5’s depiction of the wide
`configuration data port 82 does not support Patent Owner’s position that a
`structure within the memory array is responsible for the recited acceleration.
`In its Sur-reply, Patent Owner contends that the ’214 patent “describes
`that the memory array is functional to accelerate when it describes a wide
`configuration data port and ‘buffer cells 88 . . . a portion of memory die 66’
`(a necessary part of the wide configuration data port) that is responsible for
`the acceleration of reconfiguration data to the field programmable gate array
`(‘FPGA’)[sic].” PO Sur-reply 1–2 (citing Ex. 1001, 5:32–41 (discussing
`Fig. 5)). The Patent Owner appears to be contending that the buffer cells 88
`depicted in Figure 5 both (i) are a portion of memory die 66 and (ii) are a
`necessary part of the wide configuration data port. See also PO Resp. 21
`(indicating the ’214 patent “discloses utilizing a portion of the memory array
`as a wide configuration data port including buffer cells” (citing Ex. 1001,
`5:33–38)); Tr. 53:18–19 (Patent Owner confirming its position that “buffer
`cells are part of the wide configuration data port.”).
`For the reasons discussed above, we do not agree that Figure 5 depicts
`the buffer cells as part of the wide configuration data port. The ’214 patent
`expressly describes the central purpose of the buffer cells: “they can be
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`loaded while the FPGA 68 comprising the logic cells are in operation,”
`which “then enables the FPGA 68 to be totally reconfigured in one clock
`cycle with all of it[s] configuration cells 84 updated in parallel.” Ex. 1001,
`5:39–43 (emphasis added). None of the challenged claims, however, recite
`buffer cells or require that the recited FPGA be reconfigured while in
`operation.
`Additionally, Patent Owner’s edited quotation omits the qualification
`that “[t]he buffer cells are preferably a portion of the memory die 66” shown
`in Figure 4, which further undermines Patent Owner’s position. Ex. 1001,
`5:36–37. Additionally, the buffer cells are only “preferably a portion of the
`memory die 66” that enables loading the buffer cells while the logic cells are
`in operation. Ex. 1001, 5:36–39 (“The buffer cells 88 are preferably a
`portion of the memory die 66 (FIG. 4). In this manner, they can be loaded
`while the FPGA 68 comprising logic cells 84 are in operation.”). None of
`the challenged claims require loading the FPGA while it is in operation,
`which further undermines Patent Owner’s position.
`In sum, the ’214 patent does not support Patent Owner’s contentions
`regarding the wide configuration data port.13 Additionally, Patent Owner’s
`expert, Dr. Souri, describes a wide configuration data port as interconnecting
`“the two elements of a memory die and a programmable array die” rather
`than being within the memory array. Ex. 2011 ¶ 54. Moreover, Patent
`Owner appears elsewhere to describe the wide configuration data port as the
`
`
`13 Moreover, during the Oral Hearing, Patent Owner’s counsel allowed for
`buffer cells being on the FPGA. Specifically, Patent Owner’s counsel
`argued that “when the buffer cells are on the FPGA, it then raises the
`question, okay, well, what’s on the memory array, right. And my answer
`would be probably more buffer cells.” Tr. 54:21–24.
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`“die-area interconnection arrangement with buffer cells,” which further
`supports that the wide configuration data port is not a structure provided
`within the memory array. PO Sur-reply 2 (“the novel die-area
`interconnection arrangement with buffer cells (i.e., wide configuration data
`port) allows the parallel loading of data from the memory die to the
`programmable array that is responsible for the claimed acceleration”).
`Furthermore, the ’214 patent consistently identifies acceleration with
`stacking techniques that include contacts throughout the stacked dies,
`without requiring other structure. For example, the abstract of the ’214
`patent describes a processor module “constructed by stacking one or more
`thinned microprocessor, memory and/or . . . FPGA die elements and
`interconnecting the same utilizing contacts that traverse the thickness of the
`die.” Ex. 1001, code (57). The abstract indicates that this processor module
`“allows for significant acceleration of the sharing of data between the
`microprocessor and the FPGA element. . . .” Ex. 1001, code (57). Notably,
`this description of “significant acceleration” does not include a wide
`configuration data port or buffer cells.
`Additionally, the ’214 patent similarly describes stacking techniques
`as accelerating the sharing of data between the microprocessor and the
`FPGA and accelerating external memory references, without referring to a
`wide configuration data port or buffer cells. See Ex. 1001, 2:64–66
`(describing “a processor module with a reconfigurable capability that may
`include, for example, a microprocessor, memory and FPGA die stacked in a
`single block for the purpose of accelerating the sharing of data between the
`microprocessor and FPGA”), 2:64–66 (indicating “the FPGA module may
`employ stacking techniques to combine it with a memory die for the purpose
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`of accelerating external memory references”). The ’214 patent indicates that
`“[b]ecause the various die 64, 66 and 68 (FIG. 4) have very short electrical
`paths between them, the signal levels can be reduced while at the same time
`the interconnect clock speeds can be increased.” Ex. 1001, 5:50–53
`(emphasis added). Similarly, “there is an added benefit of . . . increased
`operational bandwidth.” Ex. 1001, 5:48–50. Notably, the descriptions of
`shorter electrical paths, increased speed and bandwidth are due to the
`stacking techniques and are made within the context of Figure 4 without
`mention of Figure 5’s wide configuration data port and buffer cell
`embodiment. As noted above, even reconfiguration may occur without the
`spe