Micron Technology, Inc.
`Petitioner
`v.
`Vervain, LLC
`Patent Owner
`
`Case No. IPR2021-01550
`U.S. Patent No. 10,950,300
`
`Micron’s Hearing Demonstratives
`
`January 12, 2023
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`IPR2021-01550
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`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
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`1
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`Micron Ex. 1071, p. 1
`Micron v. Vervain
`IPR2021-01550
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`
`Petitioner
`v.
`Vervain, LLC
`Patent Owner
`
`Case No. IPR2021-01550
`U.S. Patent No. 10,950,300
`
`Micron’s Hearing Demonstratives
`
`January 12, 2023
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`IPR2021-01550
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`DEMONSTRATIVE EXHIBIT – NOT EVIDENCE
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`1
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`Micron Ex. 1071, p. 1
`Micron v. Vervain
`IPR2021-01550
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`Roadmap
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`• The 300 Patent
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`• The Remaining Dispute: RAM Cache in Dusija’s Controller
`
`• The Petition’s Showing of RAM Cache in Dusija’s Controller
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`• Petitioner’s Showing Remains Unrebutted
`
`• PO’s Arguments Are Without Merit
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`2
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`Micron Ex. 1071, p. 2
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`IPR2021-01550
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`Roadmap
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`• The 300 Patent
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`• The Remaining Dispute: RAM Cache in Dusija’s Controller
`
`• The Petition’s Showing of RAM Cache in Dusija’s Controller
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`• Petitioner’s Showing Remains Unrebutted
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`• PO’s Arguments Are Without Merit
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`Micron Ex. 1071, p. 3
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`The 300 Patent
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`• The specification discloses performing a
`“data integrity test” on data stored in MLC
`NAND flash by:
`
`1. retaining in DRAM a copy of data to be
`written to the flash memory;
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`2. writing the data to the flash memory;
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`3. reading the data back from the flash
`memory; and
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`4. comparing the data read back from the flash
`memory to the data retained in the DRAM.
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`• If the data integrity test fails, the data is
`written to the SLC NAND flash memory
`module.
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`Ex. 1007 (300 Patent), 5:59-67.
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`Micron Ex. 1071, p. 4
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`The 300 Patent – “Random Access Volatile Memory” in Claim 1
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`5
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`Ex. 1007 (300 Patent), Claim 1.
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`Micron Ex. 1071, p. 5
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`The 300 Patent – Instituted Grounds Of Unpatentability
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`• Ground 1: Claims 1–9 and 11–12 are obvious over Dusija in view of the knowledge of a
`POSA.
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`Petition (Paper 1), 6, 31-61.
`
`• Ground 2: Claim 10 is obvious over Dusija in view of Sutardja and the knowledge of
`a POSA.
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`Id., 6, 61-65.
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`Micron Ex. 1071, p. 6
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`Roadmap
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`• The 300 Patent
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`• The Remaining Dispute: RAM Cache in Dusija’s Controller
`
`• The Petition’s Showing of RAM Cache in Dusija’s Controller
`
`• Petitioner’s Showing Remains Unrebutted
`
`• PO’s Arguments Are Without Merit
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`Micron Ex. 1071, p. 7
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`The Remaining Dispute
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`• There is no dispute that all elements of the claims were known individually.
`1. PO does not dispute that Dusija teaches all claim elements except the “random
`access volatile memory.”
`
`Reply (Paper 21), 8.
`2. PO does not dispute that using a “random access volatile memory” (“RAM,” for short)
`in a controller for caching was typical and well understood by a POSA.
`
`Id., 8-9.
`
`• PO does not identify any secondary considerations of nonobviousness.
`
`• The only substantive disputes are:
`- Whether Dusija, via its incorporation of Paley, Paley’s incorporation of Harari, and the
`knowledge of a POSA, would have been understood to use a RAM “cache” in its
`controller.
`- If not, whether it would have been obvious to combine Dusija with a RAM cache in its
`controller.
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`8
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`Micron Ex. 1071, p. 8
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`IPR2021-01550
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`Roadmap
`
`• The 300 Patent
`
`• The Remaining Dispute: RAM Cache in Dusija’s Controller
`
`• The Petition’s Showing of RAM Cache in Dusija’s Controller
`
`• Petitioner’s Showing Remains Unrebutted
`
`• PO’s Arguments Are Without Merit
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`Micron Ex. 1071, p. 9
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`For Limitation [1.E], The Petition Clearly Identifies Its Theory And Support
`
`I.
`
`It would have been understood that Dusija discloses RAM cache in its controller.
`Petition (Paper 1), 42.
`
`II.
`
`It would have been obvious to include RAM cache in Dusija’s controller.
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`Id.
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`Id.
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`Micron Ex. 1071, p. 10
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`1. A POSA Would Have Understood Paragraphs [0111]–[0117] Of Dusija To
`Describe A RAM Cache
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`11
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`Petition (Paper 1), 33.
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`Micron Ex. 1071, p. 11
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`2. A POSA Would Have Understood Dusija To Disclose RAM In Its
`Controller
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`Petition (Paper 1), 34.
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`Micron Ex. 1071, p. 12
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`2. A POSA Would Have Understood Dusija To Disclose RAM In Its
`Controller
`Preferred Embodiment
`
`• Dusija’s paragraphs [0109]-[0126] describe a
`“preferred” embodiment in which the comparison is
`made with a “cached” copy, but the location of the
`cached copy is not expressly stated.
`
`Alternative Embodiment
`
`• Dusija’s paragraph [0127] states that “in an
`alternative embodiment,” the flash memory serves as
`the cache.
`
`• A POSA would thus have understood that the
`embodiment described in paragraphs [0109]-[0126]
`uses a cache that is not in flash memory.
`
`• A POSA would have immediately understood that
`Dusija would have its cache in its controller or, at the
`very least, that it would have been obvious to do so.
`Petition (Paper 1), 33 n.6; Ex. 1009 (Liu Decl.), ¶ 129 n.6;
`Reply (Paper 21), 14-15; Ex. 1057 (Liu Reply Decl.), ¶ 17.
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`Ex. 1010 (Dusija), [0109]-[0127].
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`Micron Ex. 1071, p. 13
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`3. Paley, Which Dusija Expressly Incorporates By Reference, Discloses
`That The Controller “Typically” Includes A RAM Cache
`
`Ex. 1028 (Paley), Figure 15.
`
`Petition (Paper 1), 34.
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`14
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`Ex. 1028 (Paley), [0197].
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`Micron Ex. 1071, p. 14
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`4. Harari, Which Paley Incorporates By Reference, Discloses A RAM Cache
`In Its Controller
`
`Petition (Paper 1), 34-35;
`see also Ex. 1009 (Liu Decl.), ¶¶ 134-137.
`
`Ex. 1049 (Harari), Figure 8.
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`Micron Ex. 1071, p. 15
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`5. At A Minimum, It Would Have Been Obvious To A POSA To Combine
`Dusija With A RAM Cache In Its Controller
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`16
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`Petition (Paper 1), 36.
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`Micron Ex. 1071, p. 16
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`The Board’s Institution Decision Agreed With Petitioner
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`ID (Paper 11), 30.
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`Micron Ex. 1071, p. 17
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`The Institution Decision Rejected PO’s Motivation-to-Combine Argument
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`• In crediting Petitioner’s obviousness theory, the Board relied on three key and
`undisputed facts:
`1. A POSA “would have known of the use of volatile memory for caching and would have
`considered such a use to be typical and well understood.”
`
`ID (Paper 11), 26-27.
`2. A POSA “would have known of the benefits of using RAM or other volatile memory,” such
`as “superior write endurance” and “increased speed.”
`
`Id., 30.
`“[T]here would have been a reasonable expectation of success in using volatile memory as
`cache because such a usage was considered to be ‘typical’ and thus, would not have
`required undue experimentation to implement.”
`• The Board rejected PO’s argument that a POSA would not have had a
`motivation to combine because of the combination’s purported “performance
`degradation.”
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`3.
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`Id., 30.
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`Id., 30.
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`Micron Ex. 1071, p. 18
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`Roadmap
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`• The 300 Patent
`
`• The Remaining Dispute: RAM Cache in Dusija’s Controller
`
`• The Petition’s Showing of RAM Cache in Dusija’s Controller
`
`• Petitioner’s Showing Remains Unrebutted
`
`• PO’s Arguments Are Without Merit
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`Micron Ex. 1071, p. 19
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`PO Has Not Rebutted Petitioner’s Showing That Dusija Would Have Been
`Understood To Disclose RAM Cache In Its Controller
`• The Petition explained that Dusija, through its incorporation of Paley, expressly discloses a
`RAM cache in a controller.
`
`Petition (Paper 1), 34-35; Ex. 1009 (Liu Decl.), ¶¶ 131-36.
`
`• The Petition further explained that Dusija refers to Paley’s “block management system” and
`that Paley states that its cache is part of its “block management system.”
`
`Petition (Paper 1), 35-36.
`• Neither PO’s Response nor its Sur-reply discusses Paley’s disclosure, let alone
`contradicts the Petition’s showing about Paley.
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`Micron Ex. 1071, p. 20
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`PO Has Not Rebutted Petitioner’s Showing That It Would Have Been
`Obvious To Include RAM Cache In Dusija’s Controller
`• PO does not dispute that:
`1. A POSA would have known to use RAM for caching and would have considered such a
`use to be typical and well understood.
`
`Reply (Paper 21), 7.
`2. A POSA would have known that using a RAM cache had benefits, such as superior write
`endurance and speed.
`
`Id.
`
`3. The “performance degradation” purportedly caused by using a RAM cache in Dusija’s
`controller (i.e., toggling and potential rewrites) is equally present in embodiments expressly
`disclosed by Dusija (e.g., embodiments using ECC).
`
`Id., 18-19.
`4. A POSA would have known that using a flash memory cache had drawbacks, including
`lower endurance, slower performance, greater complexity, and higher costs.
`
`Id., 20-22.
`• Undisputed facts thus establish that a POSA would have been motivated to combine Dusija
`with a controller RAM cache.
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`Id., 6-13.
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`Micron Ex. 1071, p. 21
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`Undisputed Facts Establish a Motivation to Combine As a Matter of Law
`
`• Even assuming that using RAM was not the best option for Dusija’s cache, undisputed
`evidence establishes that RAM was at least a suitable option for a cache. Obviousness
`requires nothing more.
`
`“‘[T]he question is whether there is something in the prior art as a whole to suggest
`the desirability, and thus the obviousness, of making the combination,’ not whether
`there is something in the prior art as a whole to suggest that the combination is the
`most desirable combination available.”
`
`In re Fulton, 391 F.3d 1195, 1200 (Fed. Cir. 2004)
`(cited in Reply (Paper 21), 22).
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`22
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`Micron Ex. 1071, p. 22
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`Roadmap
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`• The 300 Patent
`
`• The Remaining Dispute: RAM Cache in Dusija’s Controller
`
`• The Petition’s Showing of RAM Cache in Dusija’s Controller
`
`• Petitioner’s Showing Remains Unrebutted
`
`• PO’s Arguments Are Without Merit
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`23
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`Micron Ex. 1071, p. 23
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`PO’s Arguments Are Without Merit
`
`1. The Petition’s Purported Lack of Clarity
`2. Dusija Purportedly Mentioning RAM
`Only Once
`3. The Combination Purportedly Requiring
`Two Distinct Caches
`4. All Preferred Embodiments Supposedly
`Using a Flash Cache
`5. The Combination Purportedly Requiring
`“Moving” the Cache from Flash to RAM
`6. Reliability Purportedly Not Being a
`Motivation to Combine
`7. Dusija Purportedly Requiring That
`Toggling Be Avoided
`
`8. Dusija Purportedly Requiring That
`Rewrites Be Avoided
`9. The Combination Purportedly Degrading
`Performance
`10. The Combination Purportedly Being
`Contrary to Well-Known Design
`Principles
`11. A POSA’s Purported Lack of
`Reasonable Expectation of Success
`12. Petitioner’s Purported New Arguments
`13. Dr. Liu’s Purported Lack Of Credibility
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`Micron Ex. 1071, p. 24
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`The Petition’s Obviousness Theories Are Abundantly Clear
`
`- PO attempts to fault Petitioner’s discussion of Limitation [1.E] for referring back to its
`discussion of limitation [1.A.1].
`
`Sur-reply (Paper 23), 4.
`• But PO has provided no authority for the proposition that referring back to prior discussion
`in the Petition is improper.
`- The text for Limitation [1.E] clearly articulates Petitioner’s obviousness theory.
`- Limitation [1.A.1] clearly supports Petitioner’s obviousness theory.
`
`• PO’s contention that the Petition fails to specify the location of the RAM cache lacks merit
`for two reasons:
`1. The claims do not require the “random access volatile memory” to be in any specific location.
`
`2. As demonstrated in the previous slides, the Petition clearly explains that Dusija would have been
`understood to include a RAM cache in its controller or that it would have been obvious to do so.
`Reply (Paper 21), 3.
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`Micron Ex. 1071, p. 25
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`The Petition’s Obviousness Theories Are Abundantly Clear
`
`• Both PO’s Preliminary Response and the Institution Decision show that PO and the Board
`understood Petitioner’s theory to be that Dusija disclosed, or rendered obvious, RAM
`cache in its controller.
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`POPR (Paper 9), 47.
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`ID (Paper 11), 22.
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`Micron Ex. 1071, p. 26
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`PO’s Contention That Dusija Mentions RAM Only Once Is Wrong And
`Irrelevant
`- PO repeatedly asserts that Dusija “only mentions RAM once” and not in the context of
`caching.
`
`POR (Paper 16), 43; Sur-reply (Paper 23), 14.
`
`• PO entirely ignores Dusija’s incorporation of Paley, which expressly discloses a controller
`RAM cache.
`
`Slide 14; Petition (Paper 1), 34; Ex. 1009 (Liu Decl.) ¶¶ 132-34; Ex. 2015 (Liu Depo.), 68:9-12 (“from a POSA’s
`point of view, . . . [a] controller would include RAM, and that is disclosed through incorporation of Paley”).
`• Even if Dusija did not expressly disclose a controller RAM cache, the “cache” of Dusija’s
`paragraph [0112] “would have been understood to be Dusija’s controller RAM.”
`Ex. 1009 (Liu Decl.) ¶ 173; Petition (Paper 1), 48; Reply (Paper 21), 16-17; Ex. 1057 (Liu Reply Decl.) ¶¶ 22-
`26; Ex. 2015 (Liu Depo.), 67:8-15 (“regardless if explicitly mentioned,” a “POSA would understand that it
`[i.e., RAM] has to be there [i.e., in the controller]).
`• Even if Dusija’s cache would not have been understood to be controller RAM, it would
`certainly have been obvious to use controller RAM for Dusija’s cache.
`E.g., Petition (Paper 1), 36, 48; Ex. 1009 (Liu Decl.) ¶¶ 129-136, 173; Reply (Paper 21), 13.
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`Micron Ex. 1071, p. 27
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`Petitioner’s Theory Does Not Require Two Distinct Caches
`
`- PO argues that the Petition is unclear because Dusija uses a flash cache and the
`Petition never explains why a RAM cache would be used along with a flash cache.
`Sur-reply (Paper 23), 7; POR (Paper 16), 45.
`
`• This argument fails, because it falsely assumes that all Dusija embodiments use a flash
`cache, when they don’t.
`
`Reply (Paper 21), 10.
`• Petitioner’s theory relies on the embodiment of Dusija depicted in Figure 14 and described
`in paragraphs [0109]-[0126] as its starting point.
`E.g., Slides 11-13; Petition (Paper 1), 33, 42 (for Limitation [1.E], citing Dusija, [0111]-[0117]),
`47-48 (for Limitation [1.G.2], citing Dusija, [0111]-[0116] , [0119]-[0124]), 48-49 (for Limitation
`[1.H], citing Dusija, [0111]-[0116], [0119]-[0124]); Ex. 1009 (Liu Decl.) ¶¶ 129-36, 173-76.
`• As explained on the next slide, the embodiment on which Petitioner relies does not use a
`flash cache.
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`Micron Ex. 1071, p. 28
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`In View of Figures 16A-C, A POSA Would Have Understood Figures 14A-B
`To Not Include A Flash Cache
`
`• Dusija’s Figures 14A-B (and their
`associated description) use a cache but
`do not show the cache in the flash
`memory.
`• Dusija’s Figures 16A-C and 20A-C use a
`cache and show it in the flash memory.
`• A POSA would have understood Dusija’s
`decision to show Figures 14A-B without a
`cache in flash to mean that the cache
`was not in flash memory.
`• Particularly in light of Paley and Harari, a
`POSA would have immediately
`understood that the embodiment of
`Dusija shown in Fig. 14 would have a
`RAM cache in its controller or, at the very
`least, that it would have been obvious to
`do so.
`
`Reply (Paper 21), 15-16.
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`NO FLASH
`CACHE
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`FLASH CACHE
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`Micron Ex. 1071, p. 29
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`Some Preferred Embodiments In Dusija Do Not Use A Flash Cache
`
`- PO argues that “Dusija’s preferred embodiment” discloses a flash cache and, therefore,
`that a POSA would not have understood Figure 14 to contemplate a RAM cache.
`Sur-reply (Paper 23), 15-16.
`• But PO fails to recognize that Dusija discloses a preferred embodiment that does not
`include a flash cache.
`- For example, Figure 14 is described as “a preferred embodiment” and does not include a flash cache.
`
`• Even if all preferred embodiments of Dusija did use a flash cache (they do not), that is
`insufficient to avoid obviousness.
`
`Reply (Paper 21), 10.
`- “[O]ur case law does not require that a particular combination must be the preferred, or the most
`desirable, combination described in the prior art.”
`In re Fulton, 391 F.3d 1195, 1200 (Fed. Cir. 2004) (cited in Reply (Paper 21), 22).
`
`Ex. 1010 (Dusija), [0109].
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`Petitioner’s Theory Does Not Require Moving A Cache From Flash Memory
`To The Controller
`- PO asserts a POSA would not have been motivated to use Dusija with a controller RAM
`cache because, to PO, doing so would require “moving Dusija’s flash-based cache to be
`outside of flash memory.”
`
`Sur-reply (Paper 23), 6.
`• PO’s motivation-to-combine argument starts from the wrong premise because:
`- Dusija discloses embodiments that do not use a flash cache.
`Slides 28-30; Reply (Paper 21), 14-16.
`- A POSA would have understood these embodiments to use a controller RAM cache.
`Slides 10-15, 20.
`- Thus, Petitioner’s theory does not require moving a cache from flash memory to the controller.
`
`• Even if Dusija did require a flash cache in all embodiments (it does not), a POSA would
`have been motivated to modify Dusija to use a RAM cache at the controller.
`Slides 16, 21; Reply (Paper 21), 13.
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`Micron Ex. 1071, p. 31
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`Contrary to PO’s Argument, Reliability Is Relevant To Motivation To
`Combine
`- In response to Petitioner’s undisputed evidence that using RAM for Dusija’s cache would
`improve reliability (Reply at 8–9), PO argues that “Dusija does not disclose that reliability
`is a countervailing consideration.”
`
`Sur-Reply (Paper 23), 12.
`• As an initial matter, Dusija does disclose that reliability is “[a]n important consideration.”
`
`Ex. 1010 (Dusija), [0101].
`• What’s more, PO’s argument misunderstands obviousness law. Motivation to combine
`need not be found within the four corners of a prior art reference and, on the contrary,
`“requires[] consideration of common knowledge and common sense.”
`KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 421 (2007)
`(cited in Reply (Paper 21), 13).
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`Contradicting PO’s Teaching-Away Argument, Dusija Discloses A Preferred
`Embodiment That Toggles Data To The Controller
`- PO asserts that a POSA would not have been motivated to use Dusija with a controller RAM
`cache because “Dusija expressly teaches that any error checking should be performed by
`conducting a comparison at the data latches.”
`POR (Paper 16), 19.
`- PO further asserts that “Petitioner’s proposed modification would unnecessarily and
`unreasonably require an additional processing step (some mechanism to transfer the cached
`data to the flash memory).”
`
`Sur-reply (Paper 23), 14.
`
`• But PO does not dispute that Figure 14, a “preferred”
`embodiment, discloses toggling the full data block from
`the flash memory to the controller (and back, in the case of
`a data integrity test failure) for ECC.
`
`Reply (Paper 21), 18-19.
`
`TOGGLING
`REQUIRED
`
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`Ex. 1010 (Dusija), [0112], Figure 1.
`
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`Micron Ex. 1071, p. 33
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`Contradicting PO’s Teaching-Away Argument, Dusija Discloses
`Embodiments That Require Rewriting Data
`- PO asserts that Dusija teaches away from using a controller RAM cache because, by
`requiring that data be written in the event of a data integrity test failure, “Petitioner’s
`proposed modification would eliminate Dusija’s claimed advantage” of avoiding rewrites.
`POR (Paper 16), 44-45.
`
`• But PO does not dispute that Dusija
`describes embodiments which
`require rewriting data if errors are
`detected.
`
`Reply (Paper 21), 19-20.
`
`REWRITE
`REQUIRED
`
`REWRITE
`REQUIRED
`
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`Micron Ex. 1071, p. 34
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`PO’s Argument That Dusija Teaches Away From A RAM Cache Lacks Merit
`
`- PO argues that a RAM cache would degrade the performance of Dusija’s system and,
`therefore, a POSA would not have been motivated to use a RAM cache with Dusija.
`POR (Paper 16), 45-46.
`
`• But it is undisputed that:
`1. A RAM cache, having high write endurance, would improve Dusija’s reliability relative to a flash
`memory cache.
`
`Reply (Paper 21), 8-9.
`2. The purported “degrade[d] performance” caused by using a RAM cache with Dusija is equally
`present in embodiments expressly disclosed by Dusija (e.g., embodiments using ECC).
`Id., 11, 18-20.
`
`3. A POSA would have recognized that a flash memory cache would have performance
`disadvantages relative to a RAM cache in certain respects.
`
`Id., 20-22.
`“Far from requiring that a disclosed combination be preferred in the prior art in order to be
`motivating, this Court has held that ‘[a] known or obvious composition does not become
`patentable simply because it has been described as somewhat inferior to some other
`product for the same use.”
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`35
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`In re Fulton, 391 F.3d 1195, 1200 (Fed. Cir. 2004).
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`Micron Ex. 1071, p. 35
`Micron v. Vervain
`IPR2021-01550
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`Contrary to PO’s Teaching-Away Argument, A Flash Memory Cache Is Not
`“Fundamental” To Dusija
`- PO argues that a POSA would not have been motivated to use controller RAM for
`Dusija’s cache because a flash memory cache allegedly is “fundamental” to Dusija.
`POR (Paper 16), 43-44, 46.
`• But Petitioner explained, and PO does not dispute, that the purported advantages of using
`a flash memory cache—avoiding toggling and rewrites—cannot be fundamental to Dusija
`because Dusija discloses embodiments that perform toggling and rewriting.
`Reply (Paper 21), 18-19; Sur-Reply (Paper 23), 11.
`• PO’s sole remaining basis for a flash memory cache being “fundamental” to Dusija is
`the assertion that Dusija discloses only a flash memory cache. Even if that were true (it is
`not, see Reply at 14-16), it is of no consequence because Petitioner’s theory is
`obviousness, not anticipation.
`
`Reply (Paper 21), 10.
`
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`Micron Ex. 1071, p. 36
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`PO’s “Well-Known Design Principles” Argument Is Not Supported By Any
`Evidence
`- PO’s Response asserts that a POSA would not have been motivated to use a RAM
`cache in Dusija because “an off-chip comparison would have been contrary to well-
`known design principles regarding fast cache operation.”
`
`POR (Paper 16), 55 (emphasis added).
`• Although the POR cites Dr. Khatri’s declaration, he only states that an on-chip comparison
`is “consistent with well-known design criteria.”
`
`Ex. 2014 (Khatri Decl.), ¶ 97 (emphasis added).
`
`• In fact:
`1. PO’s assertion that RAM caches are contrary to well-known design principles is contradicted by
`the common and well-understood use of RAM caches in SSDs.
`Petition (Paper 1), 33-35; Reply (Paper 21), 24 (citing Ex. 1009 (Liu Decl.), ¶ 130; Ex. 1057, (Liu Reply Decl.), ¶¶ 64–71).
`2. The Sartore reference, on which PO relies for its argument, has nothing to do with flash
`memory.
`
`Reply (Paper 21), 24; Ex. 1057 (Liu Reply Decl.), ¶¶ 67–71; Ex. 2017 (Sartore).
`
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`Micron Ex. 1071, p. 37
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`PO’s Nonobviousness Argument Is Contrary To KSR
`
`“When a patent claims a structure already known in the prior art that is
`altered by the mere substitution of one element for another known in the
`field, the combination must do more than yield a predictable result.”
`
`KSR v. Teleflex, 550 U.S. 398, 416 (2007).
`
`• Here, PO claims a structure already known in the prior art (Dusija’s system) that is altered
`by the mere substitution of one element (the flash memory cache) for another known in the
`field (a RAM cache), but the combination undisputedly does not do more than yield a
`predictable result.
`
`Reply (Paper 21), 12-13.
`
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`Micron Ex. 1071, p. 38
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`A POSA Would Have Had A Reasonable Expectation Of Success In Using A
`Controller RAM Cache With Dusija
`- PO asserts, without any support, that Petitioner has not demonstrated “a reasonable
`expectation of success regarding its obviousness implementation.”
`
`Sur-Reply (Paper 23), 5.
`
`• But the Board already considered and rejected that argument.
`
`• PO does not dispute the Board’s initial determination that using a controller RAM cache
`was considered “typical” to a POSA, nor has PO made any argument that would disturb the
`Board’s conclusion at the Institution stage.
`
`Petition (Paper 1), 36, 49; Reply (Paper 21), 8-9.
`
`ID (Paper 11), 30.
`
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`Micron Ex. 1071, p. 39
`Micron v. Vervain
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`Petitioner’s Citation To Claim 3 Is Not An Improper New Argument
`
`- PO asserts that, in responding to PO’s argument that the Petition did not explain the
`location of Dusija’s RAM cache, the Reply’s citation to Dusija’s dependent claim 3 was
`an improper new argument.
`
`POR (Paper 16), 34.
`
`• Petitioner’s citation to claim 3 was “a legitimate reply to evidence introduced by the patent
`owner.”
`
`Apple Inc. v. Andrea Elecs. Corp., 949 F.3d 697, 706–07 (Fed. Cir. 2020).
`
`• PO’s reliance on Intelligent Bio-Systems misses the mark because the argument at issue
`there included new references and new grounds of unpatentability. Neither is present here.
`
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`Micron Ex. 1071, p. 40
`Micron v. Vervain
`IPR2021-01550
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`Petitioner’s Discussion Of Reliability Is Not An Improper New Argument
`
`- PO asserts that the Reply’s discussion of reliability was an improper new argument.
`Sur-Reply (Paper 23), 12.
`
`• But Petitioner’s reliability argument is merely a reiteration of the evidence, raised in the
`Petition, that RAM caches have “high write endurance” relative to flash memory caches.
`Petition (Paper 1), 16.
`• To the extent the Reply can be said to introduce “new evidence,” such evidence is
`permissible “to document of the knowledge that skilled artisans would bring to bear in
`reading the prior art identified as producing obviousness.”
`Anacor Pharmaceuticals, Inc. v. Iancu, 89 F.3d 1372, 1380-81 (Fed. Cir. 2018).
`
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`Micron Ex. 1071, p. 41
`Micron v. Vervain
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`Petitioner’s Analogy To KSR Is Not An Improper New Argument
`
`- PO asserts that Petitioner’s analogy to KSR, and in particular Petitioner’s note that “the
`challenged patent never suggests any unpredictable result from the use of a RAM
`cache,” is an improper new argument.
`
`Sur-Reply (Paper 23), 14.
`
`• But “the petitioner in an inter partes review proceeding may introduce new evidence after
`the petition stage if the evidence is a legitimate reply to evidence introduced by the patent
`owner.”
`
`Apple Inc. v. Andrea Elecs. Corp., 949 F.3d 697, 706-07 (Fed. Cir. 2020).
`
`• Here, Petitioner’s analogy to KSR is properly in response to arguments in the POR that the
`recited “random access volatile memory” renders the claims non-obvious.
`
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`Micron Ex. 1071, p. 42
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`PO’s Attacks On Dr. Liu Are Meritless And Immaterial
`
`- PO spends pages of its sur-reply attacking Dr. Liu’s characterization of “preferred” and
`“alternative” embodiments as “nonsensical.”
`
`Sur-Reply (Paper 23), 21-22.
`
`• Dr. Liu’s point is straightforward:
`1. PO throughout these proceedings has made much of Dusija’s statement in paragraph [0131] that “In
`the preferred embodiment . . . the incoming data is cached in the first section of the first portion.”
`E.g., Sur-Reply (Paper 23), 15 (quoting Ex. 1010 (Dusija), [0131]) (emphasis added).
`2. Although paragraph [0131] uses the term “preferred,” paragraph [0127] establishes that the disclosure
`in paragraphs [0127]-[0131] is a disclosure of “an alternative embodiment.” Dusija, [0127]. So, as Dr.
`Liu explains, the disclosure in paragraphs [0127]-[0131] is the preferred embodiment of the alternative
`embodiment.
`
`Ex. 2015 (Liu Depo.),44:17–20.
`• PO has not explained the significance of its apparent quibble with Dr. Liu’s
`“preferred”/“alternative” embodiment testimony to the outcome of this case—it has none.
`
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`Micron Ex. 1071, p. 43
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`PO’s Attacks On Dr. Liu Are Meritless And Immaterial
`- PO asserts that Dr. Liu’s testimony as to whether Dusija’s controller includes RAM “should be
`discounted” as “unreliable” and “changing.”
`
`Sur-Reply (Paper 23), 23.
`• Dr. Liu’s testimony was consistent. He explained that while, in the abstract, an SSD could
`conceivably be created without the use of RAM, Ex. 2020 (Liu Reply Depo.) at 68:5-19, Dusija’s
`system would necessarily include RAM, id. at 208:25-209:7. P
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