(12) United States Patent
`Harari et al.
`
`USOO6523132B1
`US 6,523,132 B1
`(10) Patent No.:
`Feb. 18, 2003
`(45) Date of Patent:
`
`(54) FLASH EEPROM SYSTEM
`(75) Inventors: Eliyahou Harari, Los Gatos, CA (US);
`Robert D. Norman, San Jose, CA
`(US); Sanjay Mehrotra, Milpitas, CA
`(US)
`(73) Assignee: SanDisk Corporation, Sunnyvale, CA
`(US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(*) Notice:
`
`(21) Appl. No.: 09/657,482
`(22) Filed:
`Sep. 8, 2000
`Related U.S. Application Data
`(60) Continuation of application No. 08/789,421, filed on Jan. 29,
`1997, now Pat. No. 6,149,316, which is a continuation of
`application No. 08/174,768, filed on Dec. 29, 1993, now Pat.
`No. 5,602987, which is a continuation of application No.
`07/963,838, filed on Oct. 20, 1992, now Pat. No. 5,297,148,
`which is a division of application No. 07/337,566, filed on
`Apr. 13, 1989, now abandoned.
`(51) Int. Cl. ................................................. G06F 11/00
`(52) U.S. Cl. ................
`... 714/8; 714/723; 714/710
`(58) Field of Search ............................ 714/8, 723, 710;
`365/185.16, 185.25, 185.02, 230.06
`
`(56)
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`(57)
`ABSTRACT
`A system of Flash EEprom memory chips with controlling
`circuits serves as non-volatile memory such as that provided
`by magnetic disk drives. Improvements include Selective
`multiple Sector erase, in which any combinations of Flash
`Sectors may be erased together. Selective Sectors among the
`Selected combination may also be de-Selected during the
`erase operation. Another improvement is the ability to remap
`and replace defective cells with Substitute cells. The remap
`ping is performed automatically as Soon as a defective cell
`is detected. When the number of defects in a Flash sector
`becomes large, the whole Sector is remapped. Yet another
`improvement is the use of a write cache to reduce the
`number of writes to the Flash EEprom memory, thereby
`minimizing the StreSS to the device from undergoing too
`many write/erase cycling.
`
`27 Claims, 5 Drawing Sheets
`
`
`
`
`
`
`
`705
`
`
`
`CACHE
`BUFFER
`
`DATA
`
`HOST
`
`
`
`MEMORY
`N
`CONTRO
`
`33
`
`
`
`
`
`FLASH
`MEMORY
`
`HPE, Exh. 1008, p. 1
`
`

`

`US 6,523,132 B1
`Page 2
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`Oct. 28, 1972 to Dec. 31, 1972, Westinghouse Defense and
`electronic Systems Center.
`Brewer, J.E., “Block Oriented Random Access Memory
`(BORAM): Chip Line Startup Progress Report", Mar. 1975,
`Westinghouse Defense and electronic Systems Center.
`
`HPE, Exh. 1008, p. 4
`
`

`

`US 6,523,132 B1
`Page 5
`
`Brewer, J.E., “Block Oriented Random Access Memory
`(BORAM): Microelectronics Design Plan”, Aug. 15, 1975,
`Westinghouse Defense and electronic Systems Center.
`Shirota et al., “A New NAND Cell for Ultra High Density
`5V-Only EEPROMs”, 1988 Symposium on VLSI Technol
`ogy, May 10-13, 1988, p. 33-34.
`Brewer J.E., “MNOS BORAM Manufacturing Methods and
`Technology Progect”, Westinghouse Electric Corporation,
`Jan. 1982: final Technical Report for Period Apr. 1980 to
`Jan. 1982.
`Brewer,et al., “Nonvolatile Metal-Nitride-Oxide Semicon
`ductor BORAM. Twelfth Annual Tri-Service Manufactur
`ing Technology Conference, Oct. 19-23, 1980, p. 2-10.
`Ask, Henry, R., “Solid-State Flight Data Recorder”, 1980
`Government Microcircuit Applications Conference, Nov.
`19–21, 1980., p. 1–2.
`
`Brewer J.E., “MNOS BORAM Manufacturing Methods and
`Technology Progect”, Westinghouse Electric Corporation,
`Feb. 1980. final Technical Report for Period Jul. 1979 to
`Nov. 1979.
`Farrow, Raymond, “Reaping the MT Program Benefits”,
`U.S. Army ManTech Journal, vol. 5, No. 1, 1980.
`“BORAM 6008: Nonvolatile Integrated Circuit Block-Ori
`ented Random-Access Memory Chip” Westinghouse
`Defense and electronic Systems Center, Jun. 1981, pp. 1-10.
`Scientific Micro Systems, Inc., OMTI AT Compatible Con
`troller Series-Reference Manual, Publication No.
`3001774-0001, (1988) pps. 1-1 to 1-4, and 2–1, 2–8 and
`2-9.
`Intel Corporation, 27F256, 256K (32Kx8) CMOS Flash
`Memory, May 1988, pp. 1-21.
`* cited by examiner
`
`HPE, Exh. 1008, p. 5
`
`

`

`U.S. Patent
`
`Feb. 18, 2003
`
`Sheet 1 of 5
`
`US 6,523,132 B1
`
`T/373.
`FLASH
`EEPROM
`E. 1-29
`
`2
`MCRO
`PROCESSOR
`
`
`
`23
`
`
`
`t
`
`I/O
`DEVICES)
`
`FIG. 1A
`
`
`
`SYSTEM
`ADDRESS/DATA
`BUS
`
`3.
`
`SYSTEM
`CONTROL LINES
`
`33
`TTEEPRONARY TWTTTTTT
`57
`
`TO OTHER
`EEPROM
`ARRAYS
`
`
`
`CHIP
`SELECT
`
`FIG.1B
`
`HPE, Exh. 1008, p. 6
`
`

`

`U.S. Patent
`
`Feb. 18, 2003
`
`Sheet 2 of 5
`
`US 6,523,132 B1
`
`3.
`
`
`
`CONTROLLER
`
`FLASH MEMORY CHIPS
`
`-----
`axYxyYYANYSS
`
`Na YaYa YaYaNNYSYN
`
`203
`
`
`
`F- 237
`205
`SET ERASE EN
`
`
`
`24
`
`/
`239
`
`SYYYayya YYYY
`
`SECTORS TO
`BE ERASED
`
`
`
`
`
`
`
`
`
`
`
`
`
`SECTOR
`
`2
`
`
`
`233 235 (22 239
`Ele see
`t
`SECTOR
`is a 23
`I
`see
`sta
`
`We (ERASE VOLAGE) 209
`
`FIG.3A
`
`HPE, Exh. 1008, p. 7
`
`

`

`U.S. Patent
`
`Feb. 18, 2003
`
`Sheet 3 of 5
`
`US 6,523,132 B1
`
`()
`
`POINT TO SECTOR TO BE ERASED
`
`(2)
`
`(3)
`
`(4)
`
`(5)
`
`(6)
`
`(7)
`
`(8)
`
`(9)
`
`(0)
`
`(l)
`
`TAG SECTOR POINTED TO BY
`SETTING THE ASSOCATED
`ERASE ENABLE REGISTER
`
`
`
`
`
`S THERE
`MORE SECTOR TO BE
`ERASED
`
`
`
`NO
`INTATE ERASE SEQUENCE WITH
`A GLOBAL ENABLE ERASE COMMAND
`
`APPLY A PULSE OF ERASE WOLAGE
`ONLY TO THE TAGGED SECTORS
`
`READ AND VERIFY THAT EACH
`SECTOR IS IN ERASED STATE
`
`
`
`STER
`ANY SECTOR
`ERIFED,
`
`POINT TO SECTOR TO
`BE REMOVED FROM ERASE
`
`UNTAG SECTOR POINTED TO
`BY CLEARING THE ASSOCATED
`ERASE ENABE REGISTER
`
`ARE ALL
`SECTORS
`ERFED
`YES
`END ERASE SEQUENCE BY
`WITHDRAWINGENABLE ERASE COMMAND FIG.4
`
`HPE, Exh. 1008, p. 8
`
`

`

`U.S. Patent
`
`Feb. 18, 2003
`
`Sheet 4 of 5
`
`US 6,523,132 B1
`
`SECTOR PARTITION
`
`3. M" CONTROLLER MEMORY ARRAY
`
`53
`
`33
`
`
`
`
`
`5
`COMMAND
`SEQUENCER
`
`ADDRESS
`GENERATOR
`
`COMPARATOR - DEFECT POINTER
`MEMORY FILE/
`HEADER COMPARE
`ALTERNATE
`DEFECISSPARES
`
`
`
`READ DATA PATH CONTROL
`FIG.6
`
`ADDR/DATA
`
`
`
`
`
`525
`DATA
`
`HPE, Exh. 1008, p. 9
`
`

`

`U.S. Patent
`
`Feb. 18, 2003
`
`Sheet 5 of 5
`
`US 6,523,132 B1
`
`o DEFECT POINTER
`MEMORY FELE/
`HEADER COMPARE
`ALTERNATE
`DEFECTS (SPARES)
`
`WRITE DATA PATH CONTROL
`FIG.7
`
`Tolv
`
`705
`
`DATA
`
`
`
`
`
`lost
`
`INTERFACE
`
`
`
`
`
`"hi
`MEMORY
`FE TAG, TIMEN
`ANDTIME
`CONTRO
`SAMP
`
`
`
`
`
`TIMERS
`
`FIG.8
`
`HPE, Exh. 1008, p. 10
`
`

`

`1
`FLASH EEPROM SYSTEM
`
`US 6,523,132 B1
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`This is a continuation of application Ser. No. 08/789,421,
`filed Jan. 29, 1997, now U.S. Pat. No. 6,149,316; which in
`turn is a continuation of Ser. No. 08/174,768, filed Dec. 29,
`1993, now U.S. Pat. No. 5,602987; which in turn is a
`continuation of Ser. No. 07/963,838; filed Oct. 20, 1992,
`now U.S. Pat. No. 5,297,148; which in turn is a divisional of
`Ser. No. 07/337,566; filed Apr. 13, 1989, now abandoned.
`BACKGROUND OF THE INVENTION
`This invention relates generally to Semiconductor electri
`cally erasable programmable read only memories (EEprom),
`and Specifically to a System of integrated circuit Flash
`EEprom chips.
`Computer Systems typically use magnetic disk drives for
`mass Storage of data. However, disk drives are disadvanta
`geous in that they are bulky and in their requirement for high
`precision moving mechanical parts. Consequently they are
`not rugged and are prone to reliability problems, as well as
`consuming Significant amounts of power. Solid State
`memory devices such as DRAM's and SRAM's do not
`Suffer from these disadvantages. However, they are much
`more expensive, and require constant power to maintain
`their memory (volatile). Consequently, they are typically
`used as temporary Storage.
`EEprom's and Flash EEprom's are also solid state
`memory devices. Moreover, they are nonvolatile, and retain
`their memory even after power is shut down. However,
`conventional Flash EEprom's have a limited lifetime in
`terms of the number of write (or program)/erase cycles they
`can endure. Typically the devices are rendered unreliable
`after 10° to 10 write/erase cycles. Traditionally, they are
`typically used in applications where Semi-permanent Storage
`of data or program is required but with a limited need for
`reprogramming.
`Accordingly, it is an object of the present invention to
`provide a Flash EEprom memory system with enhanced
`performance and which remains reliable after enduring a
`large number of write/erase cycles.
`It is another object of the present invention to provide an
`improved Flash EEprom System which can Serve as non
`Volatile memory in a computer System.
`It is another object of the present invention to provide an
`improved Flash EEprom System that can replace magnetic
`disk Storage devices in computer Systems.
`It is another object of the present invention to provide a
`Flash EEprom System with improved erase operation.
`It is another object of the present invention to provide a
`Flash EEprom system with improved error correction.
`It is yet another object of the present invention to provide
`a Flash EEprom with improved write operation that mini
`mizes stress to the Flash EEprom device.
`It is still another object of the present invention to provide
`a Flash EEprom System with enhanced write operation.
`SUMMARY OF THE INVENTION
`These and additional objects are accomplished by
`improvements in the architecture of a System of EEprom
`chips, and the circuits and techniques therein.
`According to one aspect of the present invention, an array
`of Flash EEprom cells on a chip is organized into Sectors
`
`15
`
`25
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`Such that all cells within each Sector are erasable at once. A
`Flash EEprom memory System comprises one or more Flash
`EEprom chips under the control of a controller. The inven
`tion allows any combination of Sectors among the chips to
`be selected and then erased simultaneously. This is faster
`and more efficient than prior art Schemes where all the
`Sectors must be erased every time or only one Sector at a time
`can be erased. The invention further allows any combination
`of Sectors Selected for erase to be deselected and prevented
`from further erasing during the erase operation. This feature
`is important for Stopping those Sectors that are first to be
`erased correctly to the "erased State from Over erasing,
`thereby preventing unnecessary StreSS to the Flash EEprom
`device. The invention also allows a global de-select of all
`Sectors in the System So that no Sectors are Selected for erase.
`This global reset can quickly put the System back to its initial
`State ready for Selecting the next combination of Sectors for
`erase. Another feature of the invention is that the Selection
`is independent of the chip Select Signal which enables a
`particular chip for read or write operation. Therefore it is
`possible to perform an erase operation on Some of the Flash
`EEprom chips while read and write operations may be
`performed on other chips not involved in the erase operation.
`According to another aspect of the invention, improved
`error correction circuits and techniques are used to correct
`for errors arising from defective Flash EEprom memory
`cells. One feature of the invention allows defect mapping at
`cell level in which a defective cell is replaced by a substitute
`cell from the same Sector. The defect pointer which connects
`the address of the defective cell to that of the Substitute cell
`is Stored in a defect map. Every time the defective cell is
`accessed, its bad data is replaced by the good data from the
`Substitute cell.
`Another feature of the invention allows defect mapping at
`the sector level. When the number of defective cells in a
`Sector exceeds a predetermined number, the Sector contain
`ing the defective cells is replaced by a Substitute Sector.
`An important feature of the invention allows defective
`cells or defective Sectors to be remapped as Soon as they are
`detected thereby enabling error correction codes to
`adequately rectify the relatively few errors that may crop up
`in the System.
`According to yet another aspect of the present invention,
`a write cache is used to minimize the number of writes to the
`Flash EEprom memory. In this way the Flash EEprom
`memory will be Subject to fewer StreSS inducing write/erase
`cycles, thereby retarding its aging. The most active data files
`are written to the cache memory instead of the Flash
`EEprom memory. Only when the activity levels have
`reduced to a predetermined level are the data files written
`from the cache memory to the Flash EEprom memory.
`Another advantage of the invention is the increase in write
`throughput by Virtue of the faster cache memory.
`According to yet another aspect of the present invention,
`one or more printed circuit cards are provided which contain
`controller and EEprom circuit chips for use in a computer
`System memory for long term, non-volatile Storage, in place
`of a hard disk System, and which incorporate various of the
`other aspects of this invention alone and in combination.
`Additional objects, features, and advantages of the present
`invention will be understood from the following description
`of its preferred embodiments, which description should be
`taken in conjunction with the accompanying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1A is a general microprocessor System including the
`Flash EEprom memory System of the present invention;
`
`HPE, Exh. 1008, p. 11
`
`

`

`US 6,523,132 B1
`
`3
`FIG. 1B is Schematic block diagram illustrating a System
`including a number of Flash EEprom memory chips and a
`controller chip;
`FIG. 2 is a schematic illustration of a system of Flash
`EEprom chips, among which memory Sectors are Selected to
`be erased;
`FIG. 3A is a block circuit diagram in the controller for
`implementing Selective multiple Sector erase according to
`the preferred embodiment;
`FIG. 3B shows details of a typical register used to select
`a Sector for erase as shown in FIG. 2A,
`FIG. 4 is a flow diagram illustrating the erase Sequence of
`Selective multiple Sector erase,
`FIG. 5 is a Schematic illustration showing the partitioning
`of a Flash EEprom Sector into a data area and a Spare
`redundant area;
`FIG. 6 is a circuit block diagram illustrating the data path
`control during read operation using the defect mapping
`scheme of the preferred embodiment;
`FIG. 7 is a circuit block diagram illustrating the data path
`control during the write operation using the defect mapping
`scheme of the preferred embodiment;
`FIG. 8 is a block diagram illustrating the write cache
`circuit inside the controller.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`15
`
`25
`
`4
`The EEprom array 33 includes a number of EEprom
`integrated circuit chips 43, 45, 47, etc. Each includes a
`respective chip select and enable line 49, 51 and 53 from
`interface circuits 40. The interface circuits 40 also act to
`interface between the serial data lines 35, 37 and a circuit 55.
`Memory location addresses and data being written into or
`read from the EEprom chips 43, 45, 47, etc. are communi
`cated from a bus 55, through logic and register circuits 57
`and thence by another bus 59 to each of the memory chips
`43, 45, 47 etc.
`The bulk storage memory 29 of FIGS. 1A and 1B can be
`implemented on a Single printed circuit card for moderate
`memory sizes. The various lines of the system buses 39 and
`41 of FIG. 1B are terminated in connecting pins of such a
`card for connection with the rest of the computer System
`through a connector. Also connected to the card and its
`components are various standard power Supply Voltages (not
`shown).
`For large amounts of memory, that which is conveniently
`provided by a single array 33 may not be enough. In Such a
`case, additional EEprom arrays can be connected to the
`serial data lines 35 and 37 of the controller chip 31, as
`indicated in FIG. 1B. This is preferably all done on a single
`printed circuit card but if Space is not Sufficient to do this,
`then one or more EEprom arrayS may be implemented on a
`Second printed circuit card that is physically mounted onto
`the first and connected to a common controller chip 31.
`Erase of Memory Structures
`In System designs that Store data in files or blocks the data
`will need to be periodically