(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2005/0204091A1
`Kilbuck et al.
`(43) Pub. Date:
`Sep. 15, 2005
`
`US 20050204-091A1
`
`(54) NON-VOLATILE MEMORY WITH
`SYNCHRONOUS DRAM INTERFACE
`
`(76) Inventors: Kevin M. Kilbuck, Boise, ID (US);
`David Eggleston, San Jose, CA (US)
`s
`s
`Correspondence Address:
`LEFFERT JAY & POLGLAZE, PA.
`P.O. BOX 581009
`MINNEAPOLIS, MN 55458-1009 (US)
`9
`(21) Appl. No.:
`10/798,795
`
`(22) Filed:
`
`Mar. 11, 2004
`Publication Classification
`
`(51) Int. Cl. .................................................. G06F 12/00
`(52) U.S. Cl. .............................................................. 711/103
`
`ABSTRACT
`(57)
`A high density non-volatile memory System, card, and
`device is described that incorporates a Synchronous inter
`face. This is accomplished through use of an external or
`embedded controller and/or memory buffer to manage the
`high density non-volatile memory device(s) to present it as
`a conventional memory device having a Synchronous inter
`face that is accessible by row and column address. This
`allows the high density non-volatile memory to Support
`in-place code execution and allows it to be booted from.
`Additionally, this incorporation eliminates the overhead of
`drivers and/or operating System Support required to utilize
`and present conventional high density non-volatile memory
`devices and moves it internal to the memory device. This
`Simplifies the use and design effort in the overhead and
`Specialized interfacing of high density non-volatile memo
`ries and in particular, NAND architecture Flash memories,
`while reducing the production cost through use of leSS
`expensive high density non-volatile memory.
`
`128
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`Processor
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`Array Bank
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`122
`Sense Amplifiers
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`Control
`110
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`Ct.
`Reg.
`114
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`HPE, Exh. 1016, p. 1
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`Patent Application Publication Sep. 15, 2005 Sheet 1 of 4
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`HPE, Exh. 1016, p. 2
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`Patent Application Publication Sep. 15, 2005 Sheet 2 of 4
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`HPE, Exh. 1016, p. 3
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`Patent Application Publication Sep. 15, 2005 Sheet 3 of 4
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`US 2005/0204091 A1
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`HPE, Exh. 1016, p. 4
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`Patent Application Publication Sep. 15, 2005 Sheet 4 of 4
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`HPE, Exh. 1016, p. 5
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`US 2005/0204091 A1
`
`Sep. 15, 2005
`
`NON-VOLATILE MEMORY WITH
`SYNCHRONOUS DRAM INTERFACE
`
`TECHNICAL FIELD OF THE INVENTION
`0001. The present invention relates generally to memory
`devices and in particular the present invention relates to
`non-volatile memory devices with Synchronous interfaces.
`
`BACKGROUND OF THE INVENTION
`0002 Memory devices are typically provided as internal
`Storage areas in a computer. The term memory identifies data
`Storage that comes in the form of integrated circuit chips.
`There are Several different types of memory used in modern
`electronics, one common type is RAM (random-access
`memory). RAM is characteristically found in use as main
`memory in a computer environment. RAM refers to read and
`write memory; that is, you can both write data into RAM and
`read data from RAM. This is in contrast to ROM (read-only
`memory), which permits you only to read data. Most RAM
`is Volatile, which means that it requires a steady flow of
`electricity to maintain its contents.
`0.003 Computers almost always contain a small amount
`of ROM that holds instructions for starting up the computer,
`typically called a basic input output system (BIOS). Unlike
`RAM, ROM generally cannot be written to by a user. An
`EEPROM (electrically erasable programmable read-only
`memory) is a special type of non-volatile ROM that can be
`erased and programmed by exposing it to an electrical
`charge. EEPROM comprise a large number of memory cells
`having electrically isolated gates (floating gates). Data is
`Stored in the memory cells in the form of charge on the
`floating gates. Charge is transported to or removed from the
`floating gates by Specialized programming and erase opera
`tions.
`0004 Yet another type of non-volatile memory is a Flash
`memory. A Flash memory is a type of EEPROM that can be
`erased and reprogrammed in blocks instead of one byte at a
`time. A typical Flash memory comprises a memory array,
`which includes a large number of memory cells. Each of the
`memory cells includes a floating gate field-effect transistor
`capable of holding a charge. The data in a cell is determined
`by the presence or absence of the charge in the floating gate.
`The cells are usually grouped into Sections called "erase
`blocks.” The memory cells of a Flash memory array are
`typically arranged into a “NOR” architecture (each cell
`directly coupled to a bitline) or a “NAND” architecture
`(cells coupled into "strings” of cells, Such that each cell is
`coupled indirectly to a bitline and requires activating the
`other cells of the String for access, but allowing for a higher
`cell density). Each of the cells within an erase block can be
`electrically programmed in a random basis by charging the
`floating gate. The charge can be removed from the floating
`gate by a block erase operation, wherein all floating gate
`memory cells in the erase block are erased in a Single
`operation.
`0005) A problem with NAND Flash memory is that with
`its higher density and configuration it requires Specialized
`interfacing and interaction to utilize; many available pro
`ceSSors and memory controllers do not directly Support
`NAND Flash memory whereas NOR Flash memory support
`is more commonly available. Typically this means that a
`majority of the control and management of a NAND Flash
`
`memory device is external from the memory device and in
`expensive dedicated hardware or a Software driver that is
`executed on a coupled memory controller or processor. In
`addition, as multiple floating gate memory cell transistors
`are coupled together in the strings of a NAND Flash memory
`array, individual errors in the array are more difficult to
`correct for than in NOR Flash memory. This issue becomes
`even more of a problem when multi-level memory cells
`(MLCs), which store multiple memory states in each cell,
`are utilized. To compensate for this and to take advantage of
`the inherent higher array density, NAND Flash memory
`typically utilizes error correction codes (ECC) and/or are
`interfaced to and presented as a mass Storage device, Such as
`a magnetic disk. In this manner the errors of a NAND Flash
`memory device can be addressed by the operating System/
`host/driver/firmware and/or the file system that the Flash
`device is formatted with. In addition, wear leveling routines
`are also typically incorporated in the interface/drivers for
`NAND Flash memory device(s) to distribute writes and help
`prevent early wear out of the device(s). However, NAND
`architecture Flash memory devices are also generally leSS
`expensive and of larger capacity than a corresponding NOR
`architecture Flash memory device, making them desirable
`for System designers.
`0006 AS NAND architecture Flash memories are of
`higher array density they generally have slower initial data
`access times and typically are arranged to transfer large
`blocks of data with each access request. These features make
`the use of NAND architecture Flash memories for large
`numbers of non-Sequential individual data word accesses
`prohibitive. Because of this code and data are typically
`copied from a NAND architecture Flash memory device into
`a RAM memory and then executed. Code execution is more
`readily accomplished with NOR architecture Flash memory
`devices, which contain a more conventional array Structure
`and transfer Smaller data blocks on each access, allowing
`them to be booted/executed from. It is noted that other types
`of high density non-volatile memory that share many of the
`characteristics of NAND architecture Flash (slow access
`Speeds, large data Volume, non-Standardized interfacing and
`drivers, etc.) including, but not limited to, Polymer Memory,
`Ferroelectric Random Access Memory (FeRAM), Ovionics
`Unified Memory (OUM), Magnetoresistive Random Access
`Memory (MRAM), Molecular Memory, and Carbon Nano
`tube Memory are also known.
`0007) A synchronous DRAM (SDRAM) is a type of
`DRAM that can run at much higher clock speeds than
`conventional DRAM memory. SDRAM's can be accessed
`quickly, but are volatile. SDRAM synchronizes itself with a
`CPU's bus and is capable of running at 100 MHZ, 133
`MHZ, 166 MHZ, or 200 MHZ, about three or four times
`faster than conventional FPM (Fast Page Mode) RAM, and
`about two to three times as fast EDO (Extended Data
`Output) DRAM and BEDO (Burst Extended Data Output)
`DRAM. An extended form of SDRAM that can transfer a
`data value on the rising and falling edge of the clock signal
`is called double data rate SDRAM (DDR SDRAM, or
`simply, DDR). Other forms of synchronous memory inter
`faces are also utilized in modern memories and memory
`Systems, including, but not limited to, double data rate 2
`SDRAM (DDR2), graphics double data rate (GDDR),
`graphics double data rate 2 (GDDR2), and Rambus DRAM
`(RDRAM).
`
`HPE, Exh. 1016, p. 6
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`

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`US 2005/0204091 A1
`
`Sep. 15, 2005
`
`0008 Many computer systems are designed to operate
`using one or more forms of synchronous DRAM, but would
`benefit from non-volatile memory. A synchronous NOR
`Flash memory has been designed that allows for a non
`volatile memory device with an SDRAM interface.
`Although knowledge of the function and internal Structure of
`a synchronous NOR Flash memory is not essential to
`understanding the present invention, a detailed discussion is
`included in U.S. patent application Ser. No. 09/627,682 filed
`Jul. 28, 2000 and titled, “Synchronous Flash Memory.”
`0009 For the reasons stated above, and for other reasons
`stated below which will become apparent to those skilled in
`the art upon reading and understanding the present Specifi
`cation, there is a need in the art for a Synchronous non
`Volatile memory device or Subsystem, in particular one that
`has an SDRAM or DDR compatible interface and allows for
`in-place code execution and/or can be used to boot from.
`
`SUMMARY
`0.010 The above-mentioned problems with non-volatile
`memories, in-place code execution, Synchronous memory
`interfaces, and other problems are addressed by the present
`invention and will be understood by reading and studying
`the following specification.
`0.011
`Although described in relation to NAND architec
`ture Flash memory, the various embodiments relate gener
`ally to non-volatile memory devices and Subsystems that
`incorporate a Synchronous interface. Memory device
`embodiments of the present invention utilize an external or
`embedded controller and/or memory buffer to present the
`non-volatile memory device(s) as a conventional memory
`device having a Synchronous interface. This allows the
`non-volatile memory embodiments of the present invention
`to Support in-place code execution and allow them to be
`booted from. Additionally, the memory buffer allows for
`caching/buffering of data read and/or write accesses, allow
`ing non-volatile memory devices of the present invention to
`be quickly accessed as if they were conventional Synchro
`nous RAM memory devices.
`0012. In one embodiment of the present invention, a
`non-volatile memory device eliminates the requirement of
`external drivers, customized NAND interface port on a
`memory controller or microprocessor, and/or operating Sys
`tem Support to utilize a specialized high density non-volatile
`memory device, and in particular, a NAND architecture
`Flash memory device. This simplifies the use and design
`effort of high density non-volatile memories by reducing
`Specialized interfacing, while reducing the Overall produc
`tion cost through allowing use of a less expensive NAND
`architecture Flash memory or other high density non-volatile
`memory where a more expensive memory device would
`normally be required. In another embodiment of the present
`invention, a NAND architecture Flash card or subsystem has
`a Synchronous interface. In a further embodiment of the
`present invention, a NAND architecture Flash memory
`device, card, or subsystem has an SDRAM compatible
`interface. In yet a further embodiment of the present inven
`tion, individual data words of a NAND architecture Flash
`memory device, card, or Subsystem may be accessed in a
`non-prohibitive manner. In another embodiment of the
`present invention, a NAND architecture Flash memory
`device, card, or Subsystem is accessed by a row and column
`
`address. In yet another embodiment of the present invention,
`a NAND architecture Flash memory device, card, or Sub
`System contains a RAM buffer allowing in-place code
`execution and/or read/write access.
`0013 For one embodiment, the invention provides a
`non-volatile memory device comprising a non-volatile
`memory array, a buffer memory, a Synchronous memory
`interface, and a controller coupled to the non-volatile
`memory array, the buffer memory, and the Synchronous
`memory interface, wherein the controller is adapted to
`interface to and manage the non-volatile memory array and
`buffer memory and to present the non-volatile memory
`device as a Synchronous memory device through the Syn
`chronous memory interface.
`0014 For another embodiment, the invention provides a
`NAND architecture Flash memory device comprising a
`NAND architecture Flash memory array a buffer memory, a
`Synchronous memory interface, and a controller coupled to
`the NAND architecture Flash memory array, the buffer
`memory, and the Synchronous memory interface, wherein
`the controller is adapted to interface to and manage the
`NAND architecture Flash memory array and to portray the
`NAND architecture Flash memory device as a synchronous
`memory device through the Synchronous memory interface.
`0015 For yet another embodiment, the invention pro
`vides a non-volatile memory Subsystem comprising one or
`more non-volatile memory devices, a buffer memory, a
`Synchronous memory interface, and a controller coupled to
`the one or more non-volatile memory devices, the buffer
`memory, and the Synchronous memory interface, wherein
`the controller is adapted to interface to and manage the
`non-volatile memory devices and to present the non-volatile
`memory devices as a Synchronous memory device through
`the Synchronous memory interface.
`0016 For a further embodiment, the invention provides a
`System comprising a host and one or more non-volatile
`memory devices coupled to the host. Each of the one or more
`non-volatile memory devices comprising a non-volatile
`memory array, a buffer memory, a Synchronous memory
`interface, and a controller coupled to the non-volatile
`memory array, the buffer memory, and the Synchronous
`memory interface, wherein the controller is adapted to
`interface to and manage the non-volatile memory array and
`to present the non-volatile memory device as a Synchronous
`memory device through the Synchronous memory interface.
`0017 For yet a further embodiment, the invention pro
`vides a method of operating a non-volatile memory device
`comprising managing the non-volatile memory device with
`an internal controller presenting the non-volatile memory
`device as a Synchronous memory device through a Synchro
`nous memory interface, and buffering data acceSS requests
`received through the Synchronous memory interface in an
`internal buffer memory.
`0018 Further embodiments of the invention include
`methods and apparatus of varying Scope.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`0019 FIG. 1 is a simplified block diagram of a system
`containing a Flash memory device in accordance with an
`embodiment of the present invention.
`
`HPE, Exh. 1016, p. 7
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`

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`US 2005/0204091 A1
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`Sep. 15, 2005
`
`0020 FIG. 2 is a simplified block diagram of a system
`containing a Flash memory device in accordance with
`another embodiment of the present invention.
`0021 FIGS. 3A and 3B are simplified block diagrams of
`Systems containing a Flash memory Subsystem in accor
`dance with yet another embodiment of the present invention.
`
`DETAILED DESCRIPTION
`0022. In the following detailed description of the inven
`tion, reference is made to the accompanying drawings that
`form a part hereof, and in which is shown, by way of
`illustration, Specific embodiments in which the invention
`may be practiced. In the drawings, like numerals describe
`Substantially similar components throughout the Several
`views. These embodiments are described in Sufficient detail
`to enable those skilled in the art to practice the invention.
`Other embodiments may be utilized and structural, logical,
`and electrical changes may be made without departing from
`the Scope of the present invention. The following detailed
`description is, therefore, not to be taken in a limiting Sense,
`and the Scope of the present invention is defined only by the
`appended claims and equivalents thereof.
`0023 Although described in relation to NAND architec
`ture Flash memory, the various embodiments relate gener
`ally to non-volatile memory devices and Subsystems that
`incorporate a Synchronous interface. High density non
`Volatile memory Subsystems and devices of the present
`invention incorporate a synchronous interface to allow them
`to be utilized as a conventional memory device. Memory
`device embodiments of the present invention utilize an
`external or embedded controller and/or memory buffer to
`present the high density non-volatile memory device(s) as a
`conventional memory device having a Synchronous inter
`face. This allows the high density non-volatile memory
`embodiments of the present invention to Support in-place
`code execution and allow them to be booted from. Addi
`tionally, the memory buffer allows for caching/buffering of
`data read and/or write accesses, allowing high density non
`Volatile memory devices of the present invention to be
`quickly accessed as if they were conventional Synchronous
`RAM memory devices. In one embodiment of the present
`invention, a high density non-volatile memory device elimi
`nates the requirement of external drivers, a memory con
`troller, a customized interface port on a microprocessor,
`and/or operating System Support to utilize a Specialized high
`density non-volatile memory device, and in particular, a
`NAND architecture Flash memory device. This simplifies
`the use and design effort of high density non-volatile memo
`ries by reducing specialized interfacing, while reducing the
`overall production cost through allowing use of a leSS
`expensive NAND architecture Flash memory or other high
`density non-volatile memory where a more expensive
`memory device would normally be required. In another
`embodiment of the present invention, a NAND architecture
`Flash card or Subsystem has a Synchronous interface. In a
`further embodiment of the present invention, a NAND
`architecture Flash memory device, card, or Subsystem has an
`SDRAM compatible interface. In yet a further embodiment
`of the present invention, individual data words of a NAND
`architecture Flash memory device, card, or Subsystem may
`be accessed in a non-prohibitive manner. In another embodi
`ment of the present invention, a NAND architecture Flash
`memory device, card, or Subsystem is accessed by a row and
`
`column address. In yet another embodiment of the present
`invention, a NAND architecture Flash memory device, card,
`or Subsystem contains a RAM buffer allowing in-place code
`execution and/or read/write access. In yet a further embodi
`ment, to reduce average access time, a burst mode acceSS has
`been implemented. The burst mode uses an internal column
`address counter circuit to generate additional column
`addresses. The address counter begins at an externally
`provided address and advances in response to an external
`clock signal or a column address Strobe Signal, up to a
`Selected page size limit.
`0024. As stated above, the two common types of Flash
`memory array architectures are the “NAND” and “NOR”
`architectures, So called for the Similarity each basic memory
`cell configuration has to the corresponding logic gate design.
`Both NAND and NOR Flash memory devices have memory
`cells that are typically arranged in an array of rows and
`columns. In NAND Flash memory devices and some NOR
`Flash memory devices, a row (page) is accessed and then
`memory cells can be randomly accessed on the page by
`providing column addresses. This access mode is referred to
`as page mode acceSS. To read or write to multiple column
`locations on a page requires the external application of
`multiple column addresses.
`0025. In the NOR array architecture, the floating gate
`memory cells of the memory array are arranged in a matrix
`similar to RAM or ROM. The gates of each floating gate
`memory cell of the array matrix are coupled by rows to word
`Select lines (word lines) and their drains are coupled to
`column bit lines. The Source of each floating gate memory
`cell is typically coupled to a common source line. The NOR
`architecture floating gate memory array is accessed by a row
`decoder activating a row of floating gate memory cells by
`Selecting the word line coupled to their gates. The row of
`Selected memory cells then place their Stored data values on
`the column bit lines by flowing a differing current if in a
`programmed State or not programmed State from the coupled
`Source line to the coupled column bit lines. A column page
`of bit lines is Selected and Sensed, and individual data words
`are Selected from the Sensed data words from the column
`page and communicated from the Flash memory.
`0026. A NAND array architecture also arranges its array
`of floating gate memory cells in a matrix Such that the gates
`of each floating gate memory cell of the array are coupled by
`rows to word lines. However each memory cell is not
`directly coupled to a Source line and a column bit line.
`Instead, the memory cells of the array are arranged together
`in Strings, typically of 16, 32, or more each, where the
`memory cells in the String are coupled together in Series,
`Source to drain, between a common Source line and a column
`bit line. This allows a NAND Flash array architecture to
`have a higher memory cell density than a comparable NOR
`Flash array, but with the cost of a generally slower access
`rate and programming complexity.
`0027. A NAND architecture floating gate memory array
`is accessed by a row decoder activating a row of floating
`gate memory cells by Selecting the word Select line coupled
`to their gates. In addition, the word lines coupled to the gates
`of the unselected memory cells of each String are also
`driven. However, the unselected memory cells of each String
`are typically driven by a higher gate Voltage So as to operate
`them as pass transistors and allowing them to pass current in
`
`HPE, Exh. 1016, p. 8
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`US 2005/0204091 A1
`
`Sep. 15, 2005
`
`a manner that is unrestricted by their Stored data values.
`Current then flows from the Source line to the column bit line
`through each floating gate memory cell of the Series coupled
`String, restricted only by the memory cells of each String that
`are Selected to be read. Thereby placing the current encoded
`Stored data values of the row of Selected memory cells on the
`column bit lines. A column page of bit lines is Selected and
`Sensed, and then individual data words are Selected from the
`Sensed data words from the column page and communicated
`from the Flash memory.
`0028 Because all the cells in an erase block of a Flash
`memory device must be erased at once, one cannot directly
`rewrite a Flash memory cell without first engaging in a block
`erase operation. Erase block management (EBM), which can
`be under the control of an internal State machine of the
`memory device or part of the driver Software/memory
`controller, provides an abstraction layer for this to the host
`(typically a processor or an external memory controller),
`allowing the Flash device to appear as a freely rewriteable
`device. EBM duties also include, but are not limited to,
`managing the logical address to physical erase block trans
`lation mapping for reads and writes, the assignment of
`erased and available erase blocks for utilization, and the
`Scheduling erase blocks that have been used and closed out
`for block erasure. Erase block management also allows for
`load leveling of the internal floating gate memory cells to
`help prevent write fatigue failure. Write fatigue is where the
`floating gate memory cell, after repetitive writes and era
`Sures, no longer properly erases and removes charge from
`the floating gate. Load leveling procedures increase the
`mean time between failure of the erase block and Flash
`memory device as a whole.
`0029. The software routines and drivers that operate
`computer based devices and memory controllers are Some
`times referred to as firmware or ROM after the non-volatile
`ROM machine-usable storage device that such routines have
`historically been stored in. It is noted that firmware or
`Software routines can be Stored on a variety of machine
`uSable Storage mediums or firmware Storage mediums that
`include, but are not limited to, a non-volatile Flash memory,
`a ROM, an EEPROM, a one time programmable (OTP)
`device, a complex programmable logic device (CPLD), an
`application specific integrated circuit (ASIC), a magnetic
`media disk, etc.
`0030 FIG. 1 shows a simplified diagram of a system 128
`incorporating a NAND architecture Flash memory device
`100 of the present invention coupled to a host 102, which is
`typically a processing device or memory controller. It is
`noted that memory device 100 embodiments of the present
`invention incorporating other non-volatile memory arrayS
`112 of differing technology and architecture types (includ
`ing, but not limited to, Polymer Memory, FeRAM, OUM,
`MRAM, Molecular Memory, and Carbon Nanotube
`Memory) are also possible and should be apparent to those
`skilled in the art with the benefit of the present disclosure.
`The NAND architecture Flash memory device 100 has a
`Synchronous interface 130 that contains an address interface
`104, control interface 106, and data interface 108 that are
`each coupled to the processing device 102 to allow Synchro
`nous memory read and write accesses. Internal to the NAND
`architecture Flash memory device, an internal memory con
`troller 110 directs the internal operation; managing the Flash
`memory array 112 and updating RAM control registers and
`
`non-volatile erase block management registers 114. The
`RAM control registers and tables 114 are utilized by the
`internal memory controller 110 during operation of the Flash
`memory device 100. The NAND architecture Flash memory
`array 112 contains a Sequence of memory banks or Segments
`116. Each bank 116 is organized logically into a series of
`erase blocks (not shown). Memory access addresses are
`received on the address interface 104 of the NAND archi
`tecture Flash memory device 100 and divided into a row and
`column address portions. On a read access the row address
`is latched and decoded by row decode circuit 120, which
`Selects and activates a row page (not shown) of memory
`cells acroSS a Selected memory bank, the memory cells of the
`Strings associated with the Selected row page are also
`activated in a pass-through mode. The bit values encoded in
`the output of the Selected row of memory cells are coupled
`to a local bitline (not shown) and a global bitline (not shown)
`and are detected by Sense amplifierS 122 associated with the
`memory bank. The column address of the access is latched
`and decoded by the column decode circuit 124. The output
`of the column decode circuit 124 selects the desired column
`data from the internal data bus (not shown) that is coupled
`to the outputs of the individual read Sense amplifiers 122 and
`couples them to an internal buffer memory 126 for transfer
`from the memory device 100 through the data interface 108.
`On a write access the row decode circuit 120 selects the row
`page and column decode circuit 124 Selects write Sense
`amplifiers 122. Data values to be written are coupled from
`the buffer 126 via the internal data bus to the write sense
`amplifiers 122 selected by the column decode circuit 124
`and written to the Selected floating gate memory cells (not
`shown) of the memory array 112. The written cells are then
`reselected by the row and column decode circuits 120, 124
`and Sense amplifierS 122 So that they can be read to verify
`that the correct values have been programmed into the
`Selected memory cells.
`0031 AS stated above, the internal memory controller
`110 controls operation of the NAND architecture Flash
`memory device 100 and through the synchronous interface
`130 presents the NAND architecture Flash memory device
`100 as a conventional synchronous memory (SDRAM,
`DDR, DDR2, GDDR, RDRAM, etc.). The internal memory
`controller 110 also controls the specialized Flash memory
`interfacing and interaction with the memory array 112,
`including, but not limited to, accessing the memory array
`112, address abstraction, mapping bad blocks, generating
`and evaluating ECCs, erase block management, wear lev
`eling, block erasure, and writing data and/or files to the
`memory array 112. This allows the host 102 to interface to
`the NAND architecture Flash memory device 100 as if it was
`a conventional Synchronous memory device and not require
`the use of external memory drivers or expensive dedicated
`external hardware. Additionally, the internal memory con
`troller 110 allows ECC codes to be evaluated and generated
`in a fast and efficient manner via firmware run on the internal
`memory controller 110 or on dedicated internal ECC hard
`ware, offloading the task from the host. This ECC generation
`in internal firmware/hardware is beneficial, in particular,
`where the NAND memory array includes multi-level
`memory cells (MLCs) that store multiple data bits in a single
`cell, further increasing the memory array 112 density but
`also increasing the ECC Overhead to require the use of
`dedicated ECC generation in either the memory controller
`110 firmware or in specialized ECC hardware.
`
`HPE, Exh. 1016, p. 9
`
`

`

`US 2005/0204091 A1
`
`Sep. 15, 2005
`
`0.032 The internal buffer memory 126 operates in concert
`with the memory controller 110 buffering data reads and
`writes, allowing the NAND architecture Flash memory
`device 100 to be presented as a synchronous memory device
`that has fast random read/write and/or burst capabilities.
`During a read access, the internal memory buffer 126 buffers
`the slow accessing Flash array 112 and Stores its large data
`retrievals in the internal buffer memory 126 to be read from
`the Flash memory device 100. The buffer 126 acts as a cache
`memory and allows for fast random access of Small data
`words and blocks from the data stored within its cached
`contents, after an initial delay period where the Selected data
`is retrieved from the Flash memory array 112. In burst
`access mode the buffer 126 can also allow new data to be
`retrieved from the memory array 112, while the current data
`words stored in buffer 126 are being read. During a write
`access, the internal buffer memory 126 buffers the incoming
`data to be written to the Flash memory array 112, allowing
`data to be sent to the memory device 100 as fast as the host
`102 can transfer it through the synchronous interface 130;
`the host 102 does not have to pause its transfer and wait
`while data is written/programmed into the Flash memory
`array 112.
`0033. As the buffer 126 acts as a cache memory, its size
`and/or manner of operation can be tailored to the acceSS
`usage of the NAND architecture Flash memory device 100
`by the host 102. This allows for an as efficient data access
`as possible given the expected data usage of the memory
`device 100. For example, the memory device 100 can be
`tailored for Small data/block accesses, Sequential data
`accesses, large data/block access, and So on. For random
`reads and/or writes, caching data management/replacement
`methods, including, but not limited to, translation look aside
`buffers, least recently used (LRU) data word replacement,
`and write-through caching, can also be used to great effect.
`In one embodiment of the present invention, a special
`purpose “ready/busy external connection pin or internal
`status register/flag of the NAND architecture Flash memory
`device 100 may be monitored to indicate the status of the
`memory. This allows the memory device 100 to signal that
`it is busy with a read or write access (due to read or write