Trials@uspto.gov
`571-272-7822
`
`Paper 9
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_________________________
`
`REALTEK SEMICONDUCTOR CORP.,
`Petitioner,
`v.
`ATI TECHNOLOGIES ULC
`Patent Owner.
`_________________________
`Case No. IPR2023-00564
`U.S. Patent No. 7,742,053
`_________________________
`
`PATENT OWNER’S RESPONSE
`PURSUANT TO 37 C.F.R. § 42.107(A)
`
`
`
`

`

`Case No. IPR2023-00564
`U.S. Patent No. 7,742,053
`
`TABLE OF CONTENTS
`
`C.
`
`Page
`
`INTRODUCTION ........................................................................................... 1
`I.
`II. Graphics Processing......................................................................................... 3
`A. Vertex and Pixel Processing .................................................................. 3
`B. Vertex and Pixel Command Threads .................................................... 4
`’053 PATENT .................................................................................................. 4
`III.
`IV. EXEMPLARY CLAIM ................................................................................... 6
`V.
`CLAIM CONSTRUCTION ............................................................................ 7
`A.
`Storage of “command threads” ............................................................. 7
`B.
`“at least one memory device . . . operative to store a plurality of
`pixel command threads and . . . operative to store a plurality of
`vertex command threads” ...................................................................... 8
`“select a command thread from either of the plurality of pixel
`command threads and the plurality of vertex command threads” ....... 10
`“command processing engine” ............................................................ 11
`D.
`VI. PETITIONER HAS FAILED TO ESTABLISH THE REQUIRED
`REASONABLE LIKELIHOOD OF SUCCESS FOR ANY GROUND ...... 14
`A. Ground 1: Stuttard In View of the Knowledge Of A POSITA ........... 14
`1.
`All Claims: Stuttard Does Not Disclose or Render
`Obvious a Memory Device That Stores a Plurality of
`Pixel Command Threads and Vertex Command Threads
`at the Same Time in First and Second Portions ........................ 20
`a.
`Stuttard Operates in a Phased Manner ............................ 21
`b.
`Stuttard Executes One Instruction at a Time .................. 26
`c.
`Stuttard Does Not Care About Command Thread
`Type ................................................................................ 31
`The Claims Require More Than Mere Possibility,
`Happenstance, or Capability ........................................... 32
`All Claims: Stuttard Does Not Disclose or Render
`Obvious Storing Complete Command Threads ........................ 33
`
`d.
`
`2.
`
`i
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`Case No. IPR2023-00564
`U.S. Patent No. 7,742,053
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`4.
`
`2.
`
`3.
`
`b.
`
`3.
`
`All Claims: Stuttard Does Not Disclose Or Render
`Obvious an Arbiter That Selects A Command Thread
`From The Plurality Of Pixel Command Threads Vertex
`Command Threads .................................................................... 36
`Claim 7: Stuttard Does Not Disclose Or Render Obvious
`a Texture Processing Engine ..................................................... 39
`B. Ground 2: Stuttard In View Of Williams and The Knowledge
`Of A POSITA ...................................................................................... 40
`1.
`All Claims: Williams Does Not Disclose or Render
`Obvious Storing Vertex and Pixel Command Threads in
`First And Second Portions of Memory ..................................... 45
`a.
`There Is No Motivation to Modify the Memory in
`Williams .......................................................................... 45
`There Is No Motivation to Include the Modified
`Version of Williams’s Memory In Stuttard .................... 51
`All Claims: Williams Does Not Disclose or Render
`Obvious Storing “Command Threads” ..................................... 52
`a. Williams’ Graphics Commands Are Not Pixel and
`Vertex Command Threads .............................................. 53
`b. Williams Does Not Store Complete Command
`Threads ........................................................................... 55
`All Claims: Stuttard Does Not Disclose or Render
`Obvious the Claimed Arbiter .................................................... 59
`Claims 3, 8: Williams Does Not Disclose a “Second
`Memory Device” ....................................................................... 59
`Claim 7: Stuttard Does Not Disclose or Render Obvious
`a Texture Processing Engine ..................................................... 60
`No Motivation to Combine or Reasonable Expectation of
`Success ...................................................................................... 60
`C. Ground 3: Williams In View Of Whittaker and the Knowledge
`Of A POSITA ...................................................................................... 62
`1.
`All Claims: Ground 3 Does Not Disclose or Render
`Obvious Storing Vertex or Pixel Command Threads ............... 65
`
`4.
`
`5.
`
`6.
`
`ii
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`Case No. IPR2023-00564
`U.S. Patent No. 7,742,053
`
`2.
`
`4.
`
`5.
`
`3.
`
`All Claims: Williams’ Does Not Disclose or Render
`Obvious the Claimed Arbiter .................................................... 66
`Claims 2, 5-9: Williams Does Not Disclose Or Render
`Obvious the Claimed Command Processing Engines .............. 68
`Claims 3, 8: Williams Does Not Disclose A “Second
`Memory Device” ....................................................................... 69
`Claim 6: Williams Does Not Disclose or Render Obvious
`Arithmetic Logic Unit ............................................................... 69
`Claim 7: Williams Does Not Disclose or Render Obvious
`a Texture Processing Engine ..................................................... 70
`No Motivation to Combine or Reasonable Expectation of
`Success ...................................................................................... 70
`VII. CONCLUSION .............................................................................................. 72
`
`
`
`6.
`
`7.
`
`iii
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`Case No. IPR2023-00564
`U.S. Patent No. 7,742,053
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`TABLE OF AUTHORITIES
`
` Page(s)
`
`Federal Cases
`Aspex Eyewear, Inc. v. Marchon Eyewear, Inc.,
`672 F.3d 1335 (Fed. Cir. 2012) .......................................................................... 33
`ATI Techs. ULC ATI Techs. ULC v. Iancu, 920 F.3d 1362 (Fed. Cir.
`2019) .................................................................................................................. 12
`Gemalto S.A. v. HTC Corp.,
`754 F.3d 1364 (Fed. Cir. 2014) .......................................................................... 13
`In re Magnum Oil Tools Int’l, Ltd.,
`829 F.3d 1364 (Fed. Cir. 2016) .................................................................... 35, 57
`Oren Techs., LLC v. Proppant Express Invs. LLC,
`No. 2019-1778, 2021 U.S. App. LEXIS 21859 (Fed. Cir. July 23,
`2021) ................................................................................................................... 57
`Persion Pharms. LLC v. Alvogen Malta Operations LTD.,
`945 F.3d 1184 (Fed. Cir. 2019) .......................................................................... 40
`Retractable Techs., Inc. v. Becton,
`653 F.3d 1296 (Fed. Cir. 2011) .......................................................................... 13
`TQ Delta, LLC v. Commscope Holding Co.,
`No. 2:21-CV-310-JRG, 2022 U.S. Dist. LEXIS 102577 (E.D. Tex.
`June 8, 2022) ....................................................................................................... 32
`Wasica Fin. GmbH v. Cont’l Auto. Sys.,
`853 F.3d 1272 (Fed. Cir. 2017) .......................................................................... 70
`Regulations
`37 C.F.R. § 42.24(d) ................................................................................................ 73
`
`
`iv
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`Case No. IPR2023-00564
`U.S. Patent No. 7,742,053
`
`Exhibit
`2009
`
`TABLE OF EXHIBITS
`Description
`Declaration of John Hart, Ph.D., Regarding U.S. Patent No.
`7,742,053 (Jan. 17, 2024)
`
`Deposition Transcript of Massoud Pedram, Ph.D. (Jan. 8, 2024)
`
`Frank D. Luna. 2003. Introduction to 3D Game Programming with
`DirectX 9.0. Wordware Publishing Inc.
`
`Sumair Ahmed. 2009. “OpenGL – Lighting, Material, Shading and
`Texture Mapping.” IIT Bombay.
`
`2010
`
`2011
`
`2012
`
`
`
`v
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`

`

`Case No. IPR2023-00564
`U.S. Patent No. 7,742,053
`
`I.
`
`INTRODUCTION
`Petitioner Realtek has failed to prove that any of the challenged claims 1-9 of
`
`Patent Owner ATI’s U.S. Patent No. 7,742,053 are unpatentable for at least the
`
`following reasons.
`
`
`
`Ground 1 fails for all challenged claims because Stuttard does not disclose
`
`or render obvious the following limitations required by each challenged claim:
`
` a memory that stores pixel and vertex command threads at the same time,
`
`in first and second portions of memory;
`
` storing complete command threads; and
`
` an arbiter that selects a command thread from the plurality of vertex or
`
`pixel command threads.
`
`
`
`In addition, Ground 1 fails for dependent claim 7 because Stuttard does not
`
`disclose or render obvious that claim’s texture processing engine.
`
`
`
`Ground 2 fails for all challenged claims because neither Stuttard nor Williams
`
`discloses or renders obvious the following limitations required by each challenged
`
`claim:
`
` a memory that stores pixel and vertex command threads at the same time,
`
`in first and second portions of memory ; and
`
` storing complete command threads
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`1
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`Case No. IPR2023-00564
`U.S. Patent No. 7,742,053
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` an arbiter that selects a command thread from the plurality of vertex or
`
`pixel command threads.
`
`Ground 2 also fails because there is no motivation to combine Stuttard and
`
`Williams, nor reasonable expectation of success of combining these two references
`
`that take conflicting approaches to graphics processing. In addition, Ground 2 fails
`
`for dependent claim 7 because it again relies on Stuttard, and also fails to disclose
`
`the additional restrictions of claims 3 and 8.
`
`
`
`Ground 3 fails for all challenged claims because neither Williams nor
`
`Whittaker discloses or renders obvious the following limitations required by each
`
`challenged claim:
`
` storing vertex and pixel command threads; and
`
` an arbiter that selects a command thread from the plurality of vertex or
`
`pixel command threads.
`
`In addition, Ground 3 fails because the Petition does not establish a motivation
`
`to combine or reasonable expectation of success for the proposed combination, and
`
`because that combination fails to disclose or make obvious additional limitations
`
`required by claims 2, 3, and 5-8.
`
`2
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`

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`Case No. IPR2023-00564
`U.S. Patent No. 7,742,053
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`II. GRAPHICS PROCESSING
`A. Vertex and Pixel Processing
`Graphics processing involves manipulating and rendering 3D graphical
`
`objects onto a 2D display screen. Ex. 2004 (Real-Time Rendering), 11; Ex. 2009,
`
`¶25. Specifically, 3D objects (typically represented by triangles) are converted into
`
`a 2D image (typically comprising pixels) as shown below. Ex. 2003 (Foley), 3, 11-
`
`15, 17-20; Ex. 2004, 11-13; Ex. 2009, ¶25. The 2D image represents a depiction of
`
`the 3D objects, rendered from the perspective of a viewer, and shaded to convey the
`
`object’s surface material illuminated from a given light source. Ex. 2003, 210-222,
`
`722-741; Ex. 2004, 21-27; Ex. 2009, ¶25.
`
`
`
`The conversion of a 3D shape consisting of a mesh of triangles into a
`
`photorealistic 2D image consisting of an array of pixels happens in a pipeline. Ex.
`
`2003, 806-809, 866-871; Ex. 2004, 12; Ex. 2009, ¶26. The first stage processes each
`
`triangle’s corner points, i.e., its “vertices,” and is thus called “vertex processing.” In
`
`vertex processing, each vertex’s original 3D coordinates are transformed into 2D
`
`coordinates for display on a 2D screen. Ex. 2003, 806-809, 866-871; Ex. 2004, 14-
`
`21; Ex. 2009, ¶26.
`
`3
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`The next stage, “scan conversion,” each 2D triangle is rendered as a collection
`
`of 2D dots on the screen, known as “pixels.” Ex. 2003, 806-809; Ex. 2004, 21-22;
`
`Ex. 2009, ¶27. The final “pixel processing” stage computes the colors and textures
`
`for each rendered pixel. Ex. 2003, 868-872; Ex. 2006 (Catmull); Ex. 2004, 22-23;
`
`Ex. 2009, ¶27.
`
`B. Vertex and Pixel Command Threads
` As the ITC has found, and as adopted in the Board’s Institution Decision
`
`(“ID”), a “command thread” is “a sequence of commands applicable to the
`
`corresponding element.” ID, 14-15. The “corresponding element” for a pixel
`
`command thread is a pixel, and for a vertex command thread is a vertex. Ex. 1001,
`
`2:41-45; Ex. 2009, ¶46. Thus, a pixel command thread is a sequence of commands
`
`applicable to a pixel, and a vertex command threads is a sequence of commands
`
`applicable to a vertex.
`
`III.
`
`’053 PATENT
`The ’053 Patent discloses novel graphics processing systems and for
`
`processing multiple command threads across one or more hardware processing units
`
`with the specialized parallel processing architecture of a graphics processor. Ex.
`
`2009, ¶28.
`
`Prior art systems were rigid systems that required providing command threads
`
`sequentially. Ex. 1001, 1:31-48; Ex. 2009, ¶29. Prior to the ’053 Patent, systems
`
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`Case No. IPR2023-00564
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`consisted of two separate command processing engines: a pixel command processing
`
`engine that only ran pixel command threads and a vertex command processing
`
`engine that only ran vertex command threads. Ex. 2009, ¶29. Since there were 10x-
`
`100x more pixels than vertices, graphics processing could run into a load imbalance
`
`causing one of the command processing engines to wait while the other finished its
`
`processing. Id.
`
`The ’053 Patent solves those problems with a novel architecture that uses a
`
`single “unified shader processor” (the “command processing engine”) capable of
`
`executing both pixel command threads and vertex command threads:
`
`Ex. 1001, Fig. 4; Ex. 2009, ¶30.
`
`5
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`Case No. IPR2023-00564
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`
`
`This architecture further comprises a memory for storing the pixel and vertex
`
`command threads and an arbiter that selects one of those stored command threads
`
`for the unified shader based on the relative priorities of those threads. Ex. 1001,
`
`2:45-48, 3:29-36; Ex. 2009, ¶31. Thus, the arbiter ensures that the unified shader
`
`processor was kept as busy as possible while it completed rendering of the current
`
`frame as quickly as possible, e.g., either processing the final pixels of the current
`
`frame, or by processing the vertices for triangles in the next frame. Ex. 1001, 3:16-
`
`20; Ex. 2009, ¶31.
`
`IV. EXEMPLARY CLAIM
`Independent claim 5 demonstrates several of the important distinctions
`
`between the inventions of the ‘053 patent and the prior art:
`
`A graphics processing system comprising:
`
`at least one memory device comprising a first portion operative to store a
`
`plurality of pixel command threads and a second portion operative to store a
`
`plurality of vertex command threads;
`
`an arbiter, coupled to the at least one memory device, operable to select a
`
`command thread from either of the plurality of pixel command threads and the
`
`plurality of vertex command threads; and
`
`a plurality of command processing engines, coupled to the arbiter, each
`
`operable to receive and process the command thread.
`
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`Case No. IPR2023-00564
`U.S. Patent No. 7,742,053
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`V. CLAIM CONSTRUCTION
`A.
`Storage of “command threads”
`All the challenged claims recite a memory device having a first portion that
`
`stores “a plurality of pixel command threads” and a second portion that stores “a
`
`plurality of vertex command threads.” Ex. 2009, ¶47. The express language requires
`
`that actual “command threads” are stored, not merely a partial sequence of
`
`instructions that do not constitute a complete command thread. Accordingly, the
`
`claims should be construed to require storing full and complete “command threads,”
`
`and not incomplete sequence of instructions from a command thread. Ex. 1001,
`
`Claims 1, 5.
`
`Petitioner cannot reasonably contest this because it proposed this same
`
`construction in the ITC Investigation, where it was adopted by the ALJ. Ex. 2002
`
`(ITC Markman), 32-39. Petitioner argued that “a complete thread must be stored at
`
`a given moment in time” and that it is incorrect that “portions of a complete thread
`
`are sufficient so long as the entire thread is stored over a period of time.” Id., 32-
`
`33. The ALJ agreed. Id., 39.
`
`This construction is also consistent with the specification, which in all
`
`instances describes the storage of a “command thread,” and not merely some
`
`incomplete set of instructions thereof. Ex. 2009, ¶48. For example, the specification
`
`describes reservation stations as “any type of memory device capable of reserving
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`Case No. IPR2023-00564
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`and storing command threads.”1 Ex. 1001, 2:39-41. Both Figures 2 and 4
`
`embodiments describe “command threads” as being stored. Id., 2:63-3:36, 3:62-
`
`4:64, Figs. 2, 4. Figs. 6 and 7, which illustrate flowcharts of exemplary methods,
`
`also provides steps of retrieving “a selected command thread.” Id., 5:43-6:54, Figs.
`
`6-7. Additionally, the specification describes that complete command threads are
`
`stored in the memory device even if some instructions from that command thread
`
`have already been executed. Id., 4:21-27; Ex. 2009, ¶49. Thus, a command thread
`
`is more
`
`than a command or an
`
`instruction, but rather a sequence of
`
`commands/instructions, and the entire command thread must be stored in memory.
`
`Ex. 1001, 2:41-45.
`
`Thus, the claims should be construed so that the claimed memory device must
`
`be operative to store a plurality of complete sequences of pixel commands and a
`
`plurality of complete sequences of vertex commands.
`
`B.
`
`“at least one memory device . . . operative to store a plurality of
`pixel command threads and . . . operative to store a plurality of
`vertex command threads”
`The explicit language of the claims, the specification, the ALJ’s prior
`
`construction, and the testimony of Petitioner’s own expert all establish that this claim
`
`
`1 Unless otherwise noted, all emphases are added.
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`Case No. IPR2023-00564
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`limitation requires the storage of both pixel and vertex command threads at the same
`
`time. Ex. 2009, ¶¶51-54.
`
`The plain language of the claims provides that the memory device stores both
`
`command thread types at the same time, requiring that it be “operative to store a
`
`plurality of pixel command threads and … to store a plurality of vertex command
`
`thread.” Ex. 1001, Claims 1, 5.
`
`The ’053 Patent specification likewise uniformly describes that the memory
`
`device stores both types of command threads at the same time. Id., 2:65-3:3, 3:40-
`
`44, 3:50-53, 3:62-4:48, 5:10-16, 5:43-56; Figs. 2, 4, 5; Ex. 2009, ¶52. For example,
`
`the specification describes that command threads are stored in one portion of the
`
`memory device while vertex command threads are stored in another portion of the
`
`memory device. Ex. 1001, 4:5-13. Using priorities, the arbiter then “selectively
`
`retrieves either a pixel command thread, such as command thread 316, or a vertex
`
`command thread, such as command thread 322.” Id. In order for the arbiter to
`
`selectively retrieve either type of command thread from the memory device, both
`
`must be stored in the memory at the same time. See id.
`
`Indeed, the claims require the same; the arbiter must “select a command thread
`
`from either of the plurality of pixel command threads and the plurality of vertex
`
`command threads.” Ex. 1001, Claims 1, 5; Ex. 2009, ¶53. Petitioner’s expert
`
`testified that “select” means “look[] at command threads that are available and
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`chooses one.” Ex. 2010 (Pedram IPR Depo.), 196:24-197:4. Yet if only pixel
`
`command threads were present (and thus available) in the claimed memory device,
`
`the claimed arbiter would not be able to select “from either of” the pluralities, as
`
`required. Ex. 2009, ¶53. The same is true if only vertex command threads were
`
`available. Id. Thus, at a minimum, the claim requires the claimed memory device to
`
`store two pixel command threads and two vertex command threads, and thus four
`
`command threads, at the same time. Id. Indeed, Dr. Pedram admitted that an arbiter
`
`that is operable to select only from pixel command threads or only vertex command
`
`threads does not meet the claims. Ex. 2007, 215:20-24.
`
`In the ITC, the ALJ likewise held that “it is a correct claim construction . . .
`
`the memory device(s) are operable to store both pluralities at the same time.” Ex.
`
`2002, 84.
`
`Therefore, properly construed, the limitation “at least one memory device . . .
`
`operative to store a plurality of pixel command threads and . . . a plurality of vertex
`
`command threads” requires the storage of a plurality of pixel command threads and
`
`a plurality of vertex command threads at the same time.
`
`C.
`
`“select a command thread from either of the plurality of pixel
`command threads and the plurality of vertex command threads”
`As discussed, this limitation confirms and further requires that both types of
`
`command threads must be available to select from at the time when the arbiter’s
`
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`selection occurs, i.e., they must be present at the same time in memory. Ex. 2009,
`
`¶55.
`
`Petitioner’s Dr. Pedram agreed, testifying that an arbiter that is only operable
`
`to select pixel command threads and is not operable to select vertex command
`
`threads does not meet the claims. Ex. 2010, 215:20-24.
`
`Petitioner nonetheless contradicts
`
`the express claim
`
`language,
`
`the
`
`specification, the ALJ, and its own expert to argue that interpreting this limitation to
`
`require a plurality pixel command threads and vertex command threads be stored at
`
`the same time so that the arbiter may choose between them somehow renders the
`
`phrase “from either of” meaningless. Pet., 12; Ex. 1004, ¶44. It is Petitioner’s
`
`interpretation which renders the phrase meaningless because “from either of”
`
`specifies that the arbiter must be able to select between two possible alternatives,
`
`either a pixel type or a vertex type. Ex. 2009, ¶55. If only one type of command
`
`thread is present, it cannot select “from either of” the two, it can only select from
`
`one type. Id.
`
`D.
`“command processing engine”
`Claims 2, 5-9 require a “command processing engine” to receive whichever
`
`of the pixel or vertex command threads is selected by the arbiter. Ex. 2009, ¶56.
`
`Claims 5-9 further explicitly require that the command processing engine be able to
`
`process whichever pixel or vertex command threads are selected by the arbiter. Ex.
`
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`2009, ¶57. Accordingly, the command processing engine should be construed as
`
`being able to receive and process both pixel and vertex command threads, and not
`
`encompassing specialized engines that can only process one type of command
`
`thread. Id.
`
`Petitioner’s expert, Dr. Pedram, agreed that that the unified shader, the subject
`
`of the ʼ053 Patent, includes “a command processing engine that processes both pixel
`
`and vertex threads.” Ex. 2005 (ITC Hearing), 988:20-23. This requirement is
`
`explicit in claims 5-9. Ex. 2009, ¶57. And although claim 2 does not explicitly
`
`recite that its command processing engine must process in addition to receiving the
`
`different types of command threads, a POSITA would understand an arbiter would
`
`not provide a command thread to a command processing engine which could not
`
`process it. Ex. 2009, ¶58. Petitioner’s expert, Dr. Pedram agreed that “each of the
`
`claim[ed] processing engines must be operative to process whichever thread is
`
`provided to it by the claimed arbiter, be it a pixel command thread or a vertex
`
`command thread.” Ex. 2005, 988:7-19.
`
`The Federal Circuit has already held the same, recognizing that the “[t]he ’053
`
`Patent describes a multi-thread[ed] (unified) graphics processing system that
`
`processes both vertex and pixel operations.” ATI Techs. ULC v. Iancu,, 920 F.3d
`
`1362, 1365-6 (Fed Cir. 2019). “The system employs a memory device for storing
`
`command threads and an arbiter for providing a command thread to a command
`
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`Case No. IPR2023-00564
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`processing engine, . . . whereby the command processing engine performs either
`
`vertex or pixel operations based on the command thread from the arbiter.” Id., 1366.
`
`Dr. Pedram agreed that the specification of the ’053 Patent does not discuss
`
`or disclose specialized command processing engines, i.e., command processing
`
`engines which process only pixel or only vertex command threads. Ex. 2010,
`
`219:24-220:2; Ex. 2009, ¶59. Because “the claims cannot be of broader scope than
`
`the invention that is set forth in the specification,” the command processing engines
`
`must be able to process both types of command threads. Gemalto S.A. v. HTC Corp.,
`
`754 F.3d 1364, 1369 (Fed. Cir. 2014); see also Retractable Techs., Inc. v. Becton,
`
`653 F.3d 1296, 1305 (Fed. Cir. 2011) (“In reviewing the intrinsic record to construe
`
`the claims, we strive to capture the scope of the actual invention, rather than . . .
`
`allow[ing] the claim language to become divorced from what the specification
`
`conveys is the invention.”).
`
`Therefore, “command processing engine” should be construed as being able
`
`to process both pixel and vertex command threads, and not encompassing
`
`specialized engines that can only process one type of command thread.
`
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`Case No. IPR2023-00564
`U.S. Patent No. 7,742,053
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`VI. PETITIONER HAS FAILED TO ESTABLISH THE REQUIRED
`REASONABLE LIKELIHOOD OF SUCCESS FOR ANY GROUND
`A. Ground 1: Stuttard In View of the Knowledge Of A POSITA
`Petitioner alleges that Stuttard in view of the knowledge of a POSITA renders
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`the challenged claims obvious. However, Stuttard does not disclose the claimed “at
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`least one memory device” because the alleged memory device does not store both
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`pixel and vertex command threads at the same time, nor does it store pixel and vertex
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`command threads in first and second portions of memory, respectively, which are
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`requirements of all challenged claims. Ex. 2009, ¶61.
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`Petitioner admits that Stuttard does not disclose the claimed memory device,
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`but argues that such memory devices were known in the mind of a POSITA and a
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`POSITA would have been motivated to use such a memory device in Stuttard to
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`store command threads, either instead of or in addition to the cache memory used in
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`Stuttard to store commands.
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`But even setting aside whether Petitioner has proven that the claimed memory
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`device was known, which it has not, there is no motivation to make that change in
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`Stuttard for 3 main reasons.
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`First, it first operates exclusively on vertices in a first phase. Ex. 2009, ¶¶32-
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`34. Then, only when that vertex phase is fully complete, and after a binning phase,
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`does it operate exclusively on pixels, with no overlap in the execution of the vertex
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`and pixel phases. Id. Figure 9 of the reference discloses the flow of graphics
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`processing in Stuttard, and as the annotations demonstrate, the process describes
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`distinct pixel and vertex phases, with an intermediate binning phase separating them:
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`
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`Ex. 1005, Fig. 9 (annotated). There is thus no reason to modify Stuttard to add a
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`memory, either as a replacement for or addition to cache 1024 of Stuttard, that stores
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`pixel and vertex commands at the same time, as would waste valuable memory
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`resources storing commands that are not being executed in a given phase.
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`Case No. IPR2023-00564
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`
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`Second, even if the above is incorrect, Stuttard’s system can only operate on
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`one instruction at a time. It therefore would not store both type of command threads,
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`as it cannot execute both types of commands simultaneously. Petitioner’s theory
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`revolves relies on and requires Figure 4 of Stuttard and the components it describes.
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`As Stuttard itself explains, “In the example shown in Figure 4 the thread manager
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`includes one thread processor 1026 for each thread. . . In this particular example the
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`same instruction stream is supplied to all of the processing blocks in the system.”
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`Ex. 1005 at 11:27-35.
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`Case No. IPR2023-00564
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`
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`Ex. 1005, Fig. 4 (annotated).
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`Third, even if the above are both incorrect, the thread scheduler, which
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`“determine[s] which thread should be active at any one time” (Ex. 1005 at 12:12-
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`17) does not know or care about the command thread type. It just cares about priority
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`of the thread and directs the processing blocks to execute the highest priority thread.
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`Petitioner’s expert testified that the thread scheduler’s “selection is not . . . on the
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`basis of vertex versus pixel command threads. . . It just looks at the priority of the
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`thread.” Ex. 2010, 318:11-319:17. There is therefore no reason to replace cache
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`1024, or add to it, with a memory that simultaneously stores both command thread
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`types in first and second portions. It does not benefit the thread scheduler’s
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`selection, or any other aspect of Stuttard, for this more complex, more restrictive,
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`more wasteful memory.
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`Also, as explained further below, cache 1024 of Stuttard also does not store
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`complete command threads, which is required by all challenged claims.
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`Further, dependent claim 7’s “texture processing engine” is nowhere to be
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`found in Stuttard;
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`Ex. 1005, Fig. 3 (annotated).
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`
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`All Petitioner has pointed to in Stuttard is the discussion of some commands
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`that might or might not require texture processing, but there is no indication texture
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`processing is required, much less that a texture processing engine exists in Stuttard.
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`
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`Case No. IPR2023-00564
`U.S. Patent No. 7,742,053
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`1.
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`All Claims: Stuttard Does Not Disclose or Render Obvious a
`Memory Device That Stores a Plurality of Pixel Command
`Threads and Vertex Command Threads at the Same Time
`in First and Second Portions
`Claims 1 and 5 require “at least one memory device comprising a first portion
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`operative to store a plurality of pixel command threads and a second portion
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`operative to store a plurality of vertex command threads.” Ex. 1001, Claims 1, 5.
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`This claim limitation requires the storage of pixel command threads and vertex
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`command threads in different portions of memory at the same time, and in first and
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`second portions. See Section V.B.
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`Petitioner identifies the cache unit 1024 as disclosing the claimed “at least one
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`memory device . . . .” Pet., 20. However, even Petitioner admits that “Stuttard’s
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`FIFO cache unit 1024 does not explicitly disclose ‘a first portion operative to store
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`a plurality of pixel command threads’ and ‘a second portion operative to store a
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`plurality of vertex command thread.’” Id. (emphases in original). Petitioner relies
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`on an alleged “obvious” modification to the memory device to store both types of
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`command threads and to do so in separate “portions.” Pet., 20-25; Ex. 2009, ¶63.
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`There is no motivation for Petitioner’s proposed modification, as explained
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`above and detailed further below.
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`Case No. IPR2023-00564
`U.S. Patent No. 7,742,053
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`a.
`Stuttard Operates in a Phased Manner
`Figure 9 describes the phased graphics processing method of the system
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`disclosed by Stuttard. Ex. 1005, 3:21-22 (“Figure 9 is a flowchart illustrating data
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`processing using the system of Figures 1-8.”); Ex. 2009, ¶65. Petitioner nor its
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`expert does not even address the binning aspect of Stuttard, which is fatal to its
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`arguments.
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`
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`Id., Fig. 9 (annotated).
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`Figure 9 explains that the first step of graphics processing is that the host
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`prepares vertex data. Id., 20:25-30; Ex. 2009, ¶66. Then, vertex data is “loaded into
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`Case No. IPR2023-00564
`U.S. Patent No. 7,742,053
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