Trials@uspto.gov
`571-272-7822
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Paper 7
`Entered: October 25, 2023
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`REALTEK SEMICONDUCTOR CORP.,
`Petitioner,
`v.
`ATI TECHNOLOGIES ULC,
`Patent Owner.
`
`IPR2023-00564
`Patent 7,742,053 B2
`
`
`
`
`
`
`
`
`
`Before JAMES P. CALVE, BRIAN J. McNAMARA, and
`KEVIN W. CHERRY, Administrative Patent Judges.
`McNAMARA, Administrative Patent Judge.
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
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`
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`
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`
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`
`
`571-272-7822
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`Paper 7
`Entered: October 25, 2023
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`REALTEK SEMICONDUCTOR CORP.,
`Petitioner,
`v.
`ATI TECHNOLOGIES ULC,
`Patent Owner.
`
`IPR2023-00564
`Patent 7,742,053 B2
`
`
`
`
`
`
`
`
`
`Before JAMES P. CALVE, BRIAN J. McNAMARA, and
`KEVIN W. CHERRY, Administrative Patent Judges.
`McNAMARA, Administrative Patent Judge.
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314
`
`
`
`
`
`
`
`
`
`
`
`IPR2023-00564
`Patent 7,742,053 B2
`
`INTRODUCTION
`I.
`Realtek Semiconductor Corp. (“Petitioner”) filed a petition, Paper 1
`(“Petition” or “Pet.”), to institute an inter partes review (“IPR”) of claims 1–
`9 (the “challenged claims”) of U.S. Patent No. 7,742,053 B2 (“the ’053
`patent”). 35 U.S.C. § 311. ATI Technologies ULC (“Patent Owner”) filed a
`Preliminary Response, Paper 6 (“Prelim. Resp.”), contending that the
`Petition should be denied as to all challenged claims.
`We have jurisdiction under 35 U.S.C. § 6. This Decision on
`Institution is issued pursuant to 35 U.S.C. § 314, which provides that an
`inter partes review may not be instituted unless the information presented in
`the Petition “shows that there is a reasonable likelihood that the petitioner
`would prevail with respect to at least 1 of the claims challenged in the
`petition.”
`A decision to institute under § 314 may not institute on fewer than all
`claims challenged in the petition. SAS Inst., Inc. v. Iancu, 138 S. Ct. 1348,
`1359–60 (2018). In addition, per Board practice, if the Board institutes trial,
`it will institute “on all of the challenged claims and on all grounds of
`unpatentability asserted for each claim.” See 37 C.F.R. § 42.108(a).
`Having considered the arguments and the associated evidence
`presented in the Petition and the Preliminary Response, for the reasons
`described below, we institute inter partes review.
`II. REAL PARTIES IN INTEREST
`The Petition identifies Petitioner Realtek Semiconductor Corp. as the
`real party-in-interest. Pet. 1. Patent Owner identifies ATI Technologies
`ULC as the real party-in-interest. Paper 4, 1.
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`III. RELATED MATTERS
`Petitioner and Patent Owner identify the following as proceedings that
`may affect or may be affected by a decision in this proceeding:
`Advanced Micro Devices, Inc. et al v. TCL Industries Holdings Co.,
`Ltd. et al., C.A. No. 2:22-cv-00134 (E.D. Tex. May 5, 2022); and
`Certain Graphics Systems, Components Thereof, and Digital
`Televisions Containing The Same, Inv. No. 337-TA-1318 (“ITC
`Investigation”)
`Pet. 1–2; Paper 4, 1.
`
`IV. THE ’053 PATENT
`The ’053 patent relates to graphic processing and the interleaving of
`arithmetic logic unit (ALU) operations with texture fetching operations.
`Ex. 1001, 1:16 – 18. According to the ’053 patent, in a typical graphics
`processing system, the processing elements, such as vertices and/or pixels
`are processed through multiple steps that provide for the application of
`textures and other processing instructions, as done through one or more
`ALUs. Id. at 1:24 – 27. The ’053 patent describes its Figure 1, reproduced
`below, as “a prior art sequencing system.” Id. at 1:32.
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`Id. at Fig. 1. In Figure 1, system 100 includes first, second and third arbiters
`101–103 and multiple buffers or “reservation stations” 104, 106, 108, 110
`that are typically first-in, first-out (FIFO) buffers. Id. at 1:33–35, 1:43–44,
`1:46–47. Each buffer or reservation station stores multiple command
`threads, e.g., 112, 114, 116, 118. Id. at 1:36 – 38; see also id. at 2:37–41.
`“[A] command thread is a sequence of commands applicable to a
`corresponding element such as a pixel command thread relative to
`processing of pixel elements and a vertex command thread relative to vertex
`processing commands.” Id. at 2:41–45.
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`Prior art system 100 is divided into ALU resource division 120 and
`texture fetch resource division 122. Ex. 1001, 1:38–40. In ALU resource
`division 120, command thread 118 selected by arbiter 101 may be received
`in a reservation station 104, 108 from an input command 124; command
`thread 118 may then be withdrawn from reservation stations 104 and 108
`and provided to an ALU (not shown). Id. at 1:40–45. Command threads
`within texture fetch resource division 122 may be withdrawn from
`reservation stations 106 and 110 to be provided to a texture fetch processor
`(not shown). Id. at 1:45–48. First buffer 104 receives input command 124
`and outputs a completed command thread 126 to second arbiter 102. Id. at
`1:49–51. Arbiter 102 receives input command 124 and in due course
`provides the command thread to either an appropriate texture fetch buffer
`110 or an ALU buffer 108. Id. at 1:55–57. The steps are repeated where an
`output thread command 128 is provided to another ALU (not shown) or
`texture fetch processor (not shown) and returned to buffer 108 or 110. Id. at
`1:57–61. Buffer 110 also produces output 132 which is a command thread
`that may be provided to another arbiter 103 to be provided further along the
`graphics processing pipeline. Id. at 1:61–64.
`According to the ’053 patent, the prior art system in Figure 1 is
`inflexible because delineated ALU resource buffers and texture fetch
`resource buffers are such that command threads must be sequentially
`provided through the various buffers 104, 106, 108, and 110; the system also
`does not support an unlimited number of dependent fetches based on the
`buffer structure and their connectivity between each other and the available
`ALU resources and texture fetch resources. Ex. 1001, 1:65–2:6.
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`Figure 2 of the ’053 patent, reproduced below, is a schematic block
`diagram of a multithread processing graphics system according to one
`embodiment of the invention. Ex. 1001, 2:15–17.
`
`
`The embodiment in Figure 2 includes reservation station 202, which can be
`“any type of memory device capable of reserving and storing command
`threads,” and arbiter 204, implemented in hardware, software or a
`combination thereof; the arbiter receives a command thread 208, 210, 212
`from the reservation station and provides the command thread to command
`processing engine 206. Ex. 1001, 2:15–17, 2:36–52, 2:63–3:11. Command
`processing engine 206 performs a thread command and provides status
`update 218 to the corresponding command thread 208, 210, or 212 in
`reservation station 202. Id. at 3:12–15. The ’053 patent provides for
`processing of multiple threads to prevent the corresponding resources from
`going idle while waiting for resources to become available, e.g., while
`awaiting retrieval of specific data. Id. at 3:16–20. In one embodiment, a
`done flag indicates when all commands within a thread have been executed,
`allowing the command thread to be retrieved from the reservation station
`and provided to a further processing element within a graphics processing
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`pipeline. Id. at 3:20–28. Arbiter 204 may also receive command threads
`208–212 based on a priority scheme appropriate for effective utilization of
`the arbiter and command processing engine 206, or based on the oldest
`available thread. Id. at 3:29–36.
`Figure 3, reproduced below, is a schematic block diagram of a
`pipeline vector machine according to one embodiment of the invention.
`Ex. 1001, 2:15–17, 3:29–30.
`
`
`Id. at Fig. 3. The system in Figure 3 includes multiple ALU system 232,
`buffer 234, and sequencer logic 236, which may be an ALU resource. Id. at
`3:37–40. Sequencer logic 236, coupled to pipeline 240, receives first thread
`242 from buffer 234, such that logic 236 may perform simultaneous
`interleaved execution of the command threads. Id. at 3:41–45. Like fetch
`arbitration, ALU arbitration proceeds with the arbiter selecting the first
`command ready to execute from vertex and pixel reservation stations. Id. at
`3:48–53.
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`Figure 4 of the ’053 patent reproduced below, illustrates another
`embodiment of a multithread command processing system. Ex. 1001, 3:62–
`63.
`
`
`Id. at Fig. 4. The embodiment in Figure 4 shows pixel reservation station
`302 with command threads 312, 314, 316 having pixel based commands and
`vertex reservation station 304 with vertex command threads 318, 320, 322.
`Id. at 3:63–4:4. Arbiter 306 selectively retrieves either pixel command
`thread 324 or vertex command thread 326 and provides one thread 328,
`which may be either pixel thread 324 or vertex thread 326, to graphics
`processing engine 310, such as a texture engine, and provides the other
`thread 330 to ALU 308. Id. at 4:28–33. Two sets of arbitration are
`performed, one for pixels, such as command thread 316, and one for
`vertices, such as command thread 322. Id. at 5:13–16. Arbiter 306 selects
`the proper allocation of which command thread goes to graphics processing
`engine 310 and which command thread goes to ALU 308 based on state bits
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`and status bits that indicate the progress of the thread executions. Id. at
`4:49–5:10. Upon execution of the thread, ALU 308 and graphics processing
`engine 310 return command threads 332, 334 to the originating reservation
`stations. Id. at 4:34–41. To switch a command thread from ALU 308 to
`graphics processor engine (texture) 310, that thread must be returned to its
`reservation station, re-retrieved by arbiter 306 and provided to the other unit
`308, 310 respectively. Upon execution of all embedded commands in a
`thread, as indicated for example by a done flag, ALU 308 provides the
`completed command thread further in the processing pipeline, e.g., to a
`suitable rending backend and scan converter, as would be recognized by an
`ordinarily skilled artisan. Id. at 5:19–42, Fig. 5.
`ILLUSTRATIVE CLAIM
`V.
`Claims 1 and 5 are independent. Claim 5, reproduced below, is
`illustrative of the subject matter of the ’053 patent:
`5. A graphics processing system comprising:
`at least one memory device comprising a first portion
`operative to store a plurality of pixel command threads and
`a second portion operative to store a plurality of vertex
`command threads;
`an arbiter, coupled to the at least one memory device,
`operable to select a command thread from either of the
`plurality of pixel command threads and the plurality of
`vertex command threads; and
`a plurality of command processing engines, coupled to the
`arbiter, each operable to receive and process the command
`thread.
`Ex. 1001, 8:4–15.
`Claim 6 recites that the plurality of command processing engines
`comprise at least one arithmetic logic unit; claim 7 recites that the command
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`processing engines comprise least one texture processing unit. Ex. 1001,
`8:16–21.
`
`Independent claim 1 differs from independent claim 5 by (a) reciting
`that the arbiter selects a command thread based on relative priorities and (b)
`not reciting a plurality of command processing engines coupled to the arbiter
`as recited in claim 5. Compare Ex. 1001, 7:10–21, 8:4–15. Claim 2
`depends from claim 1 and recites a command processing engine coupled to
`the arbiter, with the arbiter operable to provide the command thread to the
`command processing engine. Id. at 7:22–26. Claims 3 and 8 depend from
`claim 1 and 5, respectively, and recite the first portion of the at least one
`memory device comprises a first memory device and the second portion of
`the at least one memory device comprises a second memory device. Id. at
`7:27–30, 8:23–25. Claims 4 and 9 depend from claims 1 and 5, respectively,
`and recite a single memory device comprises the first portion and the second
`portion of the at least one memory device. Id. at 8:1–3, 8:26–28.
`VI. ASSERTED GROUNDS
`Petitioner asserts that claims 1–9 would have been unpatentable on the
`following grounds:
`Claim(s) Challenged
`1–9
`
`Reference(s)
`Stuttard2, Admitted Prior Art
`
`35 U.S.C. §
`1031
`
`
`1 See The Leahy-Smith America Invents Act (“AIA”), Pub. L. No. 112-29,
`125 Stat. 284, 287–88 (2011), amended 35 U.S.C. §§ 102, 103, and 112.
`Because the application of the ’053 patent was filed before March 16, 2013
`(the effective date of the relevant amendments), the pre-AIA versions of
`§§ 102, 103, and 112 apply.
`2 PCT Pub. No. WO00/62182A2, pub. Oct. 19, 2000 to Stuttard et al. (Ex.
`1005)
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`Claim(s) Challenged
`1–9
`1–9
`
`Reference(s)
`35 U.S.C. §
`Stuttard, Williams3
`103
`Williams, Whittaker4
`103
`The following evidence is also in the record before us:
`Declaration of Dr. Massound Pedram In Support Of Petition
`For Inter Partes Review (Ex. 1004, “Pedram Decl.”);
`Declaration of Dr. John Hart Regarding U.S. Patent 7,742,053
`(Ex. 2001, “Hart Decl.”);
`LG Electronics, Inc. v. ATI Technologies ULC, IPR2015-00325
`Final Written Decision (Paper 62), PTAB, Apr. 14, 2016 (Ex.
`1011, the ’325 IPR)5;
`Transcript of Deposition of Dr. Massoud Pedram in ITC
`Investigation (Ex. 2008, “Massoud ITC Dep. Tr.”);
`Transcript of Hearing in Inv. No. 1318 (Ex. 2005, “ITC Hr’g
`Tr.”);
`Inv. No 37-TA-1318 Initial Determination On Violation Of
`Section 337 And Recommended Determination On Remedy
`And Bond (Ex. 2002, “ID”).
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`3 PCT Pub. No. WO00/63770A1, pub. Oct. 26, 2000, to Williams (Ex.
`1006).
`4 U.S. Patent 5,968,167, iss. Oct. 10, 1999, to Whittaker et al. (Ex. 1007).
`5 In IPR2015-00325 (“the -00325 IPR”), the Board found claims 1, 2, and 5–
`7 of the ’053 patent unpatentable over U.S. Patent No. 7,363,472 to Stuttard
`(“Stuttard ’472”) and the admitted prior art. The Federal Circuit reversed
`the Board’s Decision, finding that Patent Owner had antedated Stuttard ’472,
`which was asserted as prior art under 35 U.S.C. § 102(e). In this proceeding,
`Petitioner relies on the Stuttard PCT application as a prior art reference
`under 35 U.S.C. § 102(b). See Pet. 4; see also Ex. 1011, 13–14 (noting that
`the Stuttard international publication is a prior art reference under § 102(b),
`but that the Stuttard international publication was not cited in any of the
`grounds of unpatentability in the -00325 IPR).
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`VII. LEVEL OF ORDINARY SKILL IN THE ART
`Consistent with the ID, Petitioner applies the following description of
`person of ordinary skill (also referred to herein as “POSITA” or “ordinarily
`skilled artisan”):
`a POSITA would have a bachelor degree in electrical
`engineering, computer engineering, computer science, or a
`related field, and at least two years of experience in “parallel
`computing or graphics processing including developing,
`designing, or programming software or hardware for graphics
`processing or parallel processing units, graphics accelerators[,]
`or other graphics processing systems,” with additional education
`substituti[ing] for experience and vice versa.
`Ex. 1004, Pedram Decl. ¶ 41. Patent Owner does not further address the
`description of a person of ordinary skill.
`The level of ordinary skill in the art usually is evidenced by the
`references themselves. See Okajima v. Bourdeau, 261 F.3d 1350, 1355
`(Fed. Cir. 2001); In re GPAC Inc., 57 F.3d 1573, 1579 (Fed. Cir. 1995); In
`re Oelrich, 579 F.2d 86, 91 (CCPA 1978). Because the description adopted
`in the ID and by Dr. Pedram appears commensurate with the subject matter
`of the ’053 patent and the asserted prior art references, we apply it in the
`context of this Decision.
`VIII. CLAIM CONSTRUCTION
`For petitions filed after November 13, 2018, we interpret claim terms
`using “the same claim construction standard that would be used to construe
`the claim in a civil action under 35 U.S.C. 282(b).” 37 C.F.R. § 42.100(b)
`(2019). In this context, claim terms “are generally given their ordinary and
`customary meaning” as understood by a person of ordinary skill in the art in
`question at the time of the invention. Phillips v. AWH Corp., 415 F.3d 1303,
`1312–13 (Fed. Cir. 2005) (citations omitted) (en banc). “In determining the
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`meaning of the disputed claim limitation, we look principally to the intrinsic
`evidence of record, examining the claim language itself, the written
`description, and the prosecution history, if in evidence.” DePuy Spine, Inc.
`v. Medtronic Sofamor Danek, Inc., 469 F.3d 1005, 1014 (Fed. Cir. 2006)
`(citing Phillips, 415 F.3d at 1312–17). Extrinsic evidence is “less significant
`than the intrinsic record in determining ‘the legally operative meaning of
`claim language.’” Phillips, 415 F.3d at 1317 (citations omitted).
`Any special definition for a claim term must be set forth in the
`specification with reasonable clarity, deliberateness, and precision. In re
`Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994).
`We construe only those claim terms that require analysis to determine
`whether to institute inter partes review. See Realtime Data, LLC v. Iancu,
`912 F.3d 1368, 1375 (Fed. Cir. 2019) (“The Board is required to construe
`‘only those terms . . . that are in controversy, and only to the extent
`necessary to resolve the controversy’” (quoting Vivid Techs., Inc. v. Am. Sci.
`& Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999)).
`At the time of the -00325 IPR, the Board gave claims their broadest
`reasonable construction in light of the Specification. Ex. 1011, 4. As
`discussed above, we now apply the Phillips construction standard used by
`U.S. district courts and the International Trade Commissions (“ITC”).
`Petitioner contends that the constructions adopted in the ID are actually
`broader than those adopted by the Board in the -00325 IPR and that applying
`the constructions from the ID or those from the -00325 IPR would have no
`meaningful effect on the outcome of this Decision. Pet. 11. Petitioner notes
`that, for some terms, the construction applied by the Administrative Law
`Judge (“ALJ”) in the ID does not add limitations and no further construction
`is required. See id. at 11–12 (“arbiter only need to ‘select’ a command
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`thread”), 13 (‘“relative priorities’ of the ‘plurality of pixel command threads
`and the plurality of vertex command threads’ does not refer to whether the
`command thread is ‘either a ‘vertex’ priority or a ‘pixel’ priority’), 13–14
`(command engine does not require that each engine must process each
`command thread selected by and received from the arbiter), 14 (“memory
`device” given its plain and ordinary meaning), 14–15 (“coupled to” does not
`require direct connection). Petitioner contends that these constructions do
`not affect its unpatentability arguments and applies these constructions from
`the ID in the Petition. See Pet. 11.
`Patent Owner does not address the above claim terms. Neither party
`appears to argue that any issue in this Decision turns on the above
`constructions. Aa we are persuaded that construction of these claim terms is
`not determinative, for purposes of this proceeding, , we apply the above
`constructions in this Decision. We now turn to constructions that appear to
`be disputed by the parties.
`Command threads/select a command thread from either the
`A.
`plurality of pixel command threads and the plurality of vertex
`command threads
`Petitioner states that, in the ID, the term “command threads” was
`construed “to mean ‘a sequence of commands applicable to the
`corresponding element’ with no requirement that the threads comprise state
`bits.” Pet. 14; Ex. 2002, 32. According to Petitioner, “[t]his construction is
`sufficiently broad as to not affect Petitioner’s invalidity analysis.” Id. (citing
`Ex. 1004, Pedram Decl. ¶ 47).
`Patent Owner does not address how the term “command thread”
`should be construed. Instead, Patent Owner cites a different part of the ID,
`where the ALJ found the term ‘“select a command thread’ does not mean
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`selecting one and only one thread.” Prelim. Resp. 21–22 (citing Ex. 2002,
`39); see Ex. 2002, 41. According to Patent Owner, we should adopt the
`construction proposed by Petitioner and adopted in the ID, i.e., that “the
`claimed arbiter can satisfy the requirement of selecting ‘a’ command thread
`from the plurality of pixel and vertex command threads so long as the
`claimed arbiter makes a selection of one or more command threads of the
`plurality of command threads.” Id.
`Petitioner notes that, in the ID, the term “select a command thread
`from either of the plurality of pixel command threads and the plurality of
`vertex command threads” does not require an arbiter to select a command
`thread based on state bits associated with each command thread. Pet. 12.
`Patent Owner does not address this issue.
`As we are persuaded that Petitioner’s proposed construction of these
`terms is not determinative for purposes of this Decision we apply the
`constructions adopted in the ID for the terms “command thread” and “select
`a command thread.”
`At least one memory device . . . . operative to store a plurality
`B.
`of pixel command threads and . . . a plurality of vertex command
`threads
`Patent Owner urges that we adopt a construction that this term
`requires the memory device to store complete pixel and vertex command
`threads, not partial command threads. Prelim. Resp. 21–22 (arguing that
`such a construction is consistent with Petitioner’s proposed construction in
`the ITC Investigation and adopted in the ID; see Ex. 2002, 37). Petitioner
`does not comment on this aspect of the construction.
`Patent Owner also proposes that we read into this language the
`requirement that the memory devices are operable to store a plurality of
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`pixel threads and a plurality of vertex threads at the same time. According
`to Patent Owner, the ID found “this is the plain language of the words in the
`claims, and the ’053 patent specification uniformly describes the claimed
`memory device this way.” Prelim. Resp. 22 (citing Ex. 2002, 84; Ex. 1001,
`2:65–3:3, 3:40–44, 3:50–53, 3:62–4:51, 5:10–16, 5:43–56, Fig. 2, Fig. 4,
`Fig. 5). According to Patent Owner, in order for the arbiter to select a
`command thread from either the plurality of pixel command threads and the
`plurality of vertex command threads, as recited in claims 1 and 5, both
`pluralities of command threads must be present at the same time. Id. at 23
`(citing Ex. 2001, Hart Decl. ¶ 29).
`Petitioner does not address this term as a matter of claim construction,
`but in its unpatentability arguments notes that in the ITC Investigation Patent
`Owner contended that the memory device must store both pixel and vertex
`command threads at the same time. Pet. 25. Petitioner contends that the
`claim does not require the pixel and vertex threads be stored at the same
`time and, even if it did, the ’053 patent acknowledges that simultaneous
`storage of pixel and vertex threads was well known in the art. As we discuss
`in our analysis of Petitioner’s challenge, we need not construe this term
`because, for purposes of this Decision, we determine that Petitioner prevails
`under either construction.
`
`IX. ANALYSIS
`Legal Principles
`A.
`“In an [inter partes review], the petitioner has the burden from the
`onset to show with particularity why the patent it challenges is
`unpatentable.” Harmonic Inc. v. Avid Tech., Inc., 815 F.3d 1356, 1363 (Fed.
`Cir. 2016) (citing 35 U.S.C. § 312(a)(3) (requiring inter partes review
`petitions to identify “with particularity . . . the evidence that supports the
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`grounds for the challenge to each claim”)). This burden of persuasion never
`shifts to Patent Owner. See Dynamic Drinkware, LLC v. Nat’l Graphics,
`Inc., 800 F.3d 1375, 1378 (Fed. Cir. 2015) (discussing the burden of proof in
`inter partes review).
`The question of obviousness is resolved on the basis of underlying
`factual determinations including: (1) the scope and content of the prior art;
`(2) any differences between the claimed subject matter and the prior art;
`(3) the level of ordinary skill in the art; and (4) objective evidence of
`nonobviousness. Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966).
`
`Additionally, the obviousness inquiry typically requires an analysis of
`“whether there was an apparent reason to combine the known elements in
`the fashion claimed by the patent at issue.” KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398, 418 (2007) (citing In re Kahn, 441 F.3d 977, 988 (Fed. Cir.
`2006) (requiring “articulated reasoning with some rational underpinning to
`support the legal conclusion of obviousness”)); see In re Warsaw
`Orthopedic, Inc., 832 F.3d 1327, 1333 (Fed. Cir. 2016) (citing DyStar
`Textilfarben GmbH & Co. Deutschland KG v. C. H. Patrick Co., 464 F.3d
`1356, 1360 (Fed. Cir. 2006)).
`An obviousness analysis “need not seek out precise teachings directed
`to the specific subject matter of the challenged claim, for a court can take
`account of the inferences and creative steps that a person of ordinary skill in
`the art would employ.” KSR, 550 U.S. at 418; accord In re Translogic
`Tech., Inc., 504 F.3d 1249, 1259 (Fed. Cir. 2007). Petitioner cannot satisfy
`its burden of proving obviousness by employing “mere conclusory
`statements.” In re Magnum Oil Tools Int’l, Ltd., 829 F.3d 1364, 1380 (Fed.
`Cir. 2016). Instead, Petitioner must articulate a reason why a person of
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`IPR2023-00564
`Patent 7,742,053 B2
`ordinary skill in the art would have combined the prior art references. In re
`NuVasive, 842 F.3d 1376, 1382 (Fed. Cir. 2016).
`A reason to combine or modify the prior art may be found explicitly
`or implicitly in market forces; design incentives; the “‘interrelated teachings
`of multiple patents’”; “‘any need or problem known in the field of endeavor
`at the time of invention and addressed by the patent’”; and the background
`knowledge, creativity, and common sense of the person of ordinary skill.
`Perfect Web Techs., Inc. v. InfoUSA, Inc., 587 F.3d 1324, 1328–29 (Fed. Cir.
`2009) (quoting KSR, 550 U.S. at 418–21).
`In determining whether a claim is obvious in light of the prior art,
`when in evidence, we consider any relevant objective evidence of non-
`obviousness. See Graham, 383 U.S. at 17. Notwithstanding what the
`teachings of the prior art would have suggested to one of ordinary skill in the
`art at the time of the invention, the totality of the evidence submitted,
`including objective evidence of non-obviousness, may lead to a conclusion
`that the challenged claims would not have been obvious to one of ordinary
`skill. In re Piasecki, 745 F.2d 1468, 1471–72 (Fed. Cir. 1984). At this stage
`of the proceeding, Patent Owner does not present evidence of such objective
`considerations.
`We analyze the asserted grounds of unpatentability in accordance with
`these principles to determine whether Petitioner has met its burden to
`establish a reasonable likelihood of success at trial.
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`IPR2023-00564
`Patent 7,742,053 B2
`Petitioner’s Challenge to Claims 1–9 As Obvious Over Stuttard
`B.
`And The Knowledge of a Person of Ordinary Skill In The Art As
`Evidenced By the Admitted Prior Art in the ’053 Patent
`1.
`Stuttard – Exhibit 1005
`Stuttard discloses and claims a parallel processing apparatus that
`processes large amounts of data and observes that the computer graphics
`field is one example of a system that requires high speed processing of
`massive amounts of data. Ex. 1005, 1. 6 Stuttard discloses a “previously
`proposed processing architecture for processing large amounts of data in a
`computer system using a Single Instruction Multiple Data (SIMD) array of
`processing elements” and notes that “[i]n such an array all of the processing
`elements receive the same instruction stream, but operate on different
`respective data items.” Id. at 1:24–30.
`In Stuttard, the processing elements (PEs) are operably divided into a
`plurality of processing blocks. Ex. 1005, 2:17–23, 56:3–9 (claim 1). The
`processing blocks each have at least one PE and are operable to process
`respective groups of data items. Id. at 2:25–33, 56:11–18 (claims 1, 2).
`Within a processing block, the array of PEs operates in parallel on respective
`data items carrying out the same instructions (SIMD). Id. at 17:29–33,
`Fig. 8.
`Figure 1 of Stuttard, shown below, is a block diagram of an exemplary
`graphics processing system. Ex. 1005, 3:5–6, 4:3–11.
`
`
`6 Both parties use the page numbers of the published version of Stuttard,
`rather than the page numbers of Exhibit 1005. For consistency, we adopt the
`same page numbering conventions as those used by the parties in this
`Decision.
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`IPR2023-00564
`Patent 7,742,053 B2
`
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`Id. at Fig. 1. Graphics data processing system 3 communicates with a host
`system, e.g., a computer workstation (not shown), through interface 2, e.g.,
`an advanced graphics port or PCI interface. Id. at 4:21–24, 5:8–28.
`Embedded processor unit (EPU) 8 controls overall functions of graphics
`processor 3. Id. at 4:25–30. Processor core 10 processes graphical data to
`output to a display screen via video output 14; local memory 12 stores
`information used by graphics system 3. Id. at 4:30–34, 7:11–16. Primary
`bus 4 and secondary buses 6 are also shown. Id. at 6:8–10.
`A more detailed block diagram is shown below in Figure 2a (top),
`Figure 2b (bottom left), and Figure 2c (bottom right).
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`IPR2023-00564
`IPR2023-00564
`Patent 7,742,053 B2
`Patent 7,742,053 B2
`
`2aiq4?,
`
`FIG. 2(a)
`
`
`OIRECT HOST ACCESS
`(DHA)
`
`
`AP TARSSET|PC TARGET
`PORT
`PORT
`OONFIG
`
`
`
`“WGP MASTER|Pol MASTER SPACE
`INTERFACE
`PORT
`
`
`
`
`AGPMASTER/TARGET
`
`PCIMASTER/TARGET MEM TO MER
`
`corr UNIT
`SECONDARY
`
`ARBITERS i
`
`
`
`
`SECONDARY FPRUS x2
`
`
`61
`
`
`
` OVERLAY2 STREAM
`
` i
`TIMING &VGA
`
`
`VIDEO
`
`CAT INPUT
`UNIT
`
`
`
`
`
`
`
`21
`21
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`IPR2023-00564
`Patent 7,742,053 B2
`
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`
`
`
`Ex. 1005, Figs. 2a, 2b, 2c. In Stuttard, primary bus 4 is used for connection
`to latency intolerant devices and secondary bus 6 is used for connection to
`latency tolerant devices. Id. at 6:6–18. The architecture accommodates any
`number of primary and secondary buses—the architecture in Figures 2a and
`2b include 2 secondary buses. Id. Access to primary bus 4 is controlled by
`arbiter 41 and access to secondary buses 6 is controlled by secondary
`arbiters 61. Id. at 6:21–24. Secondary buses 6 are connected to primary
`interface bus 4 by interface units (SIP) 62. Id. at 6:25–27. Processing core
`10, which provides the graphic processing capability of the system, is
`provided with 8 processing blocks 106, although any number of processing
`blocks can be provided in a graphics processing system of this architecture.
`Id. at 8:9–13. Core 10 is connected to secondary buses 6 by core bus
`interface (Core FBI) 107 for the transfer of data and binner bus interface
`
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`IPR2023-00564
`Patent 7,742,053 B2
`(Binner FBI) 111; core 10 is connected to primary bus 4 by thread manager
`bus interface (Thread Manager FBI) 103 for the transfer of instructions. Id.
`at 8:25–34. Local memory 12 includes memory interface units (four in this
`example) to communicate with local memory
`Figure 3 of the Stuttard, reproduced below, shows processing core 10
`in more detail. Ex. 1005, 8:17.
`
`
`Ex. 1005, Fig. 3. Processing core 10 includes the following units controlling
`the operation of processing blocks 106 that perform the graphics processing:
`thread manager 102, array controller 104, channel controller 108, binning
`unit 1069 per block and microcode store 105.
`Control signals from EPU 8 inform thread manager 102 about when
`and where instructions are to be found. Ex. 1005, 8:19–21. Thread manager
`
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`IPR2023-00564
`Patent 7,742,053 B2
`102 provides instructions to array controller 104 and channel controller 106,
`which transfer control signals to respective processing blocks 106 (shown
`one behind the other in Figure 3). Id. at 8:22–27. Each processing block
`106 includes array 1061 of processing elements (PE(s)) and a mathematical
`expression evaluator (MEE) 1062, as well as binning unit 1069, FBB
`feedback to MEE unit 1068, and a transfer engine for controlling data
`transfers to and from the input/output channel under instructions from
`channel controller 108. Id. at 8:29–9:3; Fig. 8. Each PE 1061 includes
`
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