UNITED STATES PATENT AND TRADEMARK OFFICE
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` _________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`_________________
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`LENOVO (UNITED STATES) INC.
`Petitioner
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`v.
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`INTELLECTUAL VENTURES II LLC
`Patent Owner
`
`_________________
`
`Case No. IPR2024-01226
`Patent No. 7,646,835 B1
`___________________
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`DECLARATION OF R. JACOB BAKER, P.E., PH.D.
`IN SUPPORT OF PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 7,646,835 B1
`
`Petitioner Lenovo (United States) Inc. - Ex. 1002
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`1 of 212
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` _________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`_________________
`
`LENOVO (UNITED STATES) INC.
`Petitioner
`
`v.
`
`INTELLECTUAL VENTURES II LLC
`Patent Owner
`
`_________________
`
`Case No. IPR2024-01226
`Patent No. 7,646,835 B1
`___________________
`
`DECLARATION OF R. JACOB BAKER, P.E., PH.D.
`IN SUPPORT OF PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 7,646,835 B1
`
`Petitioner Lenovo (United States) Inc. - Ex. 1002
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`1 of 212
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`I.
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`II.
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`TABLE OF CONTENTS
`INTRODUCTION ...............................................................................1
`A.
`Background and Qualifications .....................................................2
`1. Industry Experience ...............................................................3
`2. Academic Experience ............................................................7
`3. Other Relevant Experience .....................................................9
`Summary of Opinions and Materials Reviewed............................. 10
`B.
`LEGAL STANDARDS FOR PATENTABILITY .................................. 13
`A. Anticipation ............................................................................. 13
`B. Obviousness ............................................................................. 13
`C.
`Level of Ordinary Skill in the Art................................................ 17
`D. Claim Construction ................................................................... 19
`1. Preambles (Claims 1, 7, 12, 20, and 23).................................. 20
`2. “the valid operating range includes an optimal operation point for
`the integrated circuit device” (Claims 1 and 7) .............................. 20
`III. OPINION ......................................................................................... 21
`A.
`Background of the Technology ................................................... 21
`1. Dynamic Random-Access Memory (DRAM) .......................... 21
`2. DDR DRAM and SLDRAM ................................................. 24
`3. Memory Controllers............................................................. 27
`B. Overview of the ’835 Patent ....................................................... 31
`C. Overview of the ’835 Patent’s File History ................................... 39
`D.
`Summary of the Prior Art References .......................................... 43
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`E.
`F.
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`1. Johnson (Ex. 1004) .............................................................. 43
`2. Jeddeloh (Ex. 1005) ............................................................. 49
`3. Keeth (Ex. 1006) ................................................................. 56
`Summary of the Grounds ........................................................... 64
`Ground 1: Claims 1-23 are Obvious Over Johnson in View of
`Jeddeloh .................................................................................. 66
`1. Claim 1 .............................................................................. 66
`2. Claim 2 – The method of claim 1, wherein the integrated circuit
`device comprises a DRAM component. ....................................... 97
`3. Claim 3 – The method of claim 2, wherein said altering is
`performed by a memory controller coupled to the DRAM component.
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`97
`4. Claim 4 – The method of claim 2, wherein the DRAM component
`comprises a DDR DRAM component. ....................................... 103
`5. Claim 5 – The method of claim 4, wherein the data signals
`comprise a plurality of data bus (DQ) signals for the DDR DRAM
`component. ............................................................................ 106
`6. Claim 6 – The method of claim 5, wherein the sampling signals
`comprise a plurality of sampling bus (DQS) signals for the DDR
`DRAM component. ................................................................. 108
`7. Claim 7 ............................................................................ 112
`8. Claim 8 – The system of claim 7, wherein the integrated circuit
`device comprises a DRAM component. ..................................... 123
`9. Claim 9 – The system of claim 8, wherein the DRAM component
`comprises a DDR DRAM component. ....................................... 124
`10. Claim 10 – The system of claim 9, wherein the data signals
`comprise a plurality of DQ signals for the DDR DRAM component.
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`124
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`11. Claim 11 – The system of claim 10, wherein the sampling signals
`comprise a plurality of DQS signals for the DDR DRAM component.
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`125
`12. Claim 12 ........................................................................ 125
`13. Claim 13 ........................................................................ 127
`14. Claim 14 – The method of claim 13, wherein said performing a
`coarse calibration comprises simultaneously varying each of the phase
`shift of the command signal, the phase shift of the data signal, and the
`phase shift of the sampling signal by a five percent step increase... 134
`15. Claim 15 – The method of claim 13, wherein said performing a
`fine calibration comprises varying each of the phase shift of the
`command signal, the phase shift of the data signal, and the phase shift
`of the sampling signal one at a time by a two percent step increase.136
`16. Claim 16 – The method of claim 13, further comprising
`configuring the memory controller to operate the DRAM component
`in the optimal operating mode................................................... 139
`17. Claim 17 – The method of claim 12, wherein the DRAM
`component comprises a DDR DRAM component........................ 140
`18. Claim 18 – The method of claim 17, wherein the data signals
`comprise a plurality of DQ signals for the DDR DRAM component.
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`140
`19. Claim 19 – The method of claim 18, wherein the sampling
`signals comprise a plurality of DQS signals for the DDR DRAM
`component. ............................................................................ 140
`20. Claim 20 ........................................................................ 141
`21. Claim 21 ........................................................................ 144
`22. Claim 22 – The computer readable media of claim 21, wherein
`the method further comprises configuring the memory controller to
`operate the DRAM component in the optimal operating mode. ..... 146
`23. Claim 23 ........................................................................ 147
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`G. Ground 2: Claims 1-3, 7-8, and 12 are Obvious Over Johnson in View
`of Keeth. ................................................................................ 149
`1. Claim 1 ............................................................................ 150
`2. Claim 2 – The method of claim 1, wherein the integrated circuit
`device comprises a DRAM component. ..................................... 166
`3. Claim 3 – The method of claim 2, wherein said altering is
`performed by a memory controller coupled to the DRAM component.
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`166
`7. Claim 7 ............................................................................ 169
`8. Claim 8 – The system of claim 7, wherein the integrated circuit
`device comprises a DRAM component. ...................................... 174
`12. Claim 12 ........................................................................ 174
`H. Ground 3: Claims 4-6, 9-11, 13-19 are Obvious Over Johnson in
`View of Keeth and Jeddeloh ..................................................... 176
`IV. CONCLUSION ............................................................................... 178
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`Declaration of R. Jacob Baker, P.E., Ph.D.
`Inter Partes Review of U.S. Patent No. 7,646,835 B1
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`I, R. Jacob Baker, declare as follows:
`
`INTRODUCTION
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`
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`I.
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`1.
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`I have been retained by Lenovo (United States) Inc. (“Lenovo” or
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`“Petitioner”) as an independent technical expert consultant in connection with the
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`above-captioned Inter Partes Review of U.S. Patent No. 7,646,835 B1 (“the ’835
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`Patent”) (Ex. 1001). Although I am being compensated at my normal consulting
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`rate of $765 per hour for the time I spend on this matter, no part of my
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`compensation is dependent on the outcome of this proceeding or any other related
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`proceeding. I have no other interest in this proceeding.
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`2.
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`I understand that the ’835 Patent is assigned to Intellectual Ventures II
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`LLC (“Intellectual Ventures” or “Patent Owner”). In addition, I understand that the
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`’835 Patent issued from U.S. Application No. 10/716,320 (the “’320 application”),
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`which was filed on November 17, 2003. (Ex. 1001.)
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`3.
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`I am familiar with the technology at issue as of November 17, 2003,
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`i.e., the filing date of the ’320 application.
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`4.
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`I have been asked to consider how a person having ordinary skill in
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`the art (POSITA) would have understood the claims of the ’835 Patent and the
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`applied references. More specifically, I have been asked to provide my technical
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`opinion on concepts discussed in the ’835 Patent and the reference documents, as
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`well as my technical opinion on how these concepts relate to the ’835 Patent’s
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`claim limitations in the context of the written description.
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`5.
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` In reaching the opinions stated herein, I have considered the ’835
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`Patent and the various other documents listed in Section III below in the context of
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`my own education, training, research, knowledge, and personal and professional
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`experiences. My opinions are provided below.
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`A. Background and Qualifications
`6. My qualifications generally are set forth in my Curriculum Vitae,
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`which is attached as Appendix A. Appendix A also includes a list of the
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`publications I have authored and a list of the other cases in which I have testified
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`during the last four years.
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`7.
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`I have been working as an Engineer since 1985 and I have been
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`teaching Electrical and Computer Engineering courses since 1991. I am currently a
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`Professor of Electrical and Computer Engineering at the University of Nevada, Las
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`Vegas (“UNLV”).
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`8.
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`I received B.S. and M.S. degrees in Electrical Engineering from
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`UNLV in 1986 and 1988, respectively. I received my Ph.D. in Electrical
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`Engineering from the University of Nevada, Reno, in 1993.
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`9. My doctoral research, culminating in the award of a Ph.D.,
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`investigated the use of power MOSFETs in the design of very high peak power,
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`and high-speed, instrumentation. I developed techniques to reliably stack power
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`MOSFETs to switch higher voltages, that is, greater than 1,000 V and 100 Amps of
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`current with nanosecond switching times. This work was reported in the paper
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`entitled “Transformerless Capacitive Coupling of Gate Signals for Series
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`Operation of Power MOSFET Devices,” published in the IEEE Transactions on
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`Power Electronics. The paper received the Best Paper Award in 2000.
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`1.
`Industry Experience
`I have done technical and expert witness consulting for over 200
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`10.
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`companies and their subsidiaries since I started working as an engineer in 1985.
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`From 1985 to 1993, I worked for EG&G Energy Measurements and the Lawrence
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`Livermore National Laboratory designing nuclear diagnostic instrumentation for
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`underground nuclear weapon tests at the Nevada Test Site. During this time, I
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`designed, and oversaw the fabrication of, over 30 electronic and electro-optic
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`instruments, including high-speed cable and fiber-optic receiver/transmitters, phase
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`locked loops (PLLs), frame and bit-syncs, data converters, streak-camera sweep
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`circuits, Pockels cell drivers, micro-channel plate gating circuits, charging circuits
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`for battery backup of equipment for recording test data, and analog oscilloscope
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`electronics.
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`11. My work during this time, as one example, had a direct impact on my
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`doctoral research work using power MOSFETs, subsequent publishing efforts, and
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`industry designs. In addition to the 2000 Best Paper Award from the IEEE Power
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`Electronics Society, I published several other papers in related areas while working
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`in industry. I hold a patent, Patent No. 5,874,830, in the area of power supply
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`design, titled, “Adaptively biased voltage regulator and operating method,” which
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`was issued on February 23, 1999. I have designed dozens of linear and switching
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`power supplies for commercial products and scientific instrumentation.
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`12.
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`I am a licensed Professional Engineer and have extensive industry
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`experience in circuit design, fabrication, and manufacture of Dynamic Random
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`Access Memory (DRAM) semiconductor integrated circuit chips, Phase-Change
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`Random Access Memory (PCRAM) chips, and CMOS Image Sensors (CISs) at
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`Micron Technology, Inc. (“MTI”) in Boise, Idaho. I spent considerable time
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`working on the development of flash memory chips while at MTI. My efforts
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`resulted in more than a dozen patents relating to flash memory. One of my projects
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`at MTI included the development, design, and testing of circuit design techniques
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`for a multi-level cell (MLC) flash memory using signal processing. This effort
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`resulted in higher-density memories for use in solid-state drives and flash memory
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`cards having an ATA interface that are ubiquitous in consumer electronics,
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`including cameras and data storage systems. Further, the use of higher-density
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`memory can result in fewer changes in the flash translation layer for logical-to-
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`physical addressing, less need for garbage collection, and larger data segments that
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`can improve a computing system’s performance. Another project I worked on at
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`MTI focused on the design of buffers for high-speed double-data rate DRAM,
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`which resulted in around 10 U.S. patents in buffer design. Among many other
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`experiences, I led the development of the delay locked loop (DLL) in the late
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`1990s so that MTI DRAM products could transition to the DDR memory protocol,
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`used in mobile and non-mobile (server, desktop, cell phones, tablets, etc.)
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`computing systems as main computer memory, for addressing and controlling
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`accesses to memory via inter-process communications (IPC) with the memory
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`controller (MC). This included interfacing with processors having multiple cores
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`that operate at various independent clock frequencies using, for example, DDR
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`protocols. I also developed delay locked loops in DDR memory. I provided
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`technical assistance with MTI’s acquisition of Photobit during 2001 and 2002,
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`including transitioning the manufacture of CIS products into MTI’s process
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`technology. Further, I did consulting work at Sun Microsystems and then Oracle
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`on the design of memory modules during 2009 and 2010. This work entailed the
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`design of low-power, high-speed, and wide interconnection methods with the goal
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`of transmitting data to/from the memory module and the MC at higher speeds.
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`13.
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`I have extensive experience in the development of instrumentation
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`and commercial products
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`in a multitude of areas
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`including:
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`integrated
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`electrical/biological circuits and systems, array (memory, imagers, and displays)
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`circuit design, CMOS analog and digital circuit design, diagnostic electrical and
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`electro-optic instrumentation for scientific research, CAD tool development and
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`online tutorials, low-power interconnect and packaging techniques, design of
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`communication/interface circuits (to meet commercial standards such as USB,
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`firewire, DDR, PCIe, SPI, etc.), circuit design for the use and storage of renewable
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`energy, and power electronics. For example, a part of my research at Boise State,
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`for many years, focused on the use of Thru-Silicon-Vias (TSVs), aka Thru-Wafer
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`Vias (TWVs), for high-density 3D packaging. These packaging techniques were
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`utilized in the memory module development work I did with Sun Microsystems
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`and Oracle. As another example, I designed circuitry for use in implementing
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`Universal Serial Bus (USB) interface circuits while I did consulting at Tower
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`Semiconductor. I designed PCI communication circuits for IPC between a
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`Graphics Processor Unit (GPU) and memory while consulting for Rendition, Inc.
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`in the late 1990s. The main processor and GPU ran at independent clock
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`frequencies which required the design of a phase-locked loop on the GPU. I did
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`similar work for Amkor also in the late 1990s. From 1994 to 1996, I worked on the
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`design of displays at Micron Display and MTI in Boise, Idaho. This work was at a
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`time when cathode ray tubes (CRTs) were still the dominant type of display. Flat
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`panel displays were being developed with the hope of replacing CRTs in the
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`consumer market. I worked on flat panel displays which resulted in 5 patents: U.S.
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`Patent Nos. 5,598,156, 5,638,085, 5,818,365, 5,894,293, and 5,909,201. I worked
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`on the design of the pixels, both active and passive, as well as the supporting
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`electronics for processing video signals. I was involved with the evaluation of
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`display technologies including liquid crystal displays (LCDs), light-emitting
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`diodes, plasma displays, and organic light emitting diode (OLED) displays; the
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`display technologies that were looking to displace CRTs in the consumer market. I
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`was also involved with the packaging of the displays including the vacuum sealing
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`and deposition of the phosphors for light wavelength conversion. I also taught
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`display design as a topic in my courses and did display design consulting again in
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`industry for Cirque in 2013.
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`14. My current research work is focused in part on the design of
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`integrated circuits for wireless sensing using LIDAR (LIght Detection And
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`Ranging). I have worked with several companies in the development of these
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`circuits and systems including Freedom Photonics, Aerius Photonics, and FLIR. In
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`the early 1990s, I worked on wireless systems for wideband impulse radar while at
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`Lawrence Livermore Laboratory. Further, part of my research for several years
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`focused on the digitization of IQ channels using delta-sigma modulation. The
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`knowledge and experience gained from this effort are reflected in my textbook
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`CMOS Mixed-Signal Circuit Design.
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`2.
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`Academic Experience
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`Inter Partes Review of U.S. Patent No. 7,646,835 B1
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`I was an adjunct faculty member in the Electrical Engineering
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`15.
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`departments of UNLV and University of Nevada, Reno (UNR) from 1991-1993.
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`From 1993 to 2000, I served on the faculty at the University of Idaho as an
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`Assistant Professor and then as a tenured Associate Professor of Electrical
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`Engineering. In 2000, I joined a new Electrical and Computer Engineering
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`program at Boise State University (“BSU”), where I served as department chair
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`from 2004 to 2007. At BSU, I helped establish graduate programs in Electrical and
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`Computer Engineering including, in 2006, the university’s second Ph.D. degree. In
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`2012, I rejoined the faculty at UNLV. Over the course of my career as a professor,
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`I have advised more than 100 masters and doctoral students.
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`16.
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`I have been recognized for my contributions as an educator in the
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`field. While at Boise State University, I received the President’s Research and
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`Scholarship Award (2005), Honored Faculty Member recognition (2003), and
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`Outstanding Department of Electrical Engineering Faculty recognition (2001). In
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`2007, I received the Frederick Emmons Terman Award (the “Father of Silicon
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`Valley”). The Terman Award is bestowed annually upon an outstanding young
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`electrical/computer engineering educator
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`in recognition of the educator’s
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`contributions to the profession. In 2011, I received the IEEE Circuits and Systems
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`Education Award. I received the Tau Beta Pi Outstanding Electrical and Computer
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`Engineering Professor Award every year it was awarded while I have been back at
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`UNLV.
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`17.
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`I have authored several books and papers in the electrical and
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`computer engineering area. My published books include CMOS Circuit Design,
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`Layout, and Simulation (Baker, R.J., Wiley-IEEE, ISBN: 9781119481515 (4th ed.,
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`2019)) and CMOS Mixed-Signal Circuit Design (Baker, R.J., Wiley-IEEE, ISBN:
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`9780470290262 (2nd ed., 2009) and ISBN: 9780471227540 (1st ed., 2002)). I co-
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`authored DRAM Circuit Design: Fundamental and High-Speed Topics (Keeth, B.,
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`Baker, R.J., Johnson, B., and Lin, F., Wiley-IEEE, ISBN: 9780470184752 (2008)),
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`DRAM Circuit Design: A Tutorial (Keeth, B. and Baker, R.J., Wiley-IEEE, ISBN:
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`0-7803-6014-1 (2001)), and CMOS Circuit Design, Layout and Simulation (Baker,
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`R.J., Li, H.W., and Boyce, D.E., Wiley - IEEE, ISBN: 9780780334168 (1998)). I
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`contributed as an editor and co-author on several other electrical and computer
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`engineering books.
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`3.
`Other Relevant Experience
`I have performed technical and expert witness consulting for more
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`18.
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`than 200 companies and their subsidiaries, and given more than 50 invited talks at
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`conferences, companies, and universities. Further, I am the author or co-author of
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`more than 100 papers and presentations in the areas of electrical and computer
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`engineering design, fabrication, and packaging.
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`I currently serve, or have served, as a volunteer on the IEEE Press
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`19.
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`Editorial Board (1999-2004); as editor for the Wiley-IEEE Press Book Series on
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`Microelectronic Systems (2010-2018); as the Technical Program Chair of the 2015
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`IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS
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`2015); on the IEEE Solid-State Circuits Society (SSCS) Administrative Committee
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`(2011-2016); as a Distinguished Lecturer for the SSCS (2012-2015); the
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`Technology Editor (2012-2014) and Editor-in-Chief (2015-2020) for IEEE Solid-
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`State Circuits Magazine; IEEE Kirchhoff Award Committee (2020-2023); and
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`advisor for the student branch of the IEEE at UNLV (2013-present). These
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`meetings, groups, and publications are intended to allow researchers to share and
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`coordinate research. My active participation in these meetings, groups, and
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`publications allowed me to see what other researchers in the field have been doing.
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`20.
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`In addition to the above, I am an IEEE Fellow for contributions to
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`semiconductor memory design and a member of the honor societies Eta Kappa Nu
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`and Tau Beta Pi.
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`Summary of Opinions and Materials Reviewed
`B.
`21. All of the opinions contained in this Declaration are based on the
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`documents I reviewed and my knowledge and professional judgment. In forming
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`the opinions expressed in this Declaration, while drawing on my knowledge and
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`experience in designing, developing, and researching high-speed computer
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`memory devices, I reviewed the following documents:
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`• ’835 Patent (Ex. 1001)
`• Prosecution History of ’835 Patent (Ex. 1003)
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`• U.S. Patent No. 6,434,081 B1 to Johnson et al. (“Johnson”) (Ex. 1004)
`• U.S. Patent No. 6,629,222 B1 to Jeddeloh (“Jeddeloh”) (Ex. 1005)
`• U.S. Patent No. 6,115,318 A to Keeth (“Keeth”) (Ex. 1006)
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`• Claim Construction Order, Intellectual Ventures I LLC et al. v. Lenovo
`Group Limited, 6:23-cv-307 (WDTX) (Ex. 1007)
`• Synchronous DRAM Architectures, Organizations, and Alternative
`Technologies by Bruce L. Jacob, published in December of 2002
`(“Jacob”) (Ex. 1008)
`• RAM Guide Part I: DRAM and SDRAM Basics by Jon Stokes, published
`in July of 2000 (“Stokes”) (Ex. 1009)
`• Design and PCB Layout Considerations for Dynamic Memories
`Interfaced to the Z80 CPU by Tim Olmstead, published in October of
`1996 (“Olmstead”) (Ex. 1010)
`• A Performance Comparison of Contemporary DRAM Architectures by
`Vinodh Cuppu et al., published in May of 1999 (“Cuppu”) (Ex. 1011)
`
`• How to Use DDR SDRAM by Elpida Memory, published in April of 2002
`(“Elpida”) (Ex. 1012)
`• Hyundai Electronics Actively Supplying DDR SDRAM Modules to Major
`PC Makers by SK hynix, published in March of 2001 (Ex. 1013)
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`• SLDRAM: High Performance, Open-Standard Memory by Peter
`Gillingham et al., published in December of 1997 (“SLDRAM”) (Ex.
`1014)
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`• 3.1. How Memory Works with the Processor by Technick, published in
`March of 1998 (Ex. 1015)
`• Memory Access Scheduling by Scott Rixner et al., published in March of
`2000 (Ex. 1016)
`• Computer-System Operation, published in July of 1999 (“Computer-
`System”) (Ex. 1017)
`• Course-to-fine Estimation of Visual Motion by Eero P. Simoncelli,
`published in September of 1993 (Ex. 1018)
`• Modern Dictionary of Electronics Seventh Edition by Rudolf F. Graf,
`published in February of 1999 (“Dictionary of Electronics”) (Ex. 1019)
`• Merriam-Webster’s Collegiate Dictionary Tenth Edition, published in
`2000 (“Merriam-Webster’s Dictionary”) (Ex. 1020)
`• Double Data Rate (DDR) SDRAM Specification by JEDEC Solid State
`Technology Association, published in June of 2000 (Ex. 1021)
`22. The opinions in this Declaration additionally are guided by my
`
`appreciation of how a POSITA (defined below in Section II(C)) would have
`
`understood the claims and specification of the ’835 Patent at the time of alleged
`
`invention of the ’835 Patent. I have been asked to assume that the time of alleged
`
`invention of the ’835 Patent is November 17, 2003, which is the filing date of the
`
`’320 application. The opinions below reflect how a POSITA would have
`
`understood the ’835 Patent, the prior art to the patent, and the state of the art at the
`
`time of alleged invention of the ’835 Patent.
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`12
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`17 of 212
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`Declaration of R. Jacob Baker, P.E., Ph.D.
`Inter Partes Review of U.S. Patent No. 7,646,835 B1
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`23. Based on my experience and expertise, it is my opinion that certain
`
`references disclosed all of the features recited in Claims 1-23 (“Challenged
`
`Claims”) of the ’835 patent, as I discuss in detail below.
`
`II. LEGAL STANDARDS FOR PATENTABILITY
`
`24.
`
`I am not an attorney and I offer no opinions on the law itself. My
`
`understanding of the relevant legal principles in this section is based on
`
`information provided to me by counsel.
`
`A. Anticipation
`I have been informed by counsel that under 35 U.S.C. § 102, for a
`25.
`
`claim to be invalid as “anticipated,” every limitation of the claim must be found in
`
`a single prior art reference, either expressly or inherently.
`
`B. Obviousness
`I have been informed by counsel that a patent claim may be found
`26.
`
`invalid under 35 U.S.C. § 103(a) if the subject matter of the claim as a whole
`
`would have been obvious to a hypothetical POSITA in view of a prior art reference
`
`or in view of a combination of references at the time of the alleged invention. I
`
`have been informed that obviousness is determined from the perspective of a
`
`POSITA and that the Challenged Claims should be read from the point of view of
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`such a person at the time the alleged invention was made. I have also been
`
`informed that a POSITA is assumed to know and to have all relevant prior art in
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`
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`13
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`18 of 212
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`Declaration of R. Jacob Baker, P.E., Ph.D.
`Inter Partes Review of U.S. Patent No. 7,646,835 B1
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`the field of endeavor covered by the patent in suit, and would thus have been
`
`familiar with each of the references cited herein, as well as the background
`
`knowledge in the art discussed in Section III(A), and the full range of teachings
`
`they contain.
`
`27.
`
`I have been informed of two criteria for determining whether a prior
`
`art reference is analogous and therefore qualifies as prior art: (1) whether the
`
`reference is from the same field of endeavor as the Challenged Claims, regardless
`
`of the problem addressed, and (2) if the reference is not within the field of
`
`endeavor of the Challenged Claims, whether the reference still is reasonably
`
`pertinent to the particular problem which the Challenged Claims purport to
`
`address. I have additionally been informed that the field of endeavor of a patent is
`
`not limited to a specific point of novelty, the narrowest possible conception of the
`
`field, or the particular focus within a given field. I have also been informed that a
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`reference may be reasonably pertinent to the Challenged Claims if, even though the
`
`reference may be in a different field than the Challenged Claims, the reference is
`
`one which logically would have commended itself to a patentee’s attention in
`
`considering his problem because of the subject matter with which the reference
`
`deals.
`
`28.
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`I further have been informed that whether an alleged invention would
`
`have been obvious should be analyzed in view of the scope and content of the prior
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`14
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`19 of 212
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`Declaration of R. Jacob Baker, P.E., Ph.D.
`Inter Partes Review of U.S. Patent No. 7,646,835 B1
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`art, the differences (if any exist) between the prior art references and the alleged
`
`invention, and the level of ordinary skill in the pertinent art involved. I have been
`
`additionally informed that a prior art reference should be viewed as a whole when
`
`performing the above analysis.
`
`29.
`
`I have been informed that in considering whether a claimed
`
`combination would have been obvious, I may assess whether there were apparent
`
`reasons to combine elements in the prior art in the manner claimed in view of
`
`interrelated teachings of one or more prior art references, the impact of demands
`
`known to the community or present in the market place, and/or the general
`
`knowledge possessed by a POSITA at the time of alleged invention. I have been
`
`informed that other principles may be relevant in evaluating whether an alleged
`
`invention would have been obvious, and that these principles may include the
`
`following:
`
`• A combination of prior art elements according to known methods is
`likely to be obvious when it does nothing more than yield predictable
`results;
`• When a known device or technology is available in one field of endeavor,
`design incentives and other market forces can prompt variations of it,
`either in the same field or in a different one, so that if a POSITA is able
`to implement a predictable variation, then that variation is likely obvious;
`• If a known technique has been used to improve a device, method, or
`product, and a POSITA would recognize that it would improve similar
`devices in the same predictable way, using the technique is obvious
`
`
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`15
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`20 of 212
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`Declaration of R. Jacob Baker, P.E., Ph.D.
`Inter Partes Review of U.S. Patent No. 7,646,835 B1
`
`unless the actual implementation of the technique is beyond his or her
`skill;
`
`• An explicit or implicit teaching, suggestion, or motivation in the prior art
`to combine the prior art references to form the claimed combination may
`demonstrate obviousness (but a teaching, suggestion, or motivation to
`combine is not a requirement for proving obviousness);
`• Market demand, rather than scientific literature, can drive design trends
`and may show obviousness;
`• In determining whether the subject matter of a patent claim would have
`been obvious, neither the motivation nor the purpose of the named
`inventor controls;
`• The subject matter of a patent may be proved obvious by demonstrating
`that there existed at the time of invention a known problem for which
`there was an obvious solution encompassed by the patent’s claims;
`• Any need or problem known in the field and addressed by the prior art
`can provide a reason for a POSITA at the time of the invention to
`combine the elements in the manner claimed;
`• “Common sense” indicates that known items and methods may have
`obvious uses beyond their primary purposes, and in many cases, a
`POSITA would be able to fit
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