(12) United States Patent
`Johnson et al.
`
`USOO6434081B1
`(10) Patent No.:
`US 6,434,081 B1
`45) Date of Patent:
`Aug. 13, 2002
`
`9
`
`(54) CALIBRATION TECHNIQUE FOR MEMORY
`DEVICES
`
`(75) Inventors: Brian Johnson; Brent Keeth, both of
`Boise, ID (US)
`s
`(73) Assignee: Micron Technology, Inc., Boise, ID
`(US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(*) Notice:
`
`(21) Appl. No.: 09/570,481
`(22) Filed:
`May 12, 2000
`(51) Int. Cl. .................................................. G11C 8700
`(52) U.S. Cl. ................... 365/233; 365/18707; 365/194
`(58) Field of Search ............................ 365/233, 18905,
`365/18907, 1890s, 194, 2300s
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`4.905,200 A
`2/1990 Pidsosny ............... 365/189.07
`5,386,392 A
`1/1995 Cantiant ..................... 365/233
`5.841,580 A 11/1998 Farmwald et al. .......... 365/194
`5,917,760 A 6/1999 Miller ................... 365/189.05
`5,923,613 A * 7/1999 Tien et al. .................. 365/233
`
`
`
`5,953,263 A 9/1999 Farmwald et al. .......... 365/194
`6,016,282 A 1/2000 Keeth ......................... 365/233
`6,035,365 A 3/2000 Farmwald et al. ..... 365/230.03
`6,038,195 A 3/2000 Farmwald et al. .......... 365/233
`6,041,419 A 3/2000 Huang et al. ............... 713/401
`6,067,592 A 5/2000 Farmwald et al. .......... 365/233
`6,101,152 A 8/2000 Farmwald et al. .......... 365/233
`6,154,821. A 11/2000 Barth et al. ................. 365/233
`6,295,246 B2
`9/2001 Jeddeloh ..................... 365/233
`OTHER PUBLICATIONS
`Gillingham; “SLDRAM Architectural and Functional Over
`view”, SLDRAM Consortium, Aug. 29, 1997, pp. 1-14.
`* cited by examiner
`Primary Examiner Trong Phan
`(74) Attorney, Agent, or Firm-Dickstein Shapiro Morin &
`Oshinsky LLP
`ABSTRACT
`(57)
`Disclosed is an improved Start-up/reset calibration apparatus
`and method for use in a memory device One of a plurality
`of data paths is bit wise calibrated relative to a clock signal
`and thereafter others of the plurality of data paths are bit
`wise aligned to a previously calibrated data path to produce
`Serial and parallel bit alignment on all data paths.
`
`104 Claims, 8 Drawing Sheets
`
`Petitioner Lenovo (United States) Inc. - Ex. 1004
`
`1 of 19
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`

`

`U.S. Patent
`
`Aug. 13, 2002
`
`Sheet 1 of 8
`
`US 6,434,081 B1
`
`
`
`FLAG
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`
`FIG. 1
`PRIOR ART
`
`
`
`FIG. 2
`PRIOR ART
`
`2 of 19
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`

`

`U.S. Patent
`
`Aug. 13, 2002
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`Sheet 2 of 8
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`US 6,434,081 B1
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`U.S. Patent
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`Aug.13, 2002
`
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`US 6,434,081 B1
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`Aug. 13, 2002
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`U.S. Patent
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`Aug. 13, 2002
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`Sheet 5 of 8
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`US 6,434,081 B1
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`
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`U.S. Patent
`
`Aug. 13, 2002
`
`Sheet 6 of 8
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`US 6,434,081 B1
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`7 of 19
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`U.S. Patent
`U.S. Patent
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`Aug. 13, 2002
`Aug. 13, 2002
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`

`

`1
`CALIBRATION TECHNIQUE FOR MEMORY
`DEVICES
`
`US 6,434,081 B1
`
`2
`calibrations are completed, can be used for normal memory
`READ and WRITE access.
`In prior Synchronizing Schemes using a calibration bit
`pattern as discussed above, all incoming data can properly
`be aligned with respect to the clock used to latch in the data
`by adjusting the data delays relative to the clock (CCLK or
`DCLK) to position a sampling clock edge at or near the
`center of the data “eye' or “window' where the data is valid
`on an incoming data path. However, this calibration proce
`dure is independently carried out for each incoming data
`path, which may take Some time and which also may, in
`extreme cases, cause the data “eye' on different incoming
`data paths to be aligned on different edges of the clock
`Signal.
`FIG. 1, for example, shows raw data coming into an
`SLDRAM module from a memory controller for a repre
`sentative FLAG data path, and three of the command bus
`data paths CA-0>, CA-12 and CA-2> (there are actually
`ten such data paths for the exemplary SLDRAM command
`bus). As shown, data positions arriving on each of the
`representative FLAG and CA-0>, CA-12 and CA-2> data
`paths are all skewed relative to one another.
`When the conventional calibration procedure is per
`formed using the 15 bit pseudo random pattern described
`above, each of the data bits on each of the incoming data
`paths is properly Serially aligned with an edge of clock
`signal CCLK, as shown in FIG. 2, for the exemplary data
`paths FLAG and CA-0>, CA-12 and CA-2>. That is, the
`clock edge CCLK is at or near the center of the data “eye'
`or “window” for each data bit on each data path. However,
`as is also shown in FIG. 2, it is possible that the data bits in
`one data path are misaligned, or aligned to an edge of the
`clock opposite to that of another data path. For example,
`while the position of data on the CA<0> data path and the
`data on the FLAG data path are properly aligned with each
`other, these two are misaligned with respect to the data bits
`on the CA-12 and CA-2> data paths. Thus, even though
`Serial calibration of each data line relative to the clock
`CCLK has been achieved, there is still a possibility for
`misalignment in a parallel direction acroSS all of the data
`paths.
`
`SUMMARY OF THE INVENTION
`The present invention provides correct alignment of data
`entering a memory module, e.g., an SLDRAM module, on
`a plurality of incoming data paths in both a Serial and
`parallel direction. Serial data alignment is first acquired for
`one of the incoming data paths, and then the remaining data
`paths are bit wise aligned in parallel to a previously aligned
`data path. In this way, Serial and parallel calibration of all
`data paths is achieved. This alignment may be performed,
`for example, at power-up or reset of the memory device.
`BRIEF DESCRIPTION OF THE DRAWINGS
`The above and other advantages and features of the
`invention will be more clearly understood from the follow
`ing detailed description of the invention which is provided
`in connection with the accompanying drawings in which:
`FIG. 1 illustrates raw data incoming on four different
`incoming data paths of a memory device,
`FIG. 2 illustrates a serial alignment of the data bits
`incoming on the different data paths shown in FIG. 1;
`FIG. 3 illustrates an SLDRAM bus topology with which
`the invention may be used;
`FIG. 4 illustrates a portion of the SLDRAM module
`shown in FIG. 3;
`
`15
`
`25
`
`FIELD OF THE INVENTION
`The present invention relates to an improved binary
`calibration technique which is useful for calibrating the
`timing of control and data Signals in memory devices, for
`example, SLDRAM memory devices.
`DISCUSSION OF THE RELATED ART
`Memory devices are constantly evolving in the directions
`of faster Speed and higher memory density. To this end,
`dynamic random access memory (DRAM) devices have
`evolved from simple DRAM devices to extended data out
`DRAM (EDO DRAM) to synchronous dynamic random
`access memory (SDRAM) to double data rate synchronous
`dynamic random access memory (DDR SDRAM) to Syn
`cLink dynamic random access memory (SLDRAM), the
`latter of which is the subject of much current industry
`interest. SLDRAM has a high Sustainable bandwidth, low
`latency, low power, user upgradability and Support for large
`hierarchical memory applications. It also provides multiple
`independent banks, fast read/write bus turn-around, and the
`capability for small fully pipelined bursts.
`One characteristic of SLDRAM is that it is a double data
`rate device which uses both the positive- and negative-going
`edges of a clock cycle to READ and WRITE data to the
`memory cells and to receive command and FLAG data from
`a memory controller.
`An overview of SLDRAM devices can be found in the
`specification entitled “SLDRAM Architectural and Func
`tional Overview,” by Gillingham, 1997 SLDRAM Consor
`tium (Aug. 29, 1997), the disclosure of which is incorpo
`rated by reference herein.
`Because of the required high Speed operation of
`SLDRAM, and other contemporary memory devices, sys
`tem timing and output signal drive level calibration at
`initialization, including Start-up or reset, is a very important
`aspect of the operation of Such devices to compensate for
`wide variations in individual device parameters.
`One of the Several calibration procedures which is per
`formed in current SLDRAM devices is a timing synchroni
`zation of clock signals CCLK (command clock signal) and
`DCLK (data clock signal) with data provided on an incom
`45
`ing command path CA and FLAG path (for the CCLK
`signal) and on the data paths DQ (for the DCLK signal) so
`that incoming data is correctly Sampled. Currently, a
`memory controller achieves this timing calibration at System
`initialization by sending continuous CCLK and DCLK tran
`Sitions on those clock paths and transmitting inverted and
`non-inverted versions of a 15 bit repeating pseudo random
`SYNC pattern “111101011001000” on each of the data paths
`DQ, the command path CA, and the FLAG path. The
`SLDRAM recognizes this pseudo random sequence by two
`consecutive ones “1” appearing on the FLAG bit and
`determines an optimal internal delay for CCLK and DCLK
`relative to the data each clocks to optimally Sample the
`known bit pattern. This optimal delay is achieved by adjust
`ing the temporal position of the received data bits to achieve
`a desired bit alignment relative to the clock. This is accom
`plished by adjusting a delay in the receiving path of the
`received data until the received data is properly Sampled by
`the clock and recognized internally. Once Synchronization
`has been achieved, that is, the proper delays on the data
`receiving paths have been Set, the memory controller Stops
`sending the SYNC pattern and the SLDRAM, after all
`
`35
`
`40
`
`50
`
`55
`
`60
`
`65
`
`10 of 19
`
`

`

`
`
`US 6,434,081 Bl
`
`4
`3
`FIG. 5 illustrates a simplified timing diagram illustrating
`
`
`
`
`The signal CCLK also passes from buffer 39 into a delay
`
`
`
`
`
`
`lock loop circuit 41 which provides 16 clock signals into a
`
`
`
`
`
`a portion of the timing signals used in the operation of the
`
`
`
`multiplexer 43. The multiplexer provides 18 clock output
`
`circuit of FIG. 4;
`
`
`
`
`signals through respective buffers 45 to 18 latches 49 which
`
`
`
`
`FIG. 6 illustrates a graphic example of the synchroniza­
`
`5 latch data output from the memory banks 69, 71. The output
`
`
`
`tion technique used to synchronize one data path of the
`data from memory banks 69, 71 pass into SRAMS 65, 67
`SLDRAM system of FIG. 3;
`
`
`which act as 1/0 buffers and pass through pipeline circuit 61
`FIG. 7 illustrates a pattern of acceptable delay values for
`
`
`
`
`
`
`
`
`before being loaded into latches 49. The output data latched
`
`synchronization used in the invention;
`
`
`
`
`in latches 49 is provided to respective buffer amplifiers 47
`
`
`
`
`
`FIG. 8 illustrates the serial and parallel alignment of data
`
`
`
`13 (FIG. 10 and from there is passed back to memory controller
`
`
`on the incoming data paths shown in FIG. 1;
`3) via data bus DQ.
`
`
`
`FIG. 9 illustrates an exemplary circuit for implementing
`Data which is to be input to memory banks 69, 71 is
`
`
`
`a first embodiment of the invention;
`
`
`supplied by memory controller 13 (FIG. 3) on the DQ data
`
`
`
`bus, is passed through gated buffers 51 through ring delays
`
`
`
`FIG. 10 illustrates an exemplary circuit for implementing
`
`
`59, through15 57 on each path of the data bus, into latches
`
`
`a second embodiment of the invention;
`
`
`pipeline circuit 63. From pipeline circuit 63, input data on
`
`
`
`FIG. 11 is a representative circuit for generating a 2N 16
`
`the DQ bus passes into buffer SRAM 65, 67 and into a
`
`bit code which may be used in the invention;
`memory bank 69, 71.
`
`
`
`FIG. 12 illustrates a processor based system using a
`The control logic circuit 21 also issues an enable com-
`
`
`
`
`memory device which employs calibration structures and
`
`
`
`indicates a 20 mand RXEN whenever the memory controller
`
`
`
`process methodologies in accordance with the invention.
`
`memory access WRITE operation by way of a WRITE
`DETAILED DESCRIPTION OF IBE
`
`command in the data on the command bus CA0---9. The
`
`PREFERRED EMBODIMENTS
`
`
`RXEN command enables the data input buffers 51 and a data
`An improved method of aligning a data path to a clock
`
`
`
`
`clock input buffer 53. The data clock DCLK passes through
`
`
`
`
`
`signal is described in detail in U.S. patent application Ser.
`
`25 gated buffer 53, delay circuit 55 and is used to control latch
`
`
`
`No. 09/568,155, filed May 10, 2000, the disclosure of which
`
`59 to latch in incoming data on the data bus DQ.
`
`
`
`is incorporated by reference herein. In order to provide
`
`
`
`
`In order to ensure proper timing of the various memory
`
`
`
`
`
`context for the present invention, relevant portions of that
`
`
`
`operations performed by the SLDRAM modules lla ... lln,
`
`application will now be described.
`
`
`
`
`the FIG. 4 circuit must be synchronized to ensure that the
`
`
`An SLDRAM system with which the present invention
`
`
`
`
`incoming data is properly clocked in by the clock signals
`30
`
`
`
`may be used is illustrated in FIG. 3. It includes a plurality of
`
`
`CCLK and DCLK To this end, and in accordance with an
`
`
`SLDRAM modules lla ... lln which are accessed and
`
`
`
`
`invention described in related application Ser. No. 09/568,
`
`
`
`controlled by a memory controller 13. Memory controller 13
`
`
`155, filed May 10, 2000, a 2N bit synchronizing pattern is
`
`provides a command link to each of the SLDRAM modules
`
`
`
`applied to each of the data input paths CA0-9 and FLAG
`
`
`lla ... lln which includes a clock signal CCLK on inverted
`
`
`
`while the data pattern is sampled in latches 23 and 25 by the
`35
`
`and non-inverted clock signal paths, a 1 bit FLAG signal on
`
`
`
`
`
`
`delayed clock signal CCLK. The control logic circuit 21
`a FLAG data path, and a 10 bit command bus data path
`
`
`
`
`
`
`steps through all possible delay positions of ring delays 27
`
`CA0-9. In addition, SLDRAM input/output enabling signals
`
`
`
`
`and 29 as the data sampling is performed and stores patterns
`
`SO, SI are provided from memory controller 13 in daisy
`
`
`
`
`
`
`representing which delay values for the ring delays 27 and
`chain fashion to the SLDRAM modules lla ... lln. In
`
`
`
`
`29 provide for a correct sampling and recognition of the 2
`40
`addition, a bi-directional data bus DQO-17 is provided
`
`
`
`
`
`bit pattern. In this manner, control logic circuit 21 estab-
`between memory controller 13 and each of the SLDRAM
`
`
`
`
`
`
`lishes an "eye" or "window" of acceptable delays for each
`
`modules lla . . . lln, as are bi-directional data clocks
`
`
`
`
`of the ring delays 27 for the command data paths CA0-9 and
`DCLKO and DCLKI. The clock DCLKO is used to strobe
`
`
`
`for ring delay 29 for the FLAG input path. Once a "window"
`
`
`
`input/output data into and out of the SLDRAM modules, a
`
`
`
`27 45 of acceptable delays is found for each of the ring delays
`
`
`
`process for which the DCLKl signal path is also intermit­
`
`
`and for the ring delay 29, the control logic circuit 21
`
`tently used.
`
`determines the "best" delay value as that value which is
`
`
`
`
`
`
`FIG. 4 illustrates a simplified relevant portion
`
`
`
`approximately of one of in the middle of the window. Although a 2N
`
`
`
`
`16 bit pattern is used for this purpose, as described above
`the SLDRAM modules lla ... lln. It includes a control
`
`
`
`
`by using a 2N-1 bit pattern, 50 calibration can also be achieved
`
`
`logic circuit 21, latches 23, 25, 49, 59, delay devices 27, 29,
`
`
`
`
`
`
`31, 55, 57 which may be ring delay devices, buffers 35, 37,
`
`
`for example, with a 15 bit pseudo random pattern, as
`
`
`
`39, 33, 45, 47, 51, 53, a delay lock loop 41, multiplexer 43,
`
`
`
`
`described in the SLDRAM specification referenced above.
`
`
`
`
`
`pipeline circuits 61, 63, SRAM input/output circuits 65 and
`
`
`
`To illustrate the calibration process, calibration of the data
`
`67, and respective memory banks Bank0 and Bankl 69, 71.
`
`
`
`appearing on the FLAG data path will be discussed using a
`
`
`
`It should be noted that although two memory banks are
`
`
`55 2N 16 bit synchronization pattern, it being understood that
`
`
`
`illustrated in FIG. 4, this is just illustrative, as any number
`
`
`
`the same calibration process may be carried out on any one
`
`
`
`of memory banks can be used. Control logic circuit 21
`
`of the data paths of the command bus CA0---9 and any one
`
`
`
`receives and analyzes commands on the CA0---9 bus and
`
`
`
`
`of the receive data paths of the data bus DQ ( although for the
`
`
`
`controls the input/output (1/0) access operations of the
`
`
`
`latter the DCLK signal is used for clocking). FIG. 5 illus-
`
`
`memory banks 69, 71. The control logic circuit 21 also
`
`
`
`60 trates a simplified timing diagram showing the timing rela­
`
`
`
`receives the FLAG signal, and the clock signals CCLK,
`
`
`
`tionship of the clock signal CCLK, the FLAG signal, the
`DCLK.
`
`
`
`command bus signal CMD, a data bus signal DQ/DBUS and
`
`The signals on each of the command bus paths CA0-9 are
`
`
`
`
`a data strobe signal DCLK. As shown, four bits of data on
`
`
`
`
`passed through respective adjustable ring delay circuits 27
`
`
`a DQ path of the data bus (DEUS) are clocked in on four
`
`
`
`and into respective latches 23 where the signals are latched
`
`
`
`65 sequential positive and negative going transitions of the data
`
`
`
`by a CCLKsignal, as buffered by buffer 39, delayed by delay
`
`
`clock signal DCLK after an initial PREAMBLE portion of
`
`31 and buffered by buffer 33.
`
`
`
`DCLK appears. The data present on the command signal
`
`N
`
`11 of 19
`
`

`

`S
`paths CA0-9 and on the FLAG path is clocked in by
`Sequential positive and negative going transitions of the
`command clock signal CCLK.
`Returning to FIG. 4, it can be seen that the data entering
`on the FLAG signal path passes through ring delay circuit 29
`and is latched in latch 25 by the command clock signal
`CCLK. This data is then serially applied to control logic
`circuit 21. During the calibration period, a known 2' bit
`Synchronization pattern is applied to the FLAG path by
`memory controller 13 (FIG. 3), together with the free
`running clock signal CCLK. The control logic circuit 21
`knows what the 2 bit calibration pattern is as it is stored
`and/or generated therein, and reads the incoming repeating
`pattern on the FLAG data path bit-by-bit from latch 25.
`When doing So, the control logic circuit 21 first Sets ring
`delay 29 for the FLAG path to one known delay setting. The
`control logic circuit 21 then examines the bit pattern Sequen
`tially received from latch 25 to see if it matches the known
`Synchronization bit pattern. If the timing of the Synchroni
`Zation pattern data on the FLAG path is not aligned with the
`transitions of the CCLK Signal, the correct bit pattern is not
`recognized at the output of latch 25 and the control logic
`circuit 21 will adjust ring delay 29 to the next delay Setting,
`offset by a given amount from the prior delay Setting of ring
`delay 29. Control logic circuit 21 will again continue to
`examine the bit pattern emerging from latch 25 to See if it
`matches the known Synchronization bit pattern. If not, it
`continues to increment the delay value of the ring delay 29
`and repeats the Sampling and examination proceSS until the
`correct 2 bit is recognized. In lieu of stopping the calibra
`tion process when the correct Synchronization bit pattern is
`recognized at the output of latch 25, the control logic circuit
`21 will actually Step through all possible delay values of ring
`delay 29 and keep track of which delays produced a proper
`recognition of the 2 bit synchronization pattern. Then the
`control logic circuit 21 will Select as a final delay value for
`ring delay 29, that value which is approximately centered
`between all delay values which produced a proper recogni
`tion of the 2 bit synchronization pattern.
`FIG. 6 illustrates the data envelope or “eye” for four
`consecutive bits <0><1><2><3> of the 2 bit synchroniza
`tion pattern together with the clock signals CCLK which
`latch the data in latch 25. The relative timing of the data
`envelope and the control data clock CCLK is illustrated as
`ten possibilities of CCLK1... 10, that is, ten possible delay
`values for ring delay 29. The beginning and end of the data
`envelope is where the data on the FLAG data path is
`unstable which leads to erroneous Sampling of the data. AS
`shown, reliable data capture occurs at the relative timing
`locations C through C-7, while unreliable data capture
`occurs at the relative timing locations C. . . . C. and C. . . .
`Co. These are represented within control logic circuit 21 as
`delay values D. . . . Dz, where the 2 bit synchronizing
`pattern was properly recognized.
`FIG. 7 illustrates how acceptable and unacceptable delay
`values are represented in control logic circuit 21 where delay
`values D. . . . D and Ds . . . Do Show a “0” logic State
`representing that the 2 bit Synchronization pattern was not
`recognized and the logic State “1” for delay values D. . . .
`D7, indicating a proper recognition of the 2 bit synchroni
`zation pattern. It should be understood that although only 10
`relative delay States of the data to the command clock signal
`CCLK are shown for Simplicity, in actual practice there may
`be many more possible delay states for ring delay 29 and the
`delay state pattern illustrated in FIG. 7.
`Once the delay state pattern shown in FIG. 7 is developed
`by control logic circuit 21, it Selects as a final delay for ring
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`delay 29 a delay value which is approximately in the center
`of those delay values, e.g., D. . . . Dz, which produced a
`proper recognition of the 2 bit synchronization pattern. In
`the example illustrated, the final delay would be Selected as
`Ds or D. Once this value is set for ring delay 29, the FLAG
`data path has been calibrated.
`Although the Same calibration procedure may also be
`applied to each of the CMD data paths CA0-9 and to each
`of the data paths of the DQ bus, (except that for the DQ bus,
`the data clock DCLK is used to latch the data in latch 59
`which is present in each of the data paths of the DQ data bus,
`as described above), this will not ensure parallel alignment
`of the data acroSS all of the incoming data paths.
`AS previously noted, in an extreme case the independent
`Serial alignment of the data paths can produce bit wise errors
`in the parallel direction of the data lines, which can be seen
`by comparing FIG. 2 with FIG. 8. FIG. 2 illustrates an
`example in which the FLAG, CA-0>, CA-12 and CA-2>
`data paths have each undergone Serial, but not parallel
`alignment. The result shows that each data path is aligned
`with the clock Such that rising and falling edges (shown at
`the top of FIG. 2) of the clock are aligned with the center of
`the respective data eye for each data path. However, the
`initial bits in the CA-12 and CA-2> data paths were serially
`aligned with an incorrect clock edge, resulting in parallel
`alignment errors relative to the other data paths.
`In contrast, FIG. 8 shows the same data paths FLAG,
`CA-0>, CA-12 and CA-2> after undergoing both serial
`and parallel alignment. Each data path has its data eye
`correctly centered on a rising or falling clock edge (serial
`alignment), and corresponding bits match across all data
`paths (parallel alignment).
`Accordingly, in the present invention, one of the data
`lines, e.g., FLAG, is first Serially calibrated using the pro
`cedures described above with reference to FIGS. 1-7. Then,
`instead of calibrating the remaining data lines in the same
`manner, the remaining data lines are calibrated to a previ
`ously calibrated data line, e.g., the FLAG data path. The
`manner of doing this will next be described with reference
`to FIGS. 9 and 10.
`FIG. 9 shows a portion of the control logic circuit 21 as
`including a plurality of compare circuits 73a, 73b, 73c for
`the illustrated data paths FLAG, CA-0>, CA-1d, and
`CA-2> which are representative of the data paths FLAG,
`and CA0-9 and DQ0-17. It should again be noted that while
`the FLAG and CA0-9 data paths are aligned to CCLK, the
`data paths DQ0-17 are aligned to DCLIK. Also illustrated
`are signals C1, C2, C3, C4 used by the logic 81 to control
`the delay settings of the ring delays 27, 29a, 29b, 29c,
`respectively. Additionally, VALID Signals are generated by
`the compare circuits 73a, 73b, 73c to signal whether the
`Synchronization pattern is properly recognized to the logic
`81.
`After one of the incoming data paths, e.g., FLAG, is
`Serially aligned in the manner described above with refer
`ence to FIGS. 1-7, the control logic circuit 21 then compares
`the newly aligned calibration pattern on the aligned data
`path, e.g., FLAG, with the calibration pattern from another
`data line, e.g., CA-0>, which is to be aligned. The control
`logic circuit 21 establishes an initial delay value for the ring
`delay 29a (via signal C2) of the CA-0> line and compares
`the outputs from the latch circuit 23 of the previously
`aligned data path with the latch circuit 25a of the data path
`undergoing calibration. If there is no pattern match, as
`detected by the compare circuit 73a, the control logic circuit
`21 will increment the ring delay 29a and again look for a
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`comparison of the calibration patterns emerging from
`latches 23 and 25a. This process of incrementing the ring
`delay 29a and looking for a match of the calibration patterns
`from latches 23 and 25a will continue until a match is found.
`Once a match is found, the control logic 21 will Still continue
`to increment the ring delay 29a and compare the calibration
`patterns and note if a match occurs until it increments the
`ring delay 29a through all its possible delay values, includ
`ing those where a pattern match is not found. This estab
`lishes a range of delays where the data on data path CA-0>
`is both Serially aligned as well as aligned in parallel with
`data on the FLAG data path. The control logic circuit 21 will
`then Set the delay value for ring delay 29a as a value at or
`near the center of the delay values which produced a match
`of the calibration patterns emerging from the latch circuits
`23 and 25a. While the data path CA-0> is being aligned to
`the previously aligned FLAG data path, the remaining data
`paths, e.g., CA-1Z or CA-2> can undergo an identical
`Simultaneous alignment (using the above described method
`modified for the appropriate data path, e.g., using Signals C3,
`C4, ring delays 29b, 29c, and latch circuits 25b, 25c for data
`paths CA-1>, CA-2>, respectively). In lieu of calibrating
`the remaining data paths simultaneously, it is also possible
`to Sequentially align each to the previously aligned FLAG
`data path.
`Alternatively, control logic circuit 21 can also be arranged
`to compare a next data path to be calibrated to a just
`calibrated data path and control the incremental adjustment
`of the ring delay for the new data path in the manner
`described above until a final delay value is selected. This is
`illustrated in FIG. 10, where a previously aligned data path,
`e.g., DQ-02 which includes ring delay 57a is aligned with
`a next in Sequence data path DQ-1> which includes ring
`delay 57b. The delay settings of the ring delays 57a, 57b,
`57c may be set by logic 87 using signals C10, C11, C12,
`respectively. This embodiment is illustrated using the data
`paths for the DQ0-17 data bus. Once a first data path, e.g.,
`DQ0, is serially aligned to DCLK using the technique
`described with reference to FIGS. 1-7, the remaining
`DQ1-17 data paths can then be aligned by comparing the
`calibration pattern of a Subsequent non-aligned data path to
`the calibration pattern which exists on a previously aligned
`data path. In one example, each data path can be aligned to
`an immediately preceding just aligned data path. Thus, if
`DQ0 is the first serially aligned data path, the next data path
`DQ1 is aligned to the previously aligned DQ0 path. To this
`end, control logic circuit 21 includes compare circuit 83a,
`which aligns the DQ1 data path including ring delay 57b to
`the previously aligned DQ0 data path which includes ring
`delay 57a by comparing the calibration pattern on aligned
`data path DQ0 with the calibration pattern on the DQ1 data
`path to generate an appropriate validity Signal on Signal lines
`VALID. As described above, the control logic circuit 21
`steps through all possible delay values of ring delay 57b, and
`notes those delayS which produce a coincidence of the
`calibration pattern on data paths DQ-0> and DQ-1>, and
`selects a final delay value for delay 57b which is at or near
`the center of acceptable delayS. Likewise, compare circuit
`83b aligns the calibration pattern on the data path DQ-2>
`including ring delay 57c with the calibration pattern on
`previously aligned data path DQ-1> which includes ring
`delay 57b.
`In a Similar manner other unaligned data paths DQ-X>
`are aligned to a precedingly aligned data path DQ-X-1>.
`The control logic circuit 21 thus Steps through all data paths,
`aligning the ring delays of a path under calibration to an
`immediate previously calibrated data path until all data paths
`have been calibrated.
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`AS noted, the Serial alignment procedure for the first data
`path, e.g., DQ-0>, may use the improved 2Y calibration
`pattern described in U.S. patent application Ser. No. 09/568,
`155, filed May 10, 2000 or the 21calibration of pattern
`described in the SLDRAM specification identified above.
`A circuit for generating the 2 bit calibration pattern,
`where N=4, to produce a repeating 16 bit pattern, is illus
`trated in FIG. 11. It includes a four stage shift register 51
`having bit positions <0><1><2><3>, NOR gate 53 having
`three inputs respectively connected to the <0><1><2> out
`puts of shift register 51, an exclusive OR gate 55 having two
`inputs respectively connected to the output <3> of shift
`register 51 and the output of NOR gate 53, and an exclusive
`OR gate 57 having a pair of inputs respectively connected to
`the output of exclusive OR gate 55 and the first stage output
`<0> of shift register 51. The output of exclusive OR gate 57
`is applied as an input to stage <0> of shift register 51. The
`clock signal CLK (or DCLK) is applied to shift register 51.
`The shift register 51 can initially be seeded with all Zeroes
`“0” at stages <0><1><2><3> and it will generate the repeat
`ing 16 bit pattern “1111010110010000.” This pattern is
`Similar to the 15-bit pseudo random pattern
`*111101011 OO 1000' described in the SLDRAM
`Specification, but includes an additional bit, e.g. a “0” added
`to the 15-bit pattern. In lieu of generating the repeating bit
`pattern with a circuit, the pattern can also be Stored in the
`memory controller 13 (FIG. 3) and repeatedly read out
`during calibration.
`A memory device containing the calibration Structure and
`operating as described above may be used in a processor
`based system of the type shown in FIG. 12. The processor
`based system 90 comprises a processor 94, a memory device
`96, and an I/O (input/output) device 92. The memory device
`96 contains the calibration Structure operating as described
`in accordance with the present invention. The memory
`device may be any type of DRAM device including an
`SLDRAM. In addition, the processor 94 may itself be an
`integrated processor which utilizes on-chip memory devices
`containing the calibration Structure and operates in accor
`dance with the present invention