United States Patent 19
`Keeth
`
`54) CLOCK VERNIER ADJUSTMENT
`
`75 Inventor: Brent Keeth, Boise, Id.
`
`73 Assignee: Micron Technology, Inc., Boise, Id.
`
`*
`
`Notice:
`
`This patent issued on a continued pros-
`ecution application filed under 37 CFR
`1.53(d), and is subject to the twenty year
`patent term provisions of 35 U.S.C.
`154(a)(2).
`
`21 Appl. No.: 08/759,351
`22 Filed:
`Dec. 3, 1996
`
`7
`
`USOO6115318A
`Patent Number:
`11
`45 Date of Patent:
`
`6,115,318
`9
`9
`Sep. S. 2000
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`Primary Examiner A. Zarabian
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`57
`ABSTRACT
`
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`
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`COMMAND BUS
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`- - - - - - - - - - - - - - - - -
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`Petitioner Lenovo (United States) Inc. - Ex. 1006
`
`1 of 19
`
`

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`3 of 19
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`U.S. Patent
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`U.S. Patent
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`6,115,318
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`Z09)
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`902909,
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`907
`XITO
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`12 of 19
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`CLOCK VERNIER ADJUSTMENT
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`delay. An edge triggered circuit receives data and the rising
`edge and falling-edge clock Signals, and Stores data at the
`rising-edge of the rising-edge clock signal and at the falling
`edge of the falling-edge clock signal.
`In one embodiment of the integrated circuit according to
`the present invention, the rising-edge and falling-edge
`delays are programmable delayS.
`In one embodiment of the integrated circuit of the present
`invention a rising-edge delay circuit receiving the input
`clock Signal and independently provides the rising-edge
`clock signal, and a falling-edge delay circuit receiving the
`input clock signal and independently provides the falling
`edge clock signal. In another embodiment of the integrated
`circuit, a rising-edge delay circuit receives the input clock
`Signal and provides the rising-edge clock signal, and a
`falling-edge delay circuit receives the rising-edge clock
`Signal and providing the falling-edge clock signal. In
`another embodiment of the integrated circuit, a falling-edge
`delay circuit receives the input clock signal and provides the
`falling-edge clock signal, and a rising-edge delay circuit
`receives the falling-edge clock signal and provides the
`rising-edge clock Signal.
`One form of the present invention is a memory System
`including a memory controller and memory modules for
`Storing data. A data bus carries write data from the memory
`controller to the memory modules and carries read data from
`the memory modules to the memory controller. A command
`buS carries commands from the memory controller to the
`memory modules. A clock line carries an input clock signal
`from the memory controller to the memory modules. Each
`memory module includes at least one Vernier clock adjust
`ment circuit receiving the input clock signal and providing
`a rising-edge clock signal representing the input clock signal
`delayed by a rising-edge delay and providing a falling-edge
`clock signal representing the input clock signal delayed by
`a falling-edge delay. Each memory module also includes at
`least one edge triggered circuit receiving read or write data
`and the rising-edge and falling-edge clock Signals, and
`Storing read or write data at the rising-edge of the rising
`edge clock signal and at the falling-edge of the falling-edge
`clock signal. Such Vernier adjustment circuitry can also be
`employed for clocking commands into the memory mod
`ules. The memory modules can include one or more memory
`integrated circuits, Such as dynamic random access memo
`ries (DRAMs).
`The Vernier clock adjustment circuitry and method
`according to the present invention more accurately and
`precisely compensates for the effects of duty cycle variation,
`bus position of a given memory device, timing drift, loading
`variations, clock jitter, clock skew, noise, overshoot, and
`ringing by individually adjusting both the rising-edge and
`falling-edge timings, either independently or interdepen
`dently from each other. As a result, data is accurately
`clocked in the memory devices even at higher data trans
`mission rates.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a block diagram of one embodiment of a
`memory System.
`FIG. 2 is a timing diagram illustrating the bus timing of
`the memory system of FIG. 1.
`FIG. 3 is a block diagram of another embodiment of a
`memory System.
`FIG. 4 is a timing diagram illustrating the bus timing of
`the memory system of FIG. 3.
`FIG. 5 is a block diagram of another embodiment of a
`memory System.
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`THE FIELD OF THE INVENTION
`The present invention relates generally to integrated
`circuits, and more particularly to clock adjustments in
`memory Systems, Such as memory Systems including
`dynamic random access memories (DRAMs).
`BACKGROUND OF THE INVENTION
`Integrated circuits typically include a number of input/
`output pins which are used for communication with addi
`tional circuitry. For example, an integrated memory device,
`Such as a dynamic random access memory (DRAM),
`includes both control inputs for receiving memory operation
`control Signals, and data pins for bidirectional data commu
`nication with an external System or processor.
`The data transmission rate of modern integrated circuits is
`primarily limited by internal circuitry operating Speeds. That
`is, communication networks have been developed which can
`transmit Signals between circuitry at a rate that is faster than
`the capacity of many integrated circuits. To address the need
`for faster circuits, a group of integrated circuits can be
`combined on a common bus and be controlled by a common
`controller. In this configuration, each integrated circuit oper
`ates in a coordinated manner with the other integrated
`circuits to share data which is transmitted at a high Speed.
`For example, a group of memory devices, Such as DRAMs,
`static RAMs, or read only memories (ROM), can be con
`nected to a common data bus and be controlled by a memory
`controller to form a memory system. The data rate of the bus
`may be Substantially faster than the feasible operating Speed
`of the individual memories. Each memory, therefore, is
`operated So that while one memory is processing received
`data, another memory is receiving new data. Such a memory
`System with an appropriate number of memory devices and
`an efficient memory controller can achieve very high Speed
`data transmissions.
`AS the transmission rate of the data communication
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`Signals in Such memory Systems continues to increase, new
`circuitry and methods are needed to accurately clock com
`mand data, write data, and read data transmitted between the
`memory controller and the memory devices. The portion of
`a clock cycle which can be devoted to clocking valid data
`becomes quite Small, and errors in clocking data can occur,
`at these increased transmission Speeds because of known
`effects Such as duty cycle Variation, buS position of a given
`memory device, timing drift, loading variations, clock jitter,
`clock skew, noise, OverShoot, and ringing.
`Therefore, for the reasons stated above, and for other
`reasons presented in greater detail in the DeScription of the
`Preferred Embodiments section of the present specification,
`there is a need in the art for a memory System which more
`accurately and precisely compensates for Such effects as
`duty cycle variation, buS position of a given memory device,
`timing drift, loading variations, clock jitter, clock skew,
`noise, overshoot, and ringing So that data can be accurately
`clocked in the memory devices.
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`SUMMARY OF THE INVENTION
`The present invention provides a method and integrated
`circuit including a vernier clock adjustment circuit receiving
`an input clock Signal and providing a rising-edge clock
`Signal representing the input clock signal delayed by a
`rising-edge delay and providing a falling-edge clock signal
`representing the input clock signal delayed by a falling-edge
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`FIG. 6 is a timing diagram illustrating the bus timing of
`the memory system of FIG. 5.
`FIG. 7 is a block diagram of a memory System having
`Vernier clock adjustment circuitry.
`FIG. 8A is a timing diagram illustrating an ideal Signal
`waveform.
`FIG. 8B is a timing diagram illustrating a non-ideal Signal
`waveform.
`FIG. 9 is a block diagram of an independent rising and
`falling edge Vernier clock adjustment System.
`FIG. 10 is a block diagram of an interdependent cascaded
`rising and falling edge Vernier clock adjustment System.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`In the following detailed description of the preferred
`embodiments, reference is made to the accompanying draw
`ings which form a part hereof, and in which is shown by way
`of illustration specific embodiments in which the invention
`may be practiced. It is to be understood that other embodi
`ments may be utilized and Structural or logical changes may
`be made without departing from the Scope of the present
`invention. The following detailed description, therefore, is
`not to be taken in a limiting Sense, and the Scope of the
`present invention is defined by the appended claims.
`The following described embodiments of the present
`invention are described as applied to a dynamic random
`access memory (DRAM) and memory Systems including
`DRAMs. The present invention can, however, be imple
`mented in any integrated circuit and other memory Systems
`including other types of memory integrated circuits. The
`DRAM according to the present invention is similar in many
`respects to conventional DRAMS, Such as those commer
`cially available from Micron Technology, Inc. of Boise, Id.
`For clarity, only a portion of the well known circuitry of the
`DRAM is described herein, while the new circuitry of the
`DRAM of the present invention is described in detail herein.
`Overview of Memory Systems
`A memory system is illustrated generally at 20 in FIG. 1.
`Memory system 20 includes a memory controller 22 and N
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`DRAM modules Such as indicated at 24 and 26. The DRAM
`modules, Such as modules 24 and 26, each comprise at least
`one DRAM device. A command bus 28 is an unidirectional
`bus for carrying address and control information from
`memory controller 22 to the DRAM modules. Address and
`control information is typically transferred from memory
`controller 22 on command bus 28 in uniform packets. For
`example, if a packet is four times the width of command bus
`28, a command packet is transferred in four cycles on each
`edge of a free-running clock (CCLK) provided on a clock
`line 30 from memory controller 22. A data bus 32 is a
`bidirectional bus carrying write data from memory control
`ler 22 to the DRAM modules and further carrying read data
`from the DRAM modules to memory controller 22. Two
`bidirectional data clocks, DCLKO and DCLK1, are respec
`tively provided on clock line 34 and clock line 36.
`Data clocks DCLK0 and DCLK1 are used to precisely
`transfer read data timing from the DRAM modules to the
`memory controller 22 and to further precisely transfer write
`data timing from memory controller 22 to the DRAM
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`modules. Both rising edge and falling edge transitions of the
`selected DCLK are employed to clock the input latches of
`the DRAM modules and memory controller receiving data.
`The data clocks DCLK0 and DCLK1 follow the same path
`as data provided on data bus 32 to reduce the effects of clock
`jitter, duty cycle Variation, bus position, drift timing, and
`loading variations.
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`When control of data bus 32 is transferred from one
`device in memory System 20 to another device in memory
`system 20, such as from memory controller 22 to DRAM
`module 24, from DRAM module 24 to memory controller
`22, or from DRAM module 24 to DRAM module 26, one
`DCLK is deactivated and the other DCLK is activated.
`Memory controller 22 determines which DCLK is to be used
`for a given read or write operation and provides the infor
`mation indicating which DCLK to use in the command
`packet provided on command buS 28.
`Memory system 20 accommodates for minimum and
`maximum delays from command at memory controller 22 to
`read data at memory controller 22 from the different DRAM
`modules by programming Vernier clock adjustment circuits
`in each DRAM module. Preferably, the vernier adjustments
`in each DRAM module provide coarse steps defined in bit
`periods and fine Steps to cover adjustments within a single
`bit period.
`FIG. 2 is a timing diagram illustrating bus timing for
`memory system 20. As illustrated in FIG. 2, CCLK has a
`falling or rising edge transition every T nanoseconds (Nsec).
`For example, T is 2.5 Nsec in one embodiment of memory
`system 20. FIG. 2 illustrates a sequence of four Tread and
`write first operations. The buS propagation delay from
`command bus 28 at memory controller 22 to command bus
`28 at a DRAM module is shown to be a maximum of one
`clock transition of the CCLK (1 T).
`As illustrated in FIG. 2, the DRAM module performs an
`internal ReadO operation at time 17 T. The DRAM module
`Vernier clock adjustment is programmed to provide read data
`beginning at time 29 T, So that read data arrives at memory
`controller 22 at time 30 T. With the programmed vernier
`clock adjustment in each DRAM module, the loop-around
`delay from command to data burst at memory controller 22,
`for both read and write operations is maintained at 30 T. The
`DRAM module provides a read data clock to memory
`controller 22 with the DCLKO on clock line 34.
`A 2 T time gap is inserted between the read0 command
`burst operation and a write1 command burst operation to
`permit control of data bus 32 to be transferred from memory
`controller 22 to the DRAM module. Thus, write data is
`provided at time 36 T at memory controller 22 which
`correspondingly arrives at the DRAM module at time 37 T.
`An internal write operation is performed immediately on the
`received write data at the DRAM module at time 41 T.
`Memory controller 22 provides a write data clock to the
`DRAM module with the DCLK1 on clock line 36.
`A sequence of gapless read burst commands (i.e., read2,
`read3, and read4) follow the write1 command. The read2-4
`burst commands are transmitted to a single DRAM module.
`Thus, timing gaps are not required in the Sequence of read
`burst commands because the same device is driving data bus
`32 during all of these read operations. A 6 T gap is inserted
`between the write1 command and the first read command of
`the sequence of read commands (i.e., read2 command) to
`permit bus Settling.
`Memory system 20 may include only one DRAM device
`per DRAM module. A memory system which includes
`several DRAM devices per DRAM module is illustrated
`generally at 120 in FIG. 3. Memory system 120 includes a
`memory controller 122 and N DRAM modules, such as
`indicated at 124 and 126. The DRAM modules, such as
`modules 124 and 126, each comprise MDRAM devices. A
`command buS 128 is a unidirectional bus for carrying
`address and control information from memory controller
`122 to the DRAM modules. Address and control information
`is typically transferred from memory controller 122 on
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`command buS 128 in uniform packets on both rising and
`falling edges of a free-running clock (CCLK) provided on a
`clock line 130 from memory controller 122. Data busses
`132a-m are bidirectional buSSes carrying write data from
`memory controller 122 to the DRAM modules and further
`carrying read data from the DRAM modules to memory
`controller 122. Two bidirectional data clocks, DCLKO and
`DCLK1, are respectively provided on clock lines 34a–m and
`clock lines 36a-m.
`DRAM module 124 includes a command buffer 140 for
`buffering commands from command bus 128 to be provided
`to M DRAM devices such as indicated at 142a and 142m.
`Similarly, the Nth DRAM module indicated at 126 includes
`a command buffer 144 which buffers commands from com
`